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Publication numberUS7055122 B1
Publication typeGrant
Application numberUS 10/118,459
Publication date30 May 2006
Filing date5 Apr 2002
Priority date5 Apr 2002
Fee statusPaid
Publication number10118459, 118459, US 7055122 B1, US 7055122B1, US-B1-7055122, US7055122 B1, US7055122B1
InventorsAlex Tain, Eric Tosaya
Original AssigneeCisco Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for automatically connecting top side conductors with bottom side conductors of an integrated circuit package
US 7055122 B1
Abstract
A method for logically connecting at least one of a plurality of top side conductors of an integrated circuit package with at least one of a plurality of bottom side conductors of the integrated circuit package. The method includes drawing a layout of the bottom side conductors, and drawing a layout of the top side conductors. One or more rings of the top side conductors are defined, and one or more rings of the bottom side conductors are defined. One or more signal sets of the top side conductors are defined, each of said signal sets contains at least two or more top side conductors. The user can select a region of top side conductors to be connected with a region of bottom side conductors, and the selected region of top side conductors is automatically connected with the selected region of bottom side conductors while maintaining the signal set relations. In this manner, the logical connection between the top and bottom side conductors of an integrated circuit package are automatically connected while maintaining the relationship between the signal sets defined by the user. A netlist can be generated of the logical connections made by the connecting operation.
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Claims(27)
1. In a computer, a method of selecting connectivity routing from a plurality of top side conductors of an integrated circuit package with a plurality of bottom side conductors of the integrated circuit package, the method comprising:
defining a ring of the top side conductors from a layout of the top side conductors using a graphical user interface, wherein the ring of the top side conductors contains one row of top side conductors;
defining a top signal set containing a plurality of X top side conductors arranged in a linearly adjacent relation in a first direction and located in the one row of the ring of top side conductors;
defining a ring of the bottom side conductors from a layout of the bottom side conductors using the graphical user interface, wherein the ring of the bottom side conductors contains at least X rows of bottom side conductors; and
selecting the connectivity routing to electrically connect the top signal set to a bottom signal set of the bottom side conductors while maintaining the top signal set linear adjacent relation, wherein bottom signal set is arranged in a linearly adjacent relation orthogonal to the first direction.
2. In a computer-aided design of an integrated circuit package, a method of logically connecting at least one of a plurality of top side conductors of the integrated circuit package with at least one of a plurality of bottom side conductors of the integrated circuit package, comprising:
drawing a layout of the bottom side conductors;
drawing a layout of the top side conductors;
defining one or more rings of the top side conductors, wherein each one of the rings of the top side conductors contains one row of conductors;
defining one or more rings of the bottom side conductors, wherein each one of the rings of the bottom side conductors contains three rows of conductors;
defining one or more signal sets of the top side conductors, each of said signal sets contains at least two or more adjacent top side conductors having a relative linear physical relations;
providing a graphical user interface for a user to select a region of top side conductors to be connected with a region of bottom side conductors; and
logically connecting the selected region of top side conductors to the selected region of bottom side conductors while maintaining the signal set relative linear physical relations, wherein the signal sets of the top side conductors are orthogonal to the signal sets of the bottom side conductors.
3. The method of claim 2, wherein at least one of said signal sets includes a pair of top side conductors arranged as a differential pair.
4. The method of claim 3, wherein the at least one of said signal sets includes a positive signal of the differential pair assigned to a first top side conductor, a negative signal of the differential pair assigned to a second top side conductor, and a ground signal assigned to a third top side conductor.
5. The method of claim 4, wherein the first top side conductor is adjacent to the second top side conductor.
6. The method of claim 4, wherein the first top side conductor is adjacent to the second top side conductor, and the second top side conductor is adjacent the third top side conductor.
7. The method of claim 4, wherein the first, second, and third top side conductors are co-linearly arranged.
8. The method of claim 3, wherein the at least one of said signal sets includes a positive signal of the differential pair assigned to a first top side conductor, a negative signal of the differential pair assigned to a second top side conductor, and a power signal assigned to a third top side conductor.
9. The method of claim 8, wherein the first top side conductor is adjacent to the second top side conductor.
10. The method of claim 8, wherein the first top side conductor is adjacent to the second top side conductor, and the second top side conductor is adjacent the third top side conductor.
11. The method of claim 8, wherein the first, second, and third top side conductors are co-linearly arranged.
12. The method of claim 2, wherein the one or more rings of the top side conductors are defined concentrically.
13. The method of claim 2, wherein the one or more rings of the bottom side conductors are defined concentrically.
14. The method of claim 2, further comprising:
generating a netlist of the logical connections made by the connecting operation.
15. In a computer, a method of connecting a plurality of top side conductors of an integrated circuit package with a plurality of bottom side conductors of the integrated circuit package, comprising:
drawing a layout of the top side conductors;
defining one or more rings of the top side conductors, wherein each one of the rings of the top side conductors contains one row of conductors;
drawing a layout of the bottom side conductors;
defining one or more rings of the bottom side conductors, wherein each one of the rings of the bottom side conductors contains three rows of conductors;
defining one or more signal sets of the top side conductors, each of said signal sets contains at least two or more top side conductors arranged in a linearly adjacent relation in an X-direction;
providing a graphical user interface for a user to select a region of top side conductors to be connected with a region of bottom side conductors; and
connecting the selected region of top side conductors to the selected region of bottom side conductors, such that the one or more signal sets of the top side conductors are connected to one or more signal sets of the bottom side conductors while maintaining the signal set linear adjacent relation, wherein bottom side conductors are arranged in a linearly adjacent relation in a Y-direction that is orthogonal to the X-direction.
16. The method of claim 15, wherein at least one of said signal sets includes a pair of top side conductors arranged as a differential pair.
17. The method of claim 16, wherein the at least one of said signal sets includes a positive signal of the differential pair assigned to a first top side conductor, a negative signal of the differential pair assigned to a second top side conductor, and a ground signal assigned to a third top side conductor.
18. The method of claim 17, wherein the first top side conductor is adjacent to the second top side conductor.
19. The method of claim 17, wherein the first top side conductor is adjacent to the second top side conductor, and the second top side conductor is adjacent the third top side conductor.
20. The method of claim 17, wherein the first, second, and third top side conductors are co-linearly arranged.
21. The method of claim 16, wherein the at least one of said signal sets includes a positive signal of the differential pair assigned to a first top side conductor, a negative signal of the differential pair assigned to a second top side conductor, and a power signal assigned to a third top side conductor.
22. The method of claim 21, wherein the first top side conductor is adjacent to the second top side conductor.
23. The method of claim 21, wherein the first top side conductor is adjacent to the second top side conductor, and the second top side conductor is adjacent the third top side conductor.
24. The method of claim 21, wherein the first, second, and third top side conductors are co-linearly arranged.
25. The method of claim 15, wherein the one or more rings of the top side conductors are defined concentrically.
26. The method of claim 15, wherein the one or more rings of the bottom side conductors are defined concentrically.
27. The method of claim 15, further comprising:
generating a netlist of the logical connections made by the connecting operation.
Description
CROSS-REFERENCE TO RELATED APPLICATION

This application is related to co-pending, commonly assigned U.S. patent application Ser. No. 11/136,036, filed contemporaneously herewith, entitled “METHOD FOR AUTOMATICALLY ROUTING CONNECTIONS BETWEEN TOP SIDE CONDUCTORS AND BOTTOM SIDE CONDUCTORS OF AN INTEGRATED CIRCUIT PACKAGE” by Alex Tain and Eric Tosaya, the disclosure of which is herein incorporated by reference in its entirety.

FIELD OF THE INVENTION

This invention relates, in general, to logically connecting top and bottom side conductors during the design of an integrated circuit package.

BACKGROUND OF THE INVENTION

In the design of packaging for integrated circuits (ICs), a die (having an integrated circuit thereon) is electrically and physically connected to a package. The package has top side conductors, a body portion, and bottom side conductors.

FIG. 1 shows an example of a die 20 and a package 22, wherein the die is a “flip chip” with an interconnect medium 24 (i.e., solder bumps, balls, posts, etc.) thereon, and the package has top side conductors 26, such as pads, for electrical connection to the die, and bottom side conductors 28 for electrical connection with a printed circuit board (PCB), an IC socket, or the like. The bottom side conductors 28 can be in the form of, for example, metallized pads, pins, balls, or columns which are to connect the package to the PCB or IC socket. The bottom side conductors 28 can be integral to the package, or can be provided by or assembled using a solder column interposer.

The body of the package 22 provides, among other things, routing of the top side conductors 26 to the bottom side conductors 28. In complex IC designs, the die 20 may have thousands of interconnect sites (i.e., solder bumps) thereon, while the package accordingly has thousands of top side conductors 26 and bottom side conductors 28. Further, the package may be comprised of multiple layers (i.e., twenty or more) of ground planes, power planes, or signal distribution layers, which are used to route the connections between the top side conductors to the bottom side conductors.

As recognized by the present inventors, it can be very difficult and time consuming to design the logical connections between the top side conductors 26 to the bottom side conductors 28, particularly where relationships such as electrical and physical constraints between the groups of signals lines need to be maintained throughout the package, as with the case of very high frequency signal lines. Such logical connections are conventionally designed by a package engineer using manual data entry to manually connect each top side conductor to each bottom side conductor—such as by manually “pointing and clicking” between two conductors within a software design tool. While commercially available design tools can automatically assign these connections, such tools have severe limitations in their ability to follow the required electrical and physical design constraints.

As recognized by the present inventors, what is needed is a method for automatically making logical connections between top side conductors and bottom side conductors of an IC package, while maintaining the relative relationships between groups of signal lines as needed.

It is against this background that various embodiments of the present invention were developed.

SUMMARY OF THE INVENTION

In light of the above and according to one broad aspect of one embodiment of the present invention, disclosed herein is a method for logically connecting at least one of a plurality of top side conductors of an integrated circuit package with at least one of a plurality of bottom side conductors of the integrated circuit package. The method includes drawing a layout of the bottom side conductors, and drawing a layout of the top side conductors. One or more rings or rows or columns of the top side conductors are defined, and one or more rings or rows or columns of the bottom side conductors are defined. One or more signal sets of the top side conductors are defined, each of said signal sets contains at least two or more top side conductors. The user can select a region of top side conductors to be connected with a region of bottom side conductors, and the selected region of top side conductors is automatically connected with the selected region of bottom side conductors while maintaining the signal set relations. In this manner, the logical connection between the top and bottom side conductors of an integrated circuit package are automatically assigned while maintaining the relationship between the signal sets defined by the user. A netlist can be generated of the logical connections made by the connecting operation.

In one embodiment, the one or more rings of the top side conductors are defined concentrically, and each of the one or more rings of the top side conductors contains a single row of top side conductors along each side of the package. In one embodiment, each of the one or more rings of the bottom side conductors contains a three rows of bottom side conductors along each side of the package, and the one or more rings of the bottom side conductors are defined concentrically.

In one embodiment, the signal sets each include a pair of top side conductors arranged as a differential pair, such as a positive signal of the differential pair assigned to a first top side conductor, a negative signal of the differential pair assigned to a second top side conductor, and a ground or power signal assigned to a third top side conductor. In one embodiment, the first, second, and third top side conductors are co-linearly arranged.

Other features, utilities and advantages of the various embodiments of the invention will be apparent from the following more particular description of embodiments of the invention as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a die and a package of an integrated circuit.

FIG. 2 illustrates the logical operations for automatically connecting top side conductors to bottom side conductors of an integrated circuit package, in accordance with one embodiment of the present invention.

FIG. 3 illustrates the logical operations for drawing the bottom side of the package, in accordance with one embodiment of the present invention.

FIG. 4A illustrates a sample display of a drawing of the bottom side of an example package.

FIG. 4B illustrates a sample display of a drawing of the bottom side of another example package.

FIG. 5 illustrates the logical operations for drawing the top side of the package, in accordance with one embodiment of the present invention.

FIG. 6A illustrates a sample display of a drawing of the top side of an example package.

FIG. 6B illustrates a sample display of a drawing of the top side of another example package.

FIG. 7A illustrates an example of a drawing layout of a top side of the package with rings shown therein, in accordance with one embodiment of the present invention.

FIG. 7B illustrates another example of a drawing layout of a top side of another package with rings shown therein, in accordance with one embodiment of the present invention.

FIG. 8 illustrates an example of a drawing layout of a bottom side of the package with rings shown therein, in accordance with one embodiment of the present invention.

FIG. 9 illustrates an example of a portion of bottom side conductors, and a portion of top side conductors arranged in signal sets, in accordance with one embodiment of the present invention.

FIG. 10 illustrates a sample display of a user-selection of a region of top side conductors selected to be connected to a region of bottom side conductors, in accordance with one embodiment of the present invention.

FIG. 11 illustrates logical operations for automatically connecting top side conductors to bottom side conductors of an integrated circuit package, in accordance with one embodiment of the present invention.

FIG. 12 illustrates logical operations for connecting top side conductors to bottom side conductors, in accordance with one embodiment of the present invention.

FIGS. 13A–J illustrate an example of a process for connecting top side conductors with bottom side conductors, in accordance with one embodiment of the present invention.

FIG. 14 illustrates a block diagram of a software architecture having various modules to perform the operations described, in accordance with one embodiment of the present invention.

FIG. 15 illustrates one example of a net list generated, in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

Disclosed herein is a method and computer program product for automatically making logical connections between the top side conductors 26 and the bottom side conductors 28 of an integrated circuit package 22, an example of which is shown in FIG. 1. In accordance with embodiments of the present invention, the top side conductors are automatically logically assigned to or connected with bottom side conductors while preserving the relative relationships specified by a user as to how sets or groups of signal lines should be positioned relative to one another.

As used herein, the term “bottom side conductors” or “pins” 28 refers to the conductors on the package 22 that are positioned to be connected with the printed circuit board or with an IC socket. Bottom side conductors include but are not limited to, for example, metallized pads, pins, balls, or columns, or the like, and these terms are used interchangeably herein to generally refer to a bottom side conductor.

As used herein, the term “top side conductors” or “pads” 26 refers to the conductors on the package 22 that are positioned to be connected with the conductors of the die 20. Top side conductors include but are not limited to, for example, pads that are adapted to be electrically connected with a corresponding conductor of the die—such as a flip chip (FC) solder ball.

The term “logical connection” refers to a representation of a physical connection between two conductors. In one example, a logical connection between a particular top side conductor and a particular bottom side conductor indicates that a physical connection between the two conductors should be made within the package.

Referring now to FIG. 2, one example of the logical operations for automatically connecting top side conductors 26 to bottom side conductors 28 of an integrated circuit package 22 is shown. At operation 1, the layout of the bottom side conductors of the package is created, based on various inputs describing the package, as will be discussed with reference to FIGS. 3–4. The layout of the bottom side conductors is drawn and displayed in a graphical user interface (GUI), so that a user can see and manipulate the image of the bottom side conductors of the package.

At operation 2, the layout of the top side conductors of the package is created, based on various inputs describing package and the footprint of the die, as will be discussed with reference to FIGS. 5–6. The layout of the top side conductors is drawn and displayed in a GUI, so that a user can see and manipulate the image of the top side conductors of the package.

Operations 1 and 2 of FIG. 2 will now be described with reference to FIGS. 3–4 and 56, respectively. FIG. 3 illustrates the logical operations for creating a view of the bottom side of an IC package, in accordance with one embodiment of the present invention.

At operation 1 of FIG. 3, data about the package is obtained. In one example, the data obtained includes the package outside dimensions, the geometries of the bottom side conductors (such as the diameter of the pin lands and the distance between the centers of the pins (pin pitch)), and the pin matrix size of the bottom side conductors (such as 8×8).

At operation 2 of FIG. 3, the corner pins are removed so that they will not be displayed or used, and at operation 3, the pins are staggered, if desired. Operations 2 and 3 of FIG. 3 are optionally performed, if desired by the user, so that the computer model of the package matches the physical layout of the actual package. Alternatively, if the footprint of the bottom side conductors of the package is available, it can be used in place of operations 13.

At operation 4, the Pin A1 identification is made—for example, the user selects which pin of the package is the “A1” pin (also commonly referred to as the Pin #1 corner)—and at operation 5, the remaining pins are labeled, in one example using JEDEC pin labeling conventions. At operation 6, the power (i.e., VDD) and ground pins (i.e., VSS) of the package are identified.

At operation 7, a view of the bottom side of the package is generated and displayed to the user, and in one example the view generated is based on the data obtained from operations 16. FIGS. 4A and 4B illustrate views of different examples of packages—in FIG. 4A, a very simple package having sixty bottom side conductors 28, and in FIG. 4B, a larger package having 1,924 bottom side conductors 28. In one example, the view generated and displayed to the user of the bottom side conductors is drawn looking through the top side of the package as if the package material were transparent.

The logical operations for generating a model or view of the top side conductors of the package are shown in FIG. 5. At operation 1, geometric data about the top side conductors is obtained. In one embodiment, a text file of the die is read to obtain, for each conductor of the die, the signal_name, the X coordinate of the conductor, and the Y coordinate of the conductor. From this information, the geometries of the top side of the package can be derived. At operation 2, the data obtained from operation 1 is manipulated so that the footprint of the die can be superimposed on the top side of the package. In one embodiment, a mirror function is performed (which conceptually flips the image about the X or Y axis as needed), and the image is rotated or scaled (reduced or enlarged) as needed. At operation 3, the flip chip pad geometry of the die is obtained (such as the flip chip pad diameters or dimensions), so that each of the top side conductors of the package can be properly selected and sized to support the corresponding flip chip die pad geometry according to normal practices. Alternatively, if the footprint of the top side conductors is available, it can be used in place of operations 13.

At operation 4 of FIG. 5, the “A1” top side conductor is identified, and at operation 5, the remaining top side conductors are labeled, in one embodiment using conventional JEDEC labeling conventions. At operation 6, a view of the top side of the package is generated and displayed to the user, and in one example the view generated is based on the data obtained from operations 15. FIGS. 6A and 6B illustrate views of different examples of packages—in FIG. 6A, the package has forty-four top conductors 26, and in FIG. 6B, the package has 2,499 top conductors 26. In one example, the view generated and displayed to the user is drawn looking through the top side of the package.

Now referring again to FIG. 2, at operation 3 one or more rings are defined for the top side conductors. These rings are groupings of rows of conductors, and in one embodiment a ring includes a single row of top side conductors, as will be described with reference to FIGS. 7A and 7B. In one embodiment, the rings are labeled as in ascending order beginning from the outer rows of the top side conductors (Ring 1, shown as 70) to the inner rows of top side conductors (Ring 2 (shown as 72), Ring 3 (shown as 73), Ring 4 (shown as 74), etc.), as shown in FIGS. 7A and 7B. In one example, a ring includes all of the conductors of a row along all sides of the top side conductors (see FIGS. 7A and 7B) so that each signal in the ring can be later routed to the corresponding bottom side conductor using a via from the ring down to a particular routing layer within the package.

At operation 4 of FIG. 2, one or more rings are defined for the bottom side conductors. These rings are groupings of rows of conductors, and in one embodiment a ring includes three rows of bottom side conductors, as shown in FIG. 8. In one embodiment, the rings are labeled as in ascending order beginning from the outer three rows of the bottom side conductors (Ring 1), to the next 3 inner rows of bottom side conductors (Ring 2), to the next 3 inner rows of bottom side conductors (Ring 3), to the next 3 inner rows of bottom side conductors (Ring 4), etc., as shown in FIG. 8. In one embodiment, a ring includes all of the conductors of three rows along all sides of the bottom side conductors of the package, as shown in FIG. 8, excepting the conductors about a corner, which are excluded. In one embodiment, the unused bottom side conductors are logically connected to ground.

At operation 5 of FIG. 2, one or more signal sets for the top side conductors are defined. A signal set is a set or grouping of top side conductors. In one embodiment, one or more portions of the top side conductors are arranged in signal sets, wherein each signal set includes three top side conductors. Such an arrangement of signal sets can provide for differential pair groupings to enhance signal integrity in a package supporting high frequency switching signals, such as for an integrated circuit in a router. Table 1 shows the various combinations of signal sets for the top side conductors, in accordance with one embodiment of the present invention.

TABLE 1
Signal set arrangements
For differential pairs:
Signal_Positive, Signal_Negative, Gnd (or any permutation thereof)
Signal_Positive, Signal_Negative, Pwr (or any permutation thereof)
For single-ended signals:
Signal, Gnd, Gnd (or any permutation thereof)
Signal, Pwr, Pwr (or any permutation thereof)
Signal, Pwr, Gnd (or any permutation thereof)
Signal, Signal, Gnd (or any permutation therof)
Signal, Signal, Pwr (or any permutation therof)
where “Signal_Positive” represents a positive signal of a differential pair
“Signal_Negative” represents a negative signal of a differential pair
“Signal” represents a single-ended signal
“Pwr” represents a power signal
“Gnd” represents a ground signal

It is understood that while the signal set arrangements shown include three signals in the examples discussed, a signal set could include other numbers of signals, as desired. In addition, the ratio of “Signal” to “Pwr” and/or “Gnd” may change depending on the electrical requirements for the signals to operate properly for a given design. There may be multiple signal sets defined for the top side conductors, and the multiple signal sets may be of different sizes (i.e., contain different numbers of conductors), as desired.

In one embodiment, sets of signals/conductors from the top side conductors are defined so that for each set, the conductors within a set are adjacent with another conductor in the set, and so each conductor of the set is within the same ring of the top side conductors. This arrangement 90 is generally illustrated in FIG. 9. For instance in the example shown in FIG. 9, in the signal set 90 having P1 (a positive signal of a differential pair), N1 (a negative signal of a differential pair), and Gnd (ground), each signal is adjacent another signal in the set, and each signal in this set is within Ring 1 of the top side conductors. Similarly, the signal set having P4, N4 and Gnd is within Ring 2 of the top side conductors.

Referring again to FIG. 2, at operation 6, a region of the top side conductors is selected for automatic logical connection to a region of the bottom side conductors. One example of this operation is shown in FIG. 10, wherein within the GUI, the user can select or highlight a region of the top side conductors, and the user can select or highlight a region of the bottom side conductors. Generally, selections for connections are made on a “one-side-at-a-time” basis wherein the user would select groups of conductors from a first side of the package for automatic connection before selecting groups of conductors from a second side of the package for automatic connection.

Operation 6, in one example, determines if the number of bottom side conductors (i.e., pins) selected equals the number of top side conductors (i.e., pads) before the automatic connection operation 7 is performed. If the number of bottom side conductors is not equal to the number of top side conductors, then the user is prompted to take action to increase the number of bottom side conductors so as to make them equal (i.e., if the number of bottom side conductors is less than the number of top side conductors, then the user is requested to select more bottom side conductors).

Alternatively, operation 6 can automatically select all of the top side conductors to be automatically connected to bottom side conductors. If the software automatically selects all of the top side conductors for connection to the bottom side conductors, in one example the software sub-divides the automatic connection process into four groups of operations, by first selecting a first side of the top side conductors and making those connections to the corresponding first side of the bottom conductors, then selecting a second side of the top side conductors and making those connections to the corresponding second side of the bottom conductors, then selecting a third side of the top side conductors and making those connections to the corresponding third side of the bottom conductors, and then selecting a fourth side of the top side conductors and making those connections to the corresponding fourth side of the bottom conductors.

Referring again to FIG. 2, at operation 7, the selected top side conductors are logically connected automatically to the bottom side conductors while maintaining the signal set relations. The logical connections made are later provided to routing software to that the logical connections between conductors can be routed through the various internal layers of the package. One embodiment of operation 7 of FIG. 2 is further described in FIGS. 11–12.

Referring to FIG. 11, at operation 1, power or ground connections are made using via connections to the appropriate power or ground planes. In this manner, the power or ground connections do not complicate the numerous connections between top and bottom side conductors which carry signal lines. It is understood that the Pwr and Gnd vias decrease the routable area on each signal routing layer through which they pass, and this issue may be addressed by the design tool, as needed.

At operation 2, for each top side conductor arranged in a set, logical connections to the bottom side conductors are made so as to preserve a relative relationship between each conductor in the set. In this manner, if a set of top conductors contains (P1, N1, Gnd), then the connections made to the bottom side conductors will contain (P1, N1, Gnd) in an adjacent or proximate relationship. In one embodiment of the invention, while top side conductors are arranged in a set within a single top conductor ring (which in FIG. 9, are drawn horizontally), the arrangement of the respective connections to bottom side conductors is generally orthogonal (shown as vertical in FIG. 13), in one example.

At operation 3, if the top side has more rings than the bottom side, then multiple top side rings are mapped to a bottom side ring as needed. For example, where the top side has 6 rings, and the bottom side has 4 rings, the following mapping shown in Table 2 can be used:

TABLE 2
Example of Mapping between Top Side Rings (6) and Bottom Side
Rings (4)
Top Side Rings Mapped to Bottom Side Rings
Rings 1 & 2 Ring 1
Rings 2, 3, & 4 Ring 2
Rings 3, 4, & 5 Ring 3
Rings 4, 5, & 6 Ring 4

By sharing a bottom side ring amongst multiple top side rings, all of the top side conductors can be logically connected to the bottom side conductors so that all of the top side conductors are assigned to the bottom side conductors. If the bottom side has more rings than the top side, a similar sharing arrangement can be used. While the sharing arrangement shown in Table 2 is for an example where there are 6 top side rings and 4 bottom side rings, different sharing arrangements can be used where the number of rings on the top side and bottom side differ.

At operation 4 of FIG. 11, the logical connections between top side conductors and bottom side conductors is automatically made. FIG. 12 illustrates one embodiment of the logical operations for making logical connections. FIG. 12 assumes that a set of top conductors has been selected to be connected to a set of bottom conductors—selected either by the user or automatically by the software. FIGS. 13A–B illustrate one example of logical connections made according to the operations of FIGS. 11–12.

For a selected groups of conductors, operations 13 determine the angle between midpoints of the groups of top and bottom pins selected for connection, and operations 46 determine where automatic connections should begin within those groups. Operations 59 (along with operations 13 of FIG. 11) are in effect “design rules” for making the logical connections between top and bottom side conductors, in accordance with one embodiment of the invention.

A reference axis 100 may be used to determine where automatic connections should begin, and one example of a reference plane is shown in FIG. 10. In one embodiment, if the angle between the midpoints is greater than or equal to zero, then the pin connections are made beginning at the right edge of the groups, and if the angle is less than zero, then the pin connections are made beginning at the left edge of the groups.

One way to determine the midpoints is shown in operations 12 of FIG. 12. At operation 1, the number of top conductors selected for connection is counted, and the number of bottom conductors selected for connection is also counted. At operation 2, the number of rows of the top conductors selected is counted, and the number of rows of the bottom conductors selected is counted. At operation 3, the center or midpoint of the group of the top conductors is determined based on the counts obtained as well as the geometries of the top conductors; and the center or midpoint of the group of the bottom conductors is determined based on the counts obtained as well as the geometries of the bottom conductors. Based on the positions of the midpoint of the group of top conductors relative the to the midpoint of the group of bottom conductors, the angle relative to a reference frame is determined. As shown in FIG. 10, the reference frame in one embodiment is from the geometric center of the package. FIG. 10 also shows the midpoints of each group of conductors, and the angle formed by the line connected between the midpoints relative to the reference frame (in the example, the angle is about 0 degrees).

Upon computing the angle, decision operation 4 determines whether the angle is greater than or equal to zero degrees, and if so, operation 5 marks the right edge of the groups to begin automatically connecting thereabout. If the angle is less than zero, the operation 6 marks the left edge of the groups to begin automatically connecting thereabout.

At operation 7 of FIG. 12, connections within the selected group of conductors will begin at the top portion of the right/left edge of the selected groups of conductors, in one embodiment of the invention. As logical connections are made between top and bottom side conductors beginning at the top outer portion of the group, the next connections made move inward and downward, generally. At operation 8, when a connection is made to a set of bottom side conductors, the next set of bottom side conductors is skipped so as to provide for sharing of bottom side rings, as explained above with reference to operation 3 of FIG. 12 and Table 2.

At operation 9 of FIG. 12, where connections are to be made between two conductors originating from a single top side ring, they are made so that crossings of signal lines should be minimized or avoided, in one embodiment of the invention. At operation 10 of FIG. 12, the top side conductors are logically connected to the bottom side conductors.

FIGS. 13A–J show one example of connections made in accordance with one embodiment of the present invention. In FIG. 13A, a portion 130 of bottom side conductors are shown as being selected to be logically connected with a portion 132 of selected top side conductors. As previously discussed, and as shown in FIG. 13A, the top side conductors have been arranged in sets, such as (P1, N1, ground); (P2, N2, ground); (P3, N3, ground); . . . (P12, N12, ground); etc. FIGS. 13B–13I show the various steps for logical connections being made between the top side conductors and the bottom side conductors, in one example. Referring to FIG. 13B, logical connections are made between the top side and bottom side conductors, in accordance with logical operations 710 of FIG. 12, in one example. For instance, as shown in FIG. 13B, top side conductors (P1, N1, ground), being a set, are connected as shown in FIG. 13B, filling the top edge first (operation 7 of FIG. 12); and then top side conductors (P2, N2, ground) are connected to bottom side conductors as shown in FIG. 13B. Note that in FIG. 13B a column of bottom side conductors is skipped between the sets, in accordance with operation 8 of FIG. 12.

Referring now to FIG. 13C, top side conductor sets (P3, N3, ground) and (P4, N4, ground) are connected to bottom side conductors as shown. Note how (P3, N3, ground) are connected to the bottom side conductors in the column between the (P1, N1) set and the (P2, N2) set, which is in accordance with operation 8 of FIG. 12, in one example.

In FIG. 13D, top side conductor sets (P5, N5, ground) and (P6, N6, ground) are logically connected with the bottom side conductors as shown.

In FIG. 13E, top side conductors (P7, N7, power) are connected to bottom side conductors as shown, while top side conductor sets (P8, N8, ground) are connected with bottom side conductors as shown. Again, a portion of a column of conductors is skipped between the sets (P7, N7, power) and (P8, N8, ground) on the bottom side conductors.

In FIG. 13F, top side conductor sets (P9, N9, ground) and (P10, N10, power) are logically connected to bottom side conductors as shown. In FIG. 13G, top side conductor sets (P12, N12, ground) and (P11, N11, ground) are connected with bottom side conductors as shown. In this instance, a portion of a column of conductors is not skipped between the sets (operation 8 of FIG. 12) because the region selected of bottom side conductors (see FIG. 13A) would not so permit.

As shown in FIG. 13H, the sets of top side conductors have been mapped to the bottom side conductors within the regions selected by the user, while FIG. 13I shows the line to line connections between the top side and bottom side conductors. FIG. 13J shows a different example of a complex set of connections between the top side conductors and the bottom side conductors for a large number of conductors.

FIG. 14 illustrates one example of a software architecture, in accordance with one embodiment of the present invention. Front end GUI modules 140 are provided for performing the various functions identified herein, as needed or desired depending on the particular implementation. As shown in FIG. 14, a module 142 is provided for drawing the top side of the package; a module 144 is provided for drawing the bottom side of the package; a module 146 is provided for selecting conductors for connection between the top side and the bottom side; a module 148 is provided for logically connecting the selected conductors; a module 150 is provided for “undo”ing any logical connection made if the user does not like the logical assignment; and a module 152 is provided for generating a net list which specifies the connections between the top side and bottom side conductors. These modules can be implemented, in one embodiment of the present invention, using the various logical operations described herein. Further, these modules can be implemented as graphical user interfaces (GUI) so as to obtain information and input from users through the GUI and display the resulting operations and results thereof to the user through the GUI. As shown in FIG. 14, the front end GUI modules can pass data to and from a computer-aided drawing software package, such as Autodesk's AutoCAD, in order to provide the functionality described herein.

FIG. 15 illustrates one example of a net list 154, and this example is shown in Allegro form. The net list is data structure or list of relationships between the top side conductors and the bottom side conductors, wherein the relationships are defined as the result of the above described operations. As shown in FIG. 15, the net list can, in one example, logically connect or associate a signal name to top side conductor (and location ID) and to a bottom side conductor. For instance, as shown in one row of FIG. 15, “ANALOG_DIODE_N” is a signal name, while “C4_PAD.D54” is a top side conductor name with a location I.D., and “UO1.A22” is a bottom side conductor name with a location I.D. This net list therefore specifies that the signal “ANALOG_DIODE_N” is connected with top side conductor D54, and is also connected with bottom side conductor “A22.” Accordingly, for a single row in the net list, a signal name, top side conductor name, and bottom side conductor name are provided.

Further, in accordance with one embodiment of the present invention, the net list 154 may also identify certain connections as differential pair connections, so that the differential pair signals which are identified will be properly routed according to design rules for the differential pairs. For instance, for an identified differential pair, a design rule may require that the physical routing of the differential pair be no farther apart than 1.27 millimeters. By identifying which signals are differential pairs, the subsequent routing software can properly place the connection according to the design rules for differential pairs. In the example of FIG. 15, a differential pair is identified as ANALOG_DIODE_N and ANALOG_DIODE_P.

Hence it can be seen that, in general, embodiments of the present invention provide initialization of the data describing the top side conductors and the bottom side conductors; provide logical connections between the top side conductors and the bottom side conductors in a manner that is automatic and efficient; and permits iterative changes to the layout as needed by the designers.

While particular numbering or labeling schemes have been used to discuss examples of various embodiments of the present invention, it is understood that the particular numbering schemes for the rings, as well as the numbering or labeling schemes for the pins or pads of the package, is a matter of choice and is not intended to be a limitation of the present invention. Further, all directional references (e.g., upper, lower, upward, downward, left, right, leftward, rightward, top, bottom, above, below, vertical, horizontal, clockwise, counterclockwise, etc.) are only used for identification purposes to aid the reader's understanding of the present invention, and do not create limitations, particularly as to the position, orientation, or use of the invention.

The embodiments of the invention described herein are implemented as logical operations in a computing system. The logical operations of the present invention are implemented (1) as a sequence of computing implemented steps running on the computing system and (2) as interconnected machine modules within the computing system. The implementation is a matter of choice dependent on the performance requirements of the computing system implementing the invention. Accordingly, the logical operations making up the embodiments of the invention described herein are referred to variously as operations, steps, or modules.

While the methods disclosed herein have been described and shown with reference to particular operations or steps performed in a particular order, it will be understood that these operations or steps may be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations or steps is not a limitation of the present invention.

While the invention has been particularly shown and described with reference to various embodiments thereof, it will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and scope of the invention.

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Classifications
U.S. Classification716/130, 438/108, 700/121, 716/139
International ClassificationG06F17/00
Cooperative ClassificationG06F2217/40, G06F17/5068
European ClassificationG06F17/50L
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