|Publication number||US7055122 B1|
|Application number||US 10/118,459|
|Publication date||30 May 2006|
|Filing date||5 Apr 2002|
|Priority date||5 Apr 2002|
|Publication number||10118459, 118459, US 7055122 B1, US 7055122B1, US-B1-7055122, US7055122 B1, US7055122B1|
|Inventors||Alex Tain, Eric Tosaya|
|Original Assignee||Cisco Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Classifications (8), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is related to co-pending, commonly assigned U.S. patent application Ser. No. 11/136,036, filed contemporaneously herewith, entitled “METHOD FOR AUTOMATICALLY ROUTING CONNECTIONS BETWEEN TOP SIDE CONDUCTORS AND BOTTOM SIDE CONDUCTORS OF AN INTEGRATED CIRCUIT PACKAGE” by Alex Tain and Eric Tosaya, the disclosure of which is herein incorporated by reference in its entirety.
This invention relates, in general, to logically connecting top and bottom side conductors during the design of an integrated circuit package.
In the design of packaging for integrated circuits (ICs), a die (having an integrated circuit thereon) is electrically and physically connected to a package. The package has top side conductors, a body portion, and bottom side conductors.
The body of the package 22 provides, among other things, routing of the top side conductors 26 to the bottom side conductors 28. In complex IC designs, the die 20 may have thousands of interconnect sites (i.e., solder bumps) thereon, while the package accordingly has thousands of top side conductors 26 and bottom side conductors 28. Further, the package may be comprised of multiple layers (i.e., twenty or more) of ground planes, power planes, or signal distribution layers, which are used to route the connections between the top side conductors to the bottom side conductors.
As recognized by the present inventors, it can be very difficult and time consuming to design the logical connections between the top side conductors 26 to the bottom side conductors 28, particularly where relationships such as electrical and physical constraints between the groups of signals lines need to be maintained throughout the package, as with the case of very high frequency signal lines. Such logical connections are conventionally designed by a package engineer using manual data entry to manually connect each top side conductor to each bottom side conductor—such as by manually “pointing and clicking” between two conductors within a software design tool. While commercially available design tools can automatically assign these connections, such tools have severe limitations in their ability to follow the required electrical and physical design constraints.
As recognized by the present inventors, what is needed is a method for automatically making logical connections between top side conductors and bottom side conductors of an IC package, while maintaining the relative relationships between groups of signal lines as needed.
It is against this background that various embodiments of the present invention were developed.
In light of the above and according to one broad aspect of one embodiment of the present invention, disclosed herein is a method for logically connecting at least one of a plurality of top side conductors of an integrated circuit package with at least one of a plurality of bottom side conductors of the integrated circuit package. The method includes drawing a layout of the bottom side conductors, and drawing a layout of the top side conductors. One or more rings or rows or columns of the top side conductors are defined, and one or more rings or rows or columns of the bottom side conductors are defined. One or more signal sets of the top side conductors are defined, each of said signal sets contains at least two or more top side conductors. The user can select a region of top side conductors to be connected with a region of bottom side conductors, and the selected region of top side conductors is automatically connected with the selected region of bottom side conductors while maintaining the signal set relations. In this manner, the logical connection between the top and bottom side conductors of an integrated circuit package are automatically assigned while maintaining the relationship between the signal sets defined by the user. A netlist can be generated of the logical connections made by the connecting operation.
In one embodiment, the one or more rings of the top side conductors are defined concentrically, and each of the one or more rings of the top side conductors contains a single row of top side conductors along each side of the package. In one embodiment, each of the one or more rings of the bottom side conductors contains a three rows of bottom side conductors along each side of the package, and the one or more rings of the bottom side conductors are defined concentrically.
In one embodiment, the signal sets each include a pair of top side conductors arranged as a differential pair, such as a positive signal of the differential pair assigned to a first top side conductor, a negative signal of the differential pair assigned to a second top side conductor, and a ground or power signal assigned to a third top side conductor. In one embodiment, the first, second, and third top side conductors are co-linearly arranged.
Other features, utilities and advantages of the various embodiments of the invention will be apparent from the following more particular description of embodiments of the invention as illustrated in the accompanying drawings.
Disclosed herein is a method and computer program product for automatically making logical connections between the top side conductors 26 and the bottom side conductors 28 of an integrated circuit package 22, an example of which is shown in
As used herein, the term “bottom side conductors” or “pins” 28 refers to the conductors on the package 22 that are positioned to be connected with the printed circuit board or with an IC socket. Bottom side conductors include but are not limited to, for example, metallized pads, pins, balls, or columns, or the like, and these terms are used interchangeably herein to generally refer to a bottom side conductor.
As used herein, the term “top side conductors” or “pads” 26 refers to the conductors on the package 22 that are positioned to be connected with the conductors of the die 20. Top side conductors include but are not limited to, for example, pads that are adapted to be electrically connected with a corresponding conductor of the die—such as a flip chip (FC) solder ball.
The term “logical connection” refers to a representation of a physical connection between two conductors. In one example, a logical connection between a particular top side conductor and a particular bottom side conductor indicates that a physical connection between the two conductors should be made within the package.
Referring now to
At operation 2, the layout of the top side conductors of the package is created, based on various inputs describing package and the footprint of the die, as will be discussed with reference to
Operations 1 and 2 of
At operation 1 of
At operation 2 of
At operation 4, the Pin A1 identification is made—for example, the user selects which pin of the package is the “A1” pin (also commonly referred to as the Pin #1 corner)—and at operation 5, the remaining pins are labeled, in one example using JEDEC pin labeling conventions. At operation 6, the power (i.e., VDD) and ground pins (i.e., VSS) of the package are identified.
At operation 7, a view of the bottom side of the package is generated and displayed to the user, and in one example the view generated is based on the data obtained from operations 1–6.
The logical operations for generating a model or view of the top side conductors of the package are shown in
At operation 4 of
Now referring again to
At operation 4 of
At operation 5 of
Signal set arrangements
For differential pairs:
Signal_Positive, Signal_Negative, Gnd (or any permutation thereof)
Signal_Positive, Signal_Negative, Pwr (or any permutation thereof)
For single-ended signals:
Signal, Gnd, Gnd (or any permutation thereof)
Signal, Pwr, Pwr (or any permutation thereof)
Signal, Pwr, Gnd (or any permutation thereof)
Signal, Signal, Gnd (or any permutation therof)
Signal, Signal, Pwr (or any permutation therof)
where “Signal_Positive” represents a positive signal of a differential pair
“Signal_Negative” represents a negative signal of a differential pair
“Signal” represents a single-ended signal
“Pwr” represents a power signal
“Gnd” represents a ground signal
It is understood that while the signal set arrangements shown include three signals in the examples discussed, a signal set could include other numbers of signals, as desired. In addition, the ratio of “Signal” to “Pwr” and/or “Gnd” may change depending on the electrical requirements for the signals to operate properly for a given design. There may be multiple signal sets defined for the top side conductors, and the multiple signal sets may be of different sizes (i.e., contain different numbers of conductors), as desired.
In one embodiment, sets of signals/conductors from the top side conductors are defined so that for each set, the conductors within a set are adjacent with another conductor in the set, and so each conductor of the set is within the same ring of the top side conductors. This arrangement 90 is generally illustrated in
Referring again to
Operation 6, in one example, determines if the number of bottom side conductors (i.e., pins) selected equals the number of top side conductors (i.e., pads) before the automatic connection operation 7 is performed. If the number of bottom side conductors is not equal to the number of top side conductors, then the user is prompted to take action to increase the number of bottom side conductors so as to make them equal (i.e., if the number of bottom side conductors is less than the number of top side conductors, then the user is requested to select more bottom side conductors).
Alternatively, operation 6 can automatically select all of the top side conductors to be automatically connected to bottom side conductors. If the software automatically selects all of the top side conductors for connection to the bottom side conductors, in one example the software sub-divides the automatic connection process into four groups of operations, by first selecting a first side of the top side conductors and making those connections to the corresponding first side of the bottom conductors, then selecting a second side of the top side conductors and making those connections to the corresponding second side of the bottom conductors, then selecting a third side of the top side conductors and making those connections to the corresponding third side of the bottom conductors, and then selecting a fourth side of the top side conductors and making those connections to the corresponding fourth side of the bottom conductors.
Referring again to
At operation 2, for each top side conductor arranged in a set, logical connections to the bottom side conductors are made so as to preserve a relative relationship between each conductor in the set. In this manner, if a set of top conductors contains (P1, N1, Gnd), then the connections made to the bottom side conductors will contain (P1, N1, Gnd) in an adjacent or proximate relationship. In one embodiment of the invention, while top side conductors are arranged in a set within a single top conductor ring (which in
At operation 3, if the top side has more rings than the bottom side, then multiple top side rings are mapped to a bottom side ring as needed. For example, where the top side has 6 rings, and the bottom side has 4 rings, the following mapping shown in Table 2 can be used:
Example of Mapping between Top Side Rings (6) and Bottom Side
Top Side Rings
Bottom Side Rings
Rings 1 & 2
Rings 2, 3, & 4
Rings 3, 4, & 5
Rings 4, 5, & 6
By sharing a bottom side ring amongst multiple top side rings, all of the top side conductors can be logically connected to the bottom side conductors so that all of the top side conductors are assigned to the bottom side conductors. If the bottom side has more rings than the top side, a similar sharing arrangement can be used. While the sharing arrangement shown in Table 2 is for an example where there are 6 top side rings and 4 bottom side rings, different sharing arrangements can be used where the number of rings on the top side and bottom side differ.
At operation 4 of
For a selected groups of conductors, operations 1–3 determine the angle between midpoints of the groups of top and bottom pins selected for connection, and operations 4–6 determine where automatic connections should begin within those groups. Operations 5–9 (along with operations 1–3 of
A reference axis 100 may be used to determine where automatic connections should begin, and one example of a reference plane is shown in
One way to determine the midpoints is shown in operations 1–2 of
Upon computing the angle, decision operation 4 determines whether the angle is greater than or equal to zero degrees, and if so, operation 5 marks the right edge of the groups to begin automatically connecting thereabout. If the angle is less than zero, the operation 6 marks the left edge of the groups to begin automatically connecting thereabout.
At operation 7 of
At operation 9 of
Referring now to
As shown in
Further, in accordance with one embodiment of the present invention, the net list 154 may also identify certain connections as differential pair connections, so that the differential pair signals which are identified will be properly routed according to design rules for the differential pairs. For instance, for an identified differential pair, a design rule may require that the physical routing of the differential pair be no farther apart than 1.27 millimeters. By identifying which signals are differential pairs, the subsequent routing software can properly place the connection according to the design rules for differential pairs. In the example of
Hence it can be seen that, in general, embodiments of the present invention provide initialization of the data describing the top side conductors and the bottom side conductors; provide logical connections between the top side conductors and the bottom side conductors in a manner that is automatic and efficient; and permits iterative changes to the layout as needed by the designers.
While particular numbering or labeling schemes have been used to discuss examples of various embodiments of the present invention, it is understood that the particular numbering schemes for the rings, as well as the numbering or labeling schemes for the pins or pads of the package, is a matter of choice and is not intended to be a limitation of the present invention. Further, all directional references (e.g., upper, lower, upward, downward, left, right, leftward, rightward, top, bottom, above, below, vertical, horizontal, clockwise, counterclockwise, etc.) are only used for identification purposes to aid the reader's understanding of the present invention, and do not create limitations, particularly as to the position, orientation, or use of the invention.
The embodiments of the invention described herein are implemented as logical operations in a computing system. The logical operations of the present invention are implemented (1) as a sequence of computing implemented steps running on the computing system and (2) as interconnected machine modules within the computing system. The implementation is a matter of choice dependent on the performance requirements of the computing system implementing the invention. Accordingly, the logical operations making up the embodiments of the invention described herein are referred to variously as operations, steps, or modules.
While the methods disclosed herein have been described and shown with reference to particular operations or steps performed in a particular order, it will be understood that these operations or steps may be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations or steps is not a limitation of the present invention.
While the invention has been particularly shown and described with reference to various embodiments thereof, it will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6041269 *||11 Aug 1997||21 Mar 2000||Advanced Micro Devices, Inc.||Integrated circuit package verification|
|US6137168 *||27 Oct 1999||24 Oct 2000||Lsi Logic Corporation||Semiconductor package with traces routed underneath a die|
|US6319752||24 Apr 2000||20 Nov 2001||Advanced Micro Devices, Inc.||Single-layer autorouter|
|US6399422 *||8 Sep 2000||4 Jun 2002||Mitsubishi Denki Kabushiki Kaisha||Radiating plate structure and method for manufacturing semiconductor devices using the same structure|
|US6479319 *||20 Apr 2001||12 Nov 2002||Lsi Logic Corporation||Contact escape pattern|
|US6510539 *||29 Oct 1999||21 Jan 2003||International Business Machines Corporation||System and method for physically modeling electronic modules wiring|
|US6534879 *||22 Feb 2001||18 Mar 2003||Oki Electric Industry Co., Ltd.||Semiconductor chip and semiconductor device having the chip|
|US6569694 *||28 Jun 2001||27 May 2003||Advanced Micro Devices, Inc.||Method of checking BGA substrate design|
|US6584596 *||24 Sep 2001||24 Jun 2003||International Business Machines Corporation||Method of designing a voltage partitioned solder-bump package|
|US6642080 *||18 Oct 2000||4 Nov 2003||International Business Machines Corporation||Chip-on-chip interconnections of varied characterstics|
|US6665194 *||9 Nov 2000||16 Dec 2003||International Business Machines Corporation||Chip package having connectors on at least two sides|
|US6680219 *||17 Aug 2001||20 Jan 2004||Qualcomm Incorporated||Method and apparatus for die stacking|
|US6680544 *||4 Feb 2002||20 Jan 2004||Via Technologies, Inc.||Flip-chip bump arrangement for decreasing impedance|
|US6686666 *||16 May 2002||3 Feb 2004||Intel Corporation||Breaking out signals from an integrated circuit footprint|
|U.S. Classification||716/130, 438/108, 700/121, 716/139|
|Cooperative Classification||G06F2217/40, G06F17/5068|
|16 May 2002||AS||Assignment|
Owner name: PROCKET NETWORKS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAIN, ALEXANDER;TOSAYA, ERIC;REEL/FRAME:012902/0605
Effective date: 20020430
|15 Dec 2005||AS||Assignment|
Owner name: CISCO TECHNOLOGY, INC.,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PROCKET NETWORKS, INC.;REEL/FRAME:016902/0034
Effective date: 20040803
|23 Oct 2009||FPAY||Fee payment|
Year of fee payment: 4
|2 Dec 2013||FPAY||Fee payment|
Year of fee payment: 8