US7045884B2 - Semiconductor device package - Google Patents

Semiconductor device package Download PDF

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Publication number
US7045884B2
US7045884B2 US10/677,069 US67706903A US7045884B2 US 7045884 B2 US7045884 B2 US 7045884B2 US 67706903 A US67706903 A US 67706903A US 7045884 B2 US7045884 B2 US 7045884B2
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Prior art keywords
conductive
package according
semiconductor package
circuit board
power
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US10/677,069
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US20040119148A1 (en
Inventor
Martin Standing
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Infineon Technologies North America Corp
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International Rectifier Corp USA
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Priority to US10/677,069 priority Critical patent/US7045884B2/en
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Priority to AU2003277266A priority patent/AU2003277266A1/en
Priority to JP2005501079A priority patent/JP2006502595A/en
Priority to PCT/US2003/031362 priority patent/WO2004034428A2/en
Priority to DE10393437T priority patent/DE10393437T5/en
Assigned to INTERNATIONAL RECTIFIER CORPORATION reassignment INTERNATIONAL RECTIFIER CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STANDING, MARTIN
Publication of US20040119148A1 publication Critical patent/US20040119148A1/en
Priority to US11/348,392 priority patent/US7364949B2/en
Application granted granted Critical
Publication of US7045884B2 publication Critical patent/US7045884B2/en
Assigned to Infineon Technologies Americas Corp. reassignment Infineon Technologies Americas Corp. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL RECTIFIER CORPORATION
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Definitions

  • FIG. 1 shows the cross-section of a typical, multi-chip package 5 , which includes substrate 6 , semiconductor components 7 , and molded housing 8 . It should be noted that semiconductor components are interconnected inside the package and to external connectors (not shown) by connectors such as bond wires 9 A and in some cases conductive clips, e.g. 9 B.
  • Such connectors add to the overall resistance and inductance of the package, and cause undesirable effects such as ringing.
  • a heatsink (not shown) may be thermally coupled to substrate 6 to dissipate the generated heat.
  • the size of the heatsink typically depends on the amount of heat generated. Thus, a large amount of heat would require a larger heatsink. Therefore, heat generation has a bearing on the size of the package.
  • a semiconductor package according to the present invention includes a first circuit board, a second circuit board, and at least one semiconductor device disposed between the two circuit boards.
  • the circuit boards are the thermally conductive variety such as insulated metal substrate or double bonded copper.
  • thermally conductive circuit boards are used double-sided cooling may be achieved.
  • heat dissipation may be divided between two surfaces and instead of one large heatsink for dissipating heat from one surface, which is the prior art solution, two smaller heatsinks may be used, thereby reducing the overall size of the package.
  • a semiconductor package may include a plurality of semiconductor devices which are interconnected inside the package to form one a or a plurality of circuits.
  • a package according to the present invention may include a plurality of power switching devices for forming half-bridges or converter circuits.
  • a semiconductor die in a package according to the present invention exhibits 26% less thermal resistance at its electrical contacts than a die in a conventional package. It has also been found that a die in a package according to the present invention operates at a lower temperature than a die in a conventional package. Experiments have shown, for example, that under identical load conditions the steady state temperatures measured at the outer surface of a circuit board in a package according to the present invention is 75° C. while the temperature at a similar position for a conventional package is 82° C.
  • FIG. 1 shows a cross-sectional view of a semiconductor package according to the prior art
  • FIG. 2 shows the top plan view of a semiconductor package according to the first embodiment of the present invention
  • FIG. 4 shows a top plan view of a circuit board used in a package according to the present invention
  • FIG. 5 shows a top plan view of another circuit board used in a package according to the present invention.
  • FIG. 6 shows a top plan view of the circuit board shown by FIG. 4 which includes a plurality of semiconductor switching devices
  • FIG. 7 shows a cross-sectional view of a package according to the present invention taken along line 7 — 7 in FIG. 2 viewed in the direction of the arrows;
  • FIG. 8 shows a side view of a package according to the present invention which has a heatsink mounted on one side thereof;
  • FIGS. 9A–9B illustrate the processing steps taken for the manufacture of a package according to the present invention
  • FIG. 10 shows a top plan view of a package according to the second embodiment of the present invention.
  • FIG. 11 shows a top plan view of a package according to the third embodiment of the present invention.
  • FIG. 12 shows a package according to the third embodiment of the present invention as integrated with a circuit board
  • FIG. 13 shows a top plan view of a circuit board adapted for integration with a package according to the first embodiment of the present invention
  • FIG. 14 shows a side view of a circuit board as integrated with a package according to the first embodiment of the present invention
  • FIG. 15 shows a side view of a motor integrated with a circuit board that includes an integral package according to the present invention
  • FIG. 16 shows a circuit diagram for a three-phase buck converter
  • semiconductor package 10 includes first circuit board 12 , and second circuit board 14 which is assembled over first circuit board 12 .
  • circuit boards 12 , 14 are of the thermally conductive variety such as insulated metal substrate (IMS), or double-bonded copper (DBC).
  • IMS insulated metal substrate
  • DBC double-bonded copper
  • Such circuit boards include a thermally conductive, but electrically insulating body which can have conductive patterns formed over at least one of its surfaces.
  • first circuit board 12 includes a plurality of external connectors 16 which serve as input and output connectors to the elements disposed between first circuit board 12 and second circuit board 14 as will be described later.
  • semiconductor package 10 includes a plurality of power MOSFETs T 1 , T 2 , T 3 , T 4 , T 5 , T 6 which are interconnected to form three parallel-connected half-bridge circuits, each for driving a respective phase of a three-phase motor.
  • MOSFET T 3 forms a half-bridge with MOSFET T 4
  • MOSFET T 2 forms a half-bridge with MOSFET T 5
  • MOSFET T 1 forms a half-bridge with MOSFET T 6 .
  • the output of each half-bridge circuit A, B, C is taken from the connection point of its high side MOSFET to its respective low side MOSFET as shown by FIG. 3 .
  • a gate signal is sent by a control circuit (not shown) through a respective gate connection G 1 , G 2 , G 3 , G 4 , G 5 , G 6 .
  • first circuit board 12 includes a plurality of source conductive pads 18 T1 , 18 T2 , 18 T3 for receiving source contacts of high side MOSFETS T 1 , T 2 , T 3 , respectively, and drain conductive pads 20 T6 , 20 T5 , 20 T4 for receiving the drain contacts of low side MOSFETs T 6 , T 5 , T 4 , respectively.
  • Each conductive pad is an area on a conductive track which has been exposed through an opening in a solder passivation layer formed on the conductive track.
  • each conductive track is itself disposed on the thermally conductive body of a circuit board 12 , 14 .
  • each conductive track is a layer of conductive material, such as copper or aluminum, which is patterned to a desired configuration.
  • Conductive tracks are covered with solder passivation material, and openings are formed in the solder passivation material to expose portions of the conductive tracks to serve as conductive pads.
  • Source conductive pad 18 T1 is connected electrically through a conductive trace 22 on circuit board 12 to conductive pad 20 T6 , and then connected to external connector 16 A through another conductive trace 22 on circuit board 12 .
  • Each conductive trace 22 is essentially a portion of the conductive track which electrically connects conductive pads together or to an external connection.
  • source conductive pad 18 T1 , drain conductive pad 20 T2 , and traces 22 , and external connector 16 A form a conductive track that provides an output connection for the half-bridge circuit that is formed by MOSFETs T 1 and T 6 .
  • conductive pads 18 T2 , and 18 T3 are similarly connected to conductive pads 20 T5 and 20 T4 and then to external connectors 16 B and 16 C in a similar manner.
  • source contacts of high side MOSFETs T 1 , T 2 , T 3 are electrically connected to drain contacts of respective low side MOSFETs T 6 , T 5 , T 4 and then connected to external connectors 16 A , 16 B , 16 C , which serve as output connections for each half-bridge circuit without using any wirebonds.
  • First circuit board 12 also includes gate conductive pads 24 T1 , 24 T2 , 24 T3 each for receiving a respective gate contact of high side MOSFETs T 1 , T 2 , T 3 .
  • Gate conductive pad 24 T1 is connected via a trace 22 to external connector 16 G1 , which serves as the gate connection for receiving a gate signal for high side MOSFET T 1 .
  • gate pads 24 T2 and 24 T3 are connected to output connectors 16 G2 and 16 G3 respectively via traces 22 .
  • Connectors 16 G2 , 16 G3 serve as gate connections for high side MOSFETs T 2 , T 3 .
  • second circuit board 14 includes drain conductive pads 20 T1 , 20 T2 , 20 T3 for receiving drain contacts of high side MOSFETs T 1 , T 2 , T 3 .
  • Second circuit board 14 also includes interconnect conductive pads 28 V+ and 28 Vground .
  • Drain conductive pads 20 T1 , 20 T2 , 20 T3 are formed on the same conductive trace as interconnect conductive pads 28 V+ .
  • Interconnect pads 28 V+ are electrically connectable to interconnect pad 29 V+ on first circuit board 12 , which is electrically connected to external connector 16 V+ via a trace 22 .
  • External connector 16 V+ in the first embodiment of the present invention serves as the connection to the input power V + , when second circuit board 14 is disposed over first circuit board 12 .
  • Second circuit board 14 also includes gate conductive pads 24 T4 , 24 T5 , 24 T6 for receiving gate contacts of low side MOSFETs T 4 , T 5 , T 6 .
  • Each gate conductive pad 24 T4 , 24 T5 , 24 T6 is electrically connected to gate interconnect pads 28 G4 , 28 G5 , 28 G6 via a respective trace 22 .
  • Each gate interconnect pad 28 G4 , 28 G5 , 28 G6 is then connected to a corresponding gate interconnect pad 29 G4 , 29 G5 , 29 G6 on first circuit board 12 , and thereby electrically connected via a respective trace 22 to a corresponding gate connector 16 G4 , 16 G5 , 16 G6 .
  • Source conductive pads 18 T4 , 18 T5 , 18 T6 , and ground interconnect pads 28 ground are formed on a common conductive track and, therefore, are electrically connected together.
  • Ground interconnect pads 28 ground on second circuit board 14 are connected to corresponding ground interconnect pads 29 ground on first circuit board 12 , which are in turn connected via a common trace 32 to external ground connector 16 ground .
  • source contacts of low side MOSFETs T 4 , T 5 , T 6 are connectable to a ground connection via external connector 16 ground .
  • source contact, e.g. ST 1 , of each high side MOSFET T 1 , T 2 , T 3 is electrically connected to a corresponding source conductive pad 18 T1 , 18 T2 , 18 T3
  • each gate contact, e.g. GT 1 , of each high side MOSFET T 1 , T 2 , T 3 is electrically connected to a corresponding gate conductive pad 24 T1 , 24 T2 , 24 T3
  • each drain contact, e.g. DT 6 of each low side MOSFET T 4 , T 5 , T 6 is electrically connected to its corresponding drain conductive pad, e.g. 20 T6 , on first circuit board 12 .
  • each case Electrical connection in each case is made by a layer of conductive adhesive 33 such as solder or conductive epoxy. It should be noted that source contact and the gate contact of each MOSFET are exposed through a solder passivation 19 (shown by crossing lines in FIG. 6 ) layer which prevents the solder (or any other conductive adhesive) from shorting the gate contact to the source contact.
  • conductive adhesive 33 such as solder or conductive epoxy.
  • second circuit board 14 is assembled opposite first circuit board 12 such that drain contact, e.g. DT 1 of each high side MOSFET T 1 , T 2 , T 3 is electrically connected via a layer of conductive adhesive 33 to its corresponding drain conductive pad, e.g. 20 T1 , on second circuit board 14 .
  • drain contact e.g. DT 1 of each high side MOSFET T 1 , T 2 , T 3 is electrically connected via a layer of conductive adhesive 33 to its corresponding drain conductive pad, e.g. 20 T1 , on second circuit board 14 .
  • source contact, e.g. ST 6 of each low side MOSFET T 4 , T 5 , T 6 is electrically connected via a layer of conductive adhesive 33 to its corresponding source conductive pad, e.g. 18 T 6 on second circuit board 14
  • gate contact e.g. GT 6
  • each low side MOSFET, T 4 , T 5 , T 6 is electrically connected to its corresponding gate conductive pad
  • interconnect 35 which electrically connects ground conductive pad 29 ground on first circuit board 12 to ground conductive pad 28 ground on second circuit board 14 .
  • Interconnect 35 is connected to each conductive pad via a layer of conductive adhesive 33 .
  • Interconnect 35 may be any conductive body such as a copper slug.
  • FIG. 7 shows that low side MOSFET T 6 , high side MOSFET T 1 and interconnect 35 are connected between first circuit board 12 and second circuit board 14 .
  • the remaining high side MOSFETs T 2 , T 3 and low side MOSFETs T 4 , T 5 are connected in the same manner as that of high side MOSFET T 1 and low side MOSFET T 6 .
  • interconnects are used to connect internal gate conductive pads 28 G4 , 28 G5 , 28 G6 to internal conductive pads 29 G4 , 29 G5 , 29 G6 , and internal conductive pads 28 V+ to conductive pads 29 V+ in the same manner as described for interconnect 35 above.
  • an epoxy underfilling 37 is provided in the spaces between first circuit board 12 and second circuit board 14 .
  • the purpose of epoxy underfilling 37 is to protect MOSFETs from environmental conditions such as moisture.
  • a heatsink 40 may be thermally coupled to second circuit board 14 to assist in heat dissipation. Heatsink 40 may also be coupled to first circuit board 12 without deviating from the present invention
  • each circuit board 12 , 14 may receive a heatsink to effect double-sided cooling.
  • a heatsink to effect double-sided cooling.
  • smaller heatsinks can be used (instead of one large heatsink) thereby reducing the overall size of the package.
  • a plurality of first circuit boards 12 may be linked together to form a large panel and MOSFETs T 1 , T 2 , T 3 , T 4 , T 5 , T 6 and second circuit boards 14 may be placed by a pick-and-place machine. Then, first circuit boards 12 are cut from the large panel to form individual packages after epoxy underfilling has been applied.
  • a package according to a second embodiment of the present invention may include external connectors on more than one side.
  • a package according to the third embodiment of the present invention may include plug-type external connectors 39 , which are adapted to be received in corresponding sockets, for example, in another circuit board.
  • An example of such arrangement is shown by FIG. 12 , in which a package according to the third embodiment of the present invention is shown assembled onto circuit board 42 having sockets (not shown) for receiving external conductors 39 .
  • a package according to the first embodiment of the present invention may be integrated with another circuit board by having external connectors 16 electrically connected to corresponding lands.
  • FIG. 13 shows circuit board 44 having a plurality of conductive lands 45 for receiving external connectors 16 of a package according to the first embodiment of the present invention.
  • FIG. 14 illustrates the assembly of package 10 according to the present invention onto circuit board 44 .
  • Circuit board 44 may include other components 47 , which may be operatively connected to the components within package 10 .
  • Components 47 may be, for example, circuit elements for controlling the MOSFETs in package 10 .
  • a circuit board including a package according to the present invention may be adapted for mounting, and mounted to the body of a device, thereby forming, for example, a device having an integral control mechanism.
  • circuit board 44 containing package 10 which includes three-half bridge circuits, may include a control circuitry for driving each half-bridge circuit, and mounted on the body of a three-phase motor 50 .
  • Each phase of motor 50 may then be operatively connected to the output connectors of package 10 , thereby forming a motor package with an integral drive circuitry.
  • a package according to the present invention is not restricted to half-bridge circuits.
  • a package according to the fourth embodiment of the present invention may be configured to include the power components for a three-phase synchronous buck converter as shown by FIG. 16 .
  • a synchronous buck converter includes two series connected power switching elements, such as power MOSFETs, one of which is referred to as a control MOSFET 50 , and the other as a synchronous MOSFET 52 .
  • a schottky diode 54 is connected between the source and the drain of the synchronous MOSFET 52 .
  • a three-phase synchronous buck converter is essentially three synchronous buck converters connected together.
  • a package according to the fourth embodiment includes first circuit board 12 , second circuit board 14 , control MOSFETs 50 , synchronous MOSFETs 52 , and schottky diodes 54 .
  • circuit boards 12 , 14 include conductive pads 51 formed on selected areas of conductive tracks 30 on each circuit board for electrical connections to, for example, electrical contacts of MOSFETs 50 , 52 , and schottky diodes 54 , as well as conductive pads for receiving interconnects 56 for internal connection of the elements within the package.
  • a package according to the fourth embodiment may be manufactured by first placing the power components on first circuit board 12 as described earlier, printing solder paste (or some other conductive adhesive) on conductive pads of second circuit board 14 , placing second circuit board 14 over first circuit board 12 and then reflowing the solder paste. Thereafter, the space between circuit boards 12 , 14 may be filled with epoxy 37 .

Abstract

A semiconductor package that includes two circuit boards and at least one semiconductor device which is disposed between the two circuit boards and connected to external connectors disposed on at least one of the circuit boards.

Description

RELATED APPLICATIONS
The application is based on and claims benefit of U.S. Provisional Application No. 60/416,503, filed on Oct. 4, 2002, entitled Multiple Phase Inverter Modules for High Density Power Applications, U.S. Provisional Application No. 60/417,217, filed on Oct. 8, 2002, entitled Multiple Phase Inverter Modules For High Density High Power Applications and U.S. Provisional Application No. 60/446,758, filed Feb. 11, 2003, entitled Intelligent Multiphase Modules, to which claims of priority are hereby made.
BACKGROUND OF THE INVENTION
To integrate a semiconductor component into an electronic circuit, the component must be packaged. FIG. 1 shows the cross-section of a typical, multi-chip package 5, which includes substrate 6, semiconductor components 7, and molded housing 8. It should be noted that semiconductor components are interconnected inside the package and to external connectors (not shown) by connectors such as bond wires 9A and in some cases conductive clips, e.g. 9B.
Such connectors add to the overall resistance and inductance of the package, and cause undesirable effects such as ringing.
Furthermore, if the package contains heat generating components, in a conventional package such as package 5, a heatsink (not shown) may be thermally coupled to substrate 6 to dissipate the generated heat. The size of the heatsink typically depends on the amount of heat generated. Thus, a large amount of heat would require a larger heatsink. Therefore, heat generation has a bearing on the size of the package.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a package for a semiconductor device or a plurality of semiconductor devices.
A semiconductor package according to the present invention includes a first circuit board, a second circuit board, and at least one semiconductor device disposed between the two circuit boards. In the preferred embodiment of the present invention the circuit boards are the thermally conductive variety such as insulated metal substrate or double bonded copper. When thermally conductive circuit boards are used double-sided cooling may be achieved. As a result, heat dissipation may be divided between two surfaces and instead of one large heatsink for dissipating heat from one surface, which is the prior art solution, two smaller heatsinks may be used, thereby reducing the overall size of the package.
According to one aspect of the invention, at least one of the circuit boards includes external connectors for external connection to other components. Each electrical connector is a portion of a conductive track on the circuit board which also includes at least one conductive pad that is electrically connected to an electrical contact of the at least one semiconductor device.
According to another embodiment of the present invention, a semiconductor package may include a plurality of semiconductor devices which are interconnected inside the package to form one a or a plurality of circuits. For example, a package according to the present invention may include a plurality of power switching devices for forming half-bridges or converter circuits.
It has been determined, through experiments, that a semiconductor die in a package according to the present invention exhibits 26% less thermal resistance at its electrical contacts than a die in a conventional package. It has also been found that a die in a package according to the present invention operates at a lower temperature than a die in a conventional package. Experiments have shown, for example, that under identical load conditions the steady state temperatures measured at the outer surface of a circuit board in a package according to the present invention is 75° C. while the temperature at a similar position for a conventional package is 82° C.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a cross-sectional view of a semiconductor package according to the prior art;
FIG. 2 shows the top plan view of a semiconductor package according to the first embodiment of the present invention;
FIG. 3 shows the circuit diagram for the components disposed within a package according to the first embodiment of the present invention;
FIG. 4 shows a top plan view of a circuit board used in a package according to the present invention;
FIG. 5 shows a top plan view of another circuit board used in a package according to the present invention;
FIG. 6 shows a top plan view of the circuit board shown by FIG. 4 which includes a plurality of semiconductor switching devices;
FIG. 7 shows a cross-sectional view of a package according to the present invention taken along line 7—7 in FIG. 2 viewed in the direction of the arrows;
FIG. 8 shows a side view of a package according to the present invention which has a heatsink mounted on one side thereof;
FIGS. 9A–9B illustrate the processing steps taken for the manufacture of a package according to the present invention;
FIG. 10 shows a top plan view of a package according to the second embodiment of the present invention;
FIG. 11 shows a top plan view of a package according to the third embodiment of the present invention;
FIG. 12 shows a package according to the third embodiment of the present invention as integrated with a circuit board;
FIG. 13 shows a top plan view of a circuit board adapted for integration with a package according to the first embodiment of the present invention;
FIG. 14 shows a side view of a circuit board as integrated with a package according to the first embodiment of the present invention;
FIG. 15 shows a side view of a motor integrated with a circuit board that includes an integral package according to the present invention;
FIG. 16 shows a circuit diagram for a three-phase buck converter; and
FIG. 17 illustrates a package according to the fourth embodiment of the present invention.
 DETAILED DESCRIPTION OF THE FIGURES
Referring to FIG. 2, semiconductor package 10 according to the first embodiment of the present invention includes first circuit board 12, and second circuit board 14 which is assembled over first circuit board 12. According to an aspect of the present invention, circuit boards 12, 14 are of the thermally conductive variety such as insulated metal substrate (IMS), or double-bonded copper (DBC). Such circuit boards include a thermally conductive, but electrically insulating body which can have conductive patterns formed over at least one of its surfaces. In the first embodiment of the present invention, first circuit board 12 includes a plurality of external connectors 16 which serve as input and output connectors to the elements disposed between first circuit board 12 and second circuit board 14 as will be described later.
Referring next to FIG. 3, semiconductor package 10 according to the first embodiment of the present invention includes a plurality of power MOSFETs T1, T2, T3, T4, T5, T6 which are interconnected to form three parallel-connected half-bridge circuits, each for driving a respective phase of a three-phase motor.
As is well known in the art, each half-bridge circuit includes a high side MOSFET, T3, T2, T1 and a low side MOSFET T4, T5, T6. When power MOSFETs are used to form half-bridge circuits, the source contact of the high side MOSFET, e.g. T1, is series connected to the drain contact of the low side MOSFET e.g. T6, while the drain contact of the high side MOSFET is connected to the input power V+ and the source contact of the low side MOSFET is connected to the ground G. Referring to FIG. 3, in the first embodiment of the present invention MOSFET T3, forms a half-bridge with MOSFET T4, MOSFET T2 forms a half-bridge with MOSFET T5, and MOSFET T1 forms a half-bridge with MOSFET T6. As is well known the output of each half-bridge circuit A, B, C is taken from the connection point of its high side MOSFET to its respective low side MOSFET as shown by FIG. 3. To operate each MOSFET T1, T2, T3, T4, T5, T6, a gate signal is sent by a control circuit (not shown) through a respective gate connection G1, G2, G3, G4, G5, G6. It should be understood that the present invention is not restricted to the circuit shown by FIG. 3, and that other circuits formed with other devices may be packaged according to the principles of the present invention.
According to an aspect of the present invention a circuit, such as the one shown by FIG. 3, is implemented without the use of wirebonds or the like. Specifically, referring now to FIG. 4, first circuit board 12 includes a plurality of source conductive pads 18 T1, 18 T2, 18 T3 for receiving source contacts of high side MOSFETS T1, T2, T3, respectively, and drain conductive pads 20 T6, 20 T5, 20 T4 for receiving the drain contacts of low side MOSFETs T6, T5, T4, respectively. Each conductive pad is an area on a conductive track which has been exposed through an opening in a solder passivation layer formed on the conductive track. The conductive track is itself disposed on the thermally conductive body of a circuit board 12, 14. Specifically, each conductive track is a layer of conductive material, such as copper or aluminum, which is patterned to a desired configuration. Conductive tracks are covered with solder passivation material, and openings are formed in the solder passivation material to expose portions of the conductive tracks to serve as conductive pads.
Source conductive pad 18 T1 is connected electrically through a conductive trace 22 on circuit board 12 to conductive pad 20 T6, and then connected to external connector 16 A through another conductive trace 22 on circuit board 12. Each conductive trace 22 is essentially a portion of the conductive track which electrically connects conductive pads together or to an external connection. Specifically, for example, as will be shown, source conductive pad 18 T1, drain conductive pad 20 T2, and traces 22, and external connector 16 A form a conductive track that provides an output connection for the half-bridge circuit that is formed by MOSFETs T1 and T6.
Now continuing with the description of the first embodiment, conductive pads 18 T2, and 18 T3 are similarly connected to conductive pads 20 T5 and 20 T4 and then to external connectors 16 B and 16 C in a similar manner. As a result, source contacts of high side MOSFETs T1, T2, T3 are electrically connected to drain contacts of respective low side MOSFETs T6, T5, T4 and then connected to external connectors 16 A, 16 B, 16 C, which serve as output connections for each half-bridge circuit without using any wirebonds.
First circuit board 12 also includes gate conductive pads 24 T1, 24 T2, 24 T3 each for receiving a respective gate contact of high side MOSFETs T1, T2, T3. Gate conductive pad 24 T1 is connected via a trace 22 to external connector 16 G1, which serves as the gate connection for receiving a gate signal for high side MOSFET T1. Similarly, gate pads 24 T2 and 24 T3 are connected to output connectors 16 G2 and 16 G3 respectively via traces 22. Connectors 16 G2, 16 G3 serve as gate connections for high side MOSFETs T2, T3.
Referring now to FIG. 5, second circuit board 14 includes drain conductive pads 20 T1, 20 T2, 20 T3 for receiving drain contacts of high side MOSFETs T1, T2, T3. Second circuit board 14 also includes interconnect conductive pads 28 V+ and 28 Vground. Drain conductive pads 20 T1, 20 T2, 20 T3 are formed on the same conductive trace as interconnect conductive pads 28 V+. Interconnect pads 28 V+ are electrically connectable to interconnect pad 29 V+ on first circuit board 12, which is electrically connected to external connector 16 V+ via a trace 22. As a result drain contacts of high side MOSFET T1, T2, T3 will be connected electrically to external connector 16 V+. External connector 16 V+ in the first embodiment of the present invention serves as the connection to the input power V+, when second circuit board 14 is disposed over first circuit board 12.
Second circuit board 14 also includes gate conductive pads 24 T4, 24 T5, 24 T6 for receiving gate contacts of low side MOSFETs T4, T5, T6. Each gate conductive pad 24 T4, 24 T5, 24 T6 is electrically connected to gate interconnect pads 28 G4, 28 G5, 28 G6 via a respective trace 22. Each gate interconnect pad 28 G4, 28 G5, 28 G6 is then connected to a corresponding gate interconnect pad 29 G4, 29 G5, 29 G6 on first circuit board 12, and thereby electrically connected via a respective trace 22 to a corresponding gate connector 16 G4, 16 G5, 16 G6.
Also disposed on second circuit board 14 are source conductive pads 18 T4, 18 T5, 18 T6, and ground interconnect pads 28 ground. Source conductive pads 18 T4, 18 T5, 18 T6 and ground interconnect pads 28 ground are formed on a common conductive track and, therefore, are electrically connected together. Ground interconnect pads 28 ground on second circuit board 14 are connected to corresponding ground interconnect pads 29 ground on first circuit board 12, which are in turn connected via a common trace 32 to external ground connector 16 ground. As a result, source contacts of low side MOSFETs T4, T5, T6 are connectable to a ground connection via external connector 16 ground.
Referring now to FIGS. 6 and 7, source contact, e.g. ST1, of each high side MOSFET T1, T2, T3 is electrically connected to a corresponding source conductive pad 18 T1, 18 T2, 18 T3, and each gate contact, e.g. GT1, of each high side MOSFET T1, T2, T3 is electrically connected to a corresponding gate conductive pad 24 T1, 24 T2, 24 T3. Also, each drain contact, e.g. DT6, of each low side MOSFET T4, T5, T6 is electrically connected to its corresponding drain conductive pad, e.g. 20 T6, on first circuit board 12. Electrical connection in each case is made by a layer of conductive adhesive 33 such as solder or conductive epoxy. It should be noted that source contact and the gate contact of each MOSFET are exposed through a solder passivation 19 (shown by crossing lines in FIG. 6) layer which prevents the solder (or any other conductive adhesive) from shorting the gate contact to the source contact.
Referring now specifically to FIG. 7, second circuit board 14 is assembled opposite first circuit board 12 such that drain contact, e.g. DT1 of each high side MOSFET T1, T2, T3 is electrically connected via a layer of conductive adhesive 33 to its corresponding drain conductive pad, e.g. 20 T1, on second circuit board 14. Similarly, source contact, e.g. ST6, of each low side MOSFET T4, T5, T6 is electrically connected via a layer of conductive adhesive 33 to its corresponding source conductive pad, e.g. 18T6 on second circuit board 14, and gate contact, e.g. GT6, of each low side MOSFET, T4, T5, T6, is electrically connected to its corresponding gate conductive pad, e.g. 24 T6, via a layer of conductive adhesive 33.
Also shown in FIG. 7, is interconnect 35 which electrically connects ground conductive pad 29 ground on first circuit board 12 to ground conductive pad 28 ground on second circuit board 14. Interconnect 35 is connected to each conductive pad via a layer of conductive adhesive 33. Interconnect 35 may be any conductive body such as a copper slug.
FIG. 7 shows that low side MOSFET T6, high side MOSFET T1 and interconnect 35 are connected between first circuit board 12 and second circuit board 14. The remaining high side MOSFETs T2, T3 and low side MOSFETs T4, T5 are connected in the same manner as that of high side MOSFET T1 and low side MOSFET T6. Furthermore, interconnects are used to connect internal gate conductive pads 28 G4, 28 G5, 28 G6 to internal conductive pads 29 G4, 29 G5, 29 G6, and internal conductive pads 28 V+ to conductive pads 29 V+ in the same manner as described for interconnect 35 above.
Referring now to FIG. 8, once second circuit board 14 is assembled over first circuit board 12, an epoxy underfilling 37 is provided in the spaces between first circuit board 12 and second circuit board 14. The purpose of epoxy underfilling 37 is to protect MOSFETs from environmental conditions such as moisture. As shown by FIG. 8, a heatsink 40 may be thermally coupled to second circuit board 14 to assist in heat dissipation. Heatsink 40 may also be coupled to first circuit board 12 without deviating from the present invention
According to an aspect of the present invention, each circuit board 12, 14 may receive a heatsink to effect double-sided cooling. Advantageously, because of double-sided cooling, smaller heatsinks can be used (instead of one large heatsink) thereby reducing the overall size of the package.
Referring now to FIGS. 9A–9D, semiconductor package 10 according to the present invention is manufactured according to the following process. First, solder paste (shown by slanted lines) or some other conductive adhesive is printed on the conductive pads on first circuit board 12. Next, as illustrated by FIG. 9B, high side MOSFETs T1, T2, T3 and low side MOSFETs T4, T5, T6 are placed on their respective positions on first circuit board 12. Thereafter, as illustrated by FIG. 9C, solder paste (shown by slanted lines) or some other conductive adhesive is printed on the conductive pads on second circuit board 14, and, as shown by FIG. 9D, second circuit board 14 is placed over first circuit and then the entire structure is heated to cause the solder paste to be reflown. Thereafter, epoxy is disposed to fill the space between first circuit board 12 and second circuit board 14.
According to the preferred embodiment of the present invention, a plurality of first circuit boards 12 may be linked together to form a large panel and MOSFETs T1, T2, T3, T4, T5, T6 and second circuit boards 14 may be placed by a pick-and-place machine. Then, first circuit boards 12 are cut from the large panel to form individual packages after epoxy underfilling has been applied.
Referring now to FIG. 10, a package according to a second embodiment of the present invention may include external connectors on more than one side.
Referring to FIG. 11, a package according to the third embodiment of the present invention may include plug-type external connectors 39, which are adapted to be received in corresponding sockets, for example, in another circuit board. An example of such arrangement is shown by FIG. 12, in which a package according to the third embodiment of the present invention is shown assembled onto circuit board 42 having sockets (not shown) for receiving external conductors 39.
Referring now to FIG. 13, a package according to the first embodiment of the present invention may be integrated with another circuit board by having external connectors 16 electrically connected to corresponding lands. Specifically, FIG. 13 shows circuit board 44 having a plurality of conductive lands 45 for receiving external connectors 16 of a package according to the first embodiment of the present invention. FIG. 14 illustrates the assembly of package 10 according to the present invention onto circuit board 44. Circuit board 44 may include other components 47, which may be operatively connected to the components within package 10. Components 47, may be, for example, circuit elements for controlling the MOSFETs in package 10.
Referring to FIG. 15, according to an aspect of the present invention, a circuit board including a package according to the present invention may be adapted for mounting, and mounted to the body of a device, thereby forming, for example, a device having an integral control mechanism. Specifically, for example, circuit board 44 containing package 10, which includes three-half bridge circuits, may include a control circuitry for driving each half-bridge circuit, and mounted on the body of a three-phase motor 50. Each phase of motor 50 may then be operatively connected to the output connectors of package 10, thereby forming a motor package with an integral drive circuitry.
A package according to the present invention is not restricted to half-bridge circuits. Referring for example to FIGS. 16 and 17, a package according to the fourth embodiment of the present invention may be configured to include the power components for a three-phase synchronous buck converter as shown by FIG. 16. As is well known, a synchronous buck converter includes two series connected power switching elements, such as power MOSFETs, one of which is referred to as a control MOSFET 50, and the other as a synchronous MOSFET 52. Also, as is well known, a schottky diode 54 is connected between the source and the drain of the synchronous MOSFET 52. A three-phase synchronous buck converter is essentially three synchronous buck converters connected together.
Referring specifically to FIG. 17, a package according to the fourth embodiment includes first circuit board 12, second circuit board 14, control MOSFETs 50, synchronous MOSFETs 52, and schottky diodes 54. According to the present invention, circuit boards 12, 14 include conductive pads 51 formed on selected areas of conductive tracks 30 on each circuit board for electrical connections to, for example, electrical contacts of MOSFETs 50, 52, and schottky diodes 54, as well as conductive pads for receiving interconnects 56 for internal connection of the elements within the package. Similar to the first embodiment, a package according to the fourth embodiment may be manufactured by first placing the power components on first circuit board 12 as described earlier, printing solder paste (or some other conductive adhesive) on conductive pads of second circuit board 14, placing second circuit board 14 over first circuit board 12 and then reflowing the solder paste. Thereafter, the space between circuit boards 12, 14 may be filled with epoxy 37.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims (20)

1. A semiconductor package comprising:
a first circuit board including at least one conductive pad disposed on a major surface thereof;
a second circuit board including at least one conductive pad on a major surface thereof; and
a semiconductor die including a first electrical contact on a first major surface thereof and a second electrical contact on a second major surface thereof;
a first layer of conductive adhesive interposed between, and mechanically connected to, said first electrical contact and said at least one conductive pad on said first circuit board; and
a second layer of conductive adhesive interposed between, and mechanically connected to, said second electrical contact and said at least one conductive pad on said second circuit board; whereby said first electrical contact is electrically connected to said at least one conductive pad on said first circuit board and said second electrical contact is electrically connected to said at least one conductive pad on said second circuit board.
2. A semiconductor package according to claim 1, further comprising terminals electrically connected to said first electrical contact and said second electrical contact of said semiconductor die, said terminals being disposed on at least one of said substrates.
3. A semiconductor package according to claim 1, wherein each of said circuit board is an insulated metal substrate.
4. A semiconductor package according to claim 1, wherein said semiconductor die is a switching power semiconductor device which includes a control terminal, said control terminal being disposed on one of said first major surface of said die and said second major surface of said die and electrically connected to a conductive pad on one of said circuit boards, and electrically connected to a terminal disposed on one of said circuit boards.
5. A semiconductor package according to claim 1, wherein said semiconductor die is one of a MOSFET and an IGBT.
6. A semiconductor package according to claim 1, wherein said conductive adhesive is either one of solder and conductive epoxy.
7. A semiconductor package according to claim 1, further comprising an epoxy underfilling disposed between said circuit boards.
8. A semiconductor package according to claim 1, further comprising a heatsink disposed on one of said circuit boards.
9. A semiconductor package according to claim 1, further comprising at least one heatsink disposed on each of said circuit boards.
10. A semiconductor package comprising:
a first thermally conductive substrate including a plurality of conductive pads disposed on a first major surface thereof;
a second thermally conductive substrate including a plurality of conductive pads disposed on a first major surface thereof;
a plurality of power semiconductor devices each including a first power contact on a first major surface thereof, a second power contact and a control contact on a second opposing major surface thereof;
a first layer of conductive adhesive interposed between, and mechanically connected to, a first power contact of each power semiconductor device and a respective conductive pad on said first thermally conductive substrate,
a second layer of conductive adhesive interposed between, and mechanically connected to, a second power contact of each power semiconductor device and a respective conductive pad on said second thermally conductive substrate;
and a third layer of conductive adhesive interposed between, and mechanically connected to, a control contact of each power semiconductor device and a respective conductive pad on said second thermally conductive substrate;
whereby each one of said contacts of said power semiconductor devices is electrically connected to a respective one of said plurality of conductive pads, and wherein said conductive pads on said thermally conductive substrate are interconnected to form part of a circuit.
11. A semiconductor package according to claim 10, further comprising output terminals connected to said power semiconductor devices through said conductive pads and disposed on at least one of said substrates.
12. A semiconductor package according to claim 10, wherein said thermally conductive substrate are insulated metal substrates.
13. A semiconductor package according to claim 10, wherein said power semiconductor devices are one of power MOSFETs and IGBTs.
14. A semiconductor package according to claim 10, wherein said conductive adhesive is one of solder and conductive epoxy.
15. A semiconductor package according to claim 10, wherein said power semiconductor devices are connected in a half-bridge configuration.
16. A semiconductor package according to claim 10, wherein said power semiconductor device are connected to form a plurality of half-bridge configurations.
17. A semiconductor package according to claim 10, further comprising a control device for controlling the operation of said power semiconductor devices.
18. A semiconductor package according to claim 10, further comprising epoxy filling spaces between said first and second thermally conductive substrates.
19. A semiconductor package according to claim 10, further comprising at least one heatsink in thermal contact with one of said thermally conductive substrates.
20. A semiconductor package according to claim 10, further comprising a heatsink in thermal contact with each one of said conductive substrates.
US10/677,069 2002-10-04 2003-10-01 Semiconductor device package Expired - Lifetime US7045884B2 (en)

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PCT/US2003/031362 WO2004034428A2 (en) 2002-10-04 2003-10-02 Semiconductor device package
DE10393437T DE10393437T5 (en) 2002-10-04 2003-10-02 Semiconductor device assembly
AU2003277266A AU2003277266A1 (en) 2002-10-04 2003-10-02 Semiconductor device package
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US20060128067A1 (en) 2006-06-15
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