US7041586B2 - Semiconductor device having a multilayer interconnection structure - Google Patents
Semiconductor device having a multilayer interconnection structure Download PDFInfo
- Publication number
- US7041586B2 US7041586B2 US10/105,190 US10519002A US7041586B2 US 7041586 B2 US7041586 B2 US 7041586B2 US 10519002 A US10519002 A US 10519002A US 7041586 B2 US7041586 B2 US 7041586B2
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- insulation film
- interlayer insulation
- film
- conductor pattern
- depression
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
TABLE 1 | ||||
[Cu] | [Al] | [W] | ||
plasma SiO2 film | 120 Å/min | 130 Å/min | 110 Å/min | ||
plasma SiN film | 350 | 300 | 240 | ||
organic SOG film | 10 | 12 | 13 | ||
Claims (14)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/105,190 US7041586B2 (en) | 1998-03-24 | 2002-03-26 | Semiconductor device having a multilayer interconnection structure |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10-075938 | 1998-03-24 | ||
JP07593898A JP3469771B2 (en) | 1998-03-24 | 1998-03-24 | Semiconductor device and manufacturing method thereof |
US09/274,976 US6417116B2 (en) | 1998-03-24 | 1999-03-23 | Semiconductor device having a multilayer interconnection structure |
US10/105,190 US7041586B2 (en) | 1998-03-24 | 2002-03-26 | Semiconductor device having a multilayer interconnection structure |
Related Parent Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/274,976 Division US6417116B2 (en) | 1998-03-24 | 1999-03-23 | Semiconductor device having a multilayer interconnection structure |
US09/274,976 Continuation US6417116B2 (en) | 1998-03-24 | 1999-03-23 | Semiconductor device having a multilayer interconnection structure |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020151190A1 US20020151190A1 (en) | 2002-10-17 |
US7041586B2 true US7041586B2 (en) | 2006-05-09 |
Family
ID=13590698
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/274,976 Expired - Lifetime US6417116B2 (en) | 1998-03-24 | 1999-03-23 | Semiconductor device having a multilayer interconnection structure |
US10/105,190 Expired - Lifetime US7041586B2 (en) | 1998-03-24 | 2002-03-26 | Semiconductor device having a multilayer interconnection structure |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/274,976 Expired - Lifetime US6417116B2 (en) | 1998-03-24 | 1999-03-23 | Semiconductor device having a multilayer interconnection structure |
Country Status (4)
Country | Link |
---|---|
US (2) | US6417116B2 (en) |
JP (1) | JP3469771B2 (en) |
KR (1) | KR100327297B1 (en) |
TW (1) | TW408437B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040248406A1 (en) * | 2003-06-04 | 2004-12-09 | Sung-Un Kwon | Local interconnection method and structure for use in semiconductor device |
US20050070086A1 (en) * | 2003-09-26 | 2005-03-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6904675B1 (en) * | 1996-09-27 | 2005-06-14 | Hewlett-Packard Development, L.P. | Method of forming electrical interconnects having electromigration-inhibiting plugs |
KR100559037B1 (en) * | 1999-11-23 | 2006-03-10 | 주식회사 하이닉스반도체 | Metal line and method for fabricating of the same |
KR100571259B1 (en) * | 1999-12-23 | 2006-04-13 | 주식회사 하이닉스반도체 | Method for forming damascene pattern of semiconductor device |
US6476775B1 (en) * | 2000-03-13 | 2002-11-05 | Rcd Technology Corporation | Method for forming radio frequency antenna |
US6410437B1 (en) * | 2000-06-30 | 2002-06-25 | Lam Research Corporation | Method for etching dual damascene structures in organosilicate glass |
JP3566203B2 (en) * | 2000-12-06 | 2004-09-15 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP3639223B2 (en) | 2001-05-14 | 2005-04-20 | 松下電器産業株式会社 | Method for forming buried wiring |
KR100421278B1 (en) * | 2001-06-26 | 2004-03-09 | 주식회사 하이닉스반도체 | Fabricating method for semiconductor device |
JP2003077920A (en) | 2001-09-04 | 2003-03-14 | Nec Corp | Method for forming metal wiring |
US6559543B1 (en) * | 2001-11-16 | 2003-05-06 | International Business Machines Corporation | Stacked fill structures for support of dielectric layers |
JP4250006B2 (en) * | 2002-06-06 | 2009-04-08 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US7319065B1 (en) * | 2003-08-08 | 2008-01-15 | Advanced Micro Devices, Inc. | Semiconductor component and method of manufacture |
US6974772B1 (en) * | 2004-08-19 | 2005-12-13 | Intel Corporation | Integrated low-k hard mask |
US7834459B2 (en) * | 2004-10-26 | 2010-11-16 | Rohm Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
KR102321209B1 (en) * | 2014-11-03 | 2021-11-02 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
KR102534051B1 (en) * | 2018-04-06 | 2023-05-18 | 삼성디스플레이 주식회사 | Connecting struture of conductive layer |
CN113611663A (en) * | 2021-08-23 | 2021-11-05 | 上海芯物科技有限公司 | Method for flattening surface of semiconductor, semiconductor manufactured by same and application of semiconductor |
Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4678709A (en) * | 1982-09-15 | 1987-07-07 | Raychem Corporation | Electrical insulation |
US5444023A (en) * | 1993-01-11 | 1995-08-22 | Nec Corporation | Method of fabricating a semiconductor device having a multilayer wiring structure and using a fluorine compound-containing gas |
JPH09172016A (en) | 1995-12-21 | 1997-06-30 | Ricoh Co Ltd | Semiconductor device manufacturing method |
US5751056A (en) * | 1994-05-31 | 1998-05-12 | Texas Instruments Incorporated | Reliable metal leads in high speed LSI semiconductors using dummy leads |
US5821162A (en) * | 1995-07-14 | 1998-10-13 | Yamaha Corporation | Method of forming multi-layer wiring utilizing SOG |
US5850102A (en) * | 1996-04-03 | 1998-12-15 | Kabushiki Kaisha Toshiba | Semiconductor device having a second insulating layer which includes carbon or fluorine at a density lower than a first insulating layer |
US5877076A (en) * | 1997-10-14 | 1999-03-02 | Industrial Technology Research Institute | Opposed two-layered photoresist process for dual damascene patterning |
US5882996A (en) * | 1997-10-14 | 1999-03-16 | Industrial Technology Research Institute | Method of self-aligned dual damascene patterning using developer soluble arc interstitial layer |
US5892269A (en) * | 1996-02-29 | 1999-04-06 | Sanyo Electric Co., Ltd. | Semiconductor device including an intrusion film layer |
US5939788A (en) | 1998-03-11 | 1999-08-17 | Micron Technology, Inc. | Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper |
US5965934A (en) * | 1994-12-21 | 1999-10-12 | Advanced Micro Devices, Inc. | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS |
US5981374A (en) * | 1997-04-29 | 1999-11-09 | International Business Machines Corporation | Sub-half-micron multi-level interconnection structure and process thereof |
US5981377A (en) * | 1997-02-28 | 1999-11-09 | Sony Corporation | Semiconductor device with improved trench interconnected to connection plug mating and method of making same |
US6017813A (en) * | 1998-01-12 | 2000-01-25 | Vanguard International Semiconductor Corporation | Method for fabricating a damascene landing pad |
US6030904A (en) | 1997-08-21 | 2000-02-29 | International Business Machines Corporation | Stabilization of low-k carbon-based dielectrics |
US6043145A (en) | 1996-03-13 | 2000-03-28 | Sony Corporation | Method for making multilayer wiring structure |
US6051321A (en) | 1997-10-24 | 2000-04-18 | Quester Technology, Inc. | Low dielectric constant materials and method |
US6071807A (en) * | 1996-12-25 | 2000-06-06 | Sanyo Electric Company, Ltd. | Fabrication method of semiconductor device including insulation film with decomposed organic content |
US6071806A (en) * | 1998-07-28 | 2000-06-06 | United Microelectronics Corp. | Method for preventing poisoned vias and trenches |
US6165899A (en) | 1997-10-31 | 2000-12-26 | Nec Corporation | Method for manufacturing semiconductor devices having dual damascene structure |
US6180512B1 (en) * | 1997-10-14 | 2001-01-30 | Industrial Technology Research Institute | Single-mask dual damascene processes by using phase-shifting mask |
US6204168B1 (en) * | 1998-02-02 | 2001-03-20 | Applied Materials, Inc. | Damascene structure fabricated using a layer of silicon-based photoresist material |
US6225217B1 (en) * | 1997-06-27 | 2001-05-01 | Nec Corporation | Method of manufacturing semiconductor device having multilayer wiring |
US6420269B2 (en) * | 1996-02-07 | 2002-07-16 | Hitachi Chemical Company, Ltd. | Cerium oxide abrasive for polishing insulating films formed on substrate and methods for using the same |
US6518170B2 (en) * | 2000-06-21 | 2003-02-11 | Nec Corporation | Method of manufacturing a semiconductor device |
US6541396B2 (en) * | 1999-05-18 | 2003-04-01 | Nec Corporation | Method of manufacturing a semiconductor device using a low dielectric constant organic film grown in a vacuum above an inlaid interconnection layer |
US6825132B1 (en) * | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2643793B2 (en) * | 1993-09-14 | 1997-08-20 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
JPH07111263A (en) * | 1993-10-14 | 1995-04-25 | Kawasaki Steel Corp | W plug forming method |
JP2751820B2 (en) * | 1994-02-28 | 1998-05-18 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JPH08124926A (en) * | 1994-10-20 | 1996-05-17 | Oki Electric Ind Co Ltd | Formation of wiring |
-
1998
- 1998-03-24 JP JP07593898A patent/JP3469771B2/en not_active Expired - Lifetime
-
1999
- 1999-03-23 TW TW088104613A patent/TW408437B/en not_active IP Right Cessation
- 1999-03-23 KR KR1019990009864A patent/KR100327297B1/en not_active IP Right Cessation
- 1999-03-23 US US09/274,976 patent/US6417116B2/en not_active Expired - Lifetime
-
2002
- 2002-03-26 US US10/105,190 patent/US7041586B2/en not_active Expired - Lifetime
Patent Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4678709A (en) * | 1982-09-15 | 1987-07-07 | Raychem Corporation | Electrical insulation |
US5444023A (en) * | 1993-01-11 | 1995-08-22 | Nec Corporation | Method of fabricating a semiconductor device having a multilayer wiring structure and using a fluorine compound-containing gas |
US5751056A (en) * | 1994-05-31 | 1998-05-12 | Texas Instruments Incorporated | Reliable metal leads in high speed LSI semiconductors using dummy leads |
US5965934A (en) * | 1994-12-21 | 1999-10-12 | Advanced Micro Devices, Inc. | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS |
US5821162A (en) * | 1995-07-14 | 1998-10-13 | Yamaha Corporation | Method of forming multi-layer wiring utilizing SOG |
JPH09172016A (en) | 1995-12-21 | 1997-06-30 | Ricoh Co Ltd | Semiconductor device manufacturing method |
US6420269B2 (en) * | 1996-02-07 | 2002-07-16 | Hitachi Chemical Company, Ltd. | Cerium oxide abrasive for polishing insulating films formed on substrate and methods for using the same |
US5892269A (en) * | 1996-02-29 | 1999-04-06 | Sanyo Electric Co., Ltd. | Semiconductor device including an intrusion film layer |
US6825132B1 (en) * | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
US6043145A (en) | 1996-03-13 | 2000-03-28 | Sony Corporation | Method for making multilayer wiring structure |
US5850102A (en) * | 1996-04-03 | 1998-12-15 | Kabushiki Kaisha Toshiba | Semiconductor device having a second insulating layer which includes carbon or fluorine at a density lower than a first insulating layer |
US6127256A (en) * | 1996-04-03 | 2000-10-03 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6071807A (en) * | 1996-12-25 | 2000-06-06 | Sanyo Electric Company, Ltd. | Fabrication method of semiconductor device including insulation film with decomposed organic content |
US5981377A (en) * | 1997-02-28 | 1999-11-09 | Sony Corporation | Semiconductor device with improved trench interconnected to connection plug mating and method of making same |
US5981374A (en) * | 1997-04-29 | 1999-11-09 | International Business Machines Corporation | Sub-half-micron multi-level interconnection structure and process thereof |
US6225217B1 (en) * | 1997-06-27 | 2001-05-01 | Nec Corporation | Method of manufacturing semiconductor device having multilayer wiring |
US6030904A (en) | 1997-08-21 | 2000-02-29 | International Business Machines Corporation | Stabilization of low-k carbon-based dielectrics |
US5882996A (en) * | 1997-10-14 | 1999-03-16 | Industrial Technology Research Institute | Method of self-aligned dual damascene patterning using developer soluble arc interstitial layer |
US6180512B1 (en) * | 1997-10-14 | 2001-01-30 | Industrial Technology Research Institute | Single-mask dual damascene processes by using phase-shifting mask |
US5877076A (en) * | 1997-10-14 | 1999-03-02 | Industrial Technology Research Institute | Opposed two-layered photoresist process for dual damascene patterning |
US6051321A (en) | 1997-10-24 | 2000-04-18 | Quester Technology, Inc. | Low dielectric constant materials and method |
US6165899A (en) | 1997-10-31 | 2000-12-26 | Nec Corporation | Method for manufacturing semiconductor devices having dual damascene structure |
US6017813A (en) * | 1998-01-12 | 2000-01-25 | Vanguard International Semiconductor Corporation | Method for fabricating a damascene landing pad |
US6204168B1 (en) * | 1998-02-02 | 2001-03-20 | Applied Materials, Inc. | Damascene structure fabricated using a layer of silicon-based photoresist material |
US20030062627A1 (en) * | 1998-02-02 | 2003-04-03 | Applied Materials, Inc. | Damascene structure fabricated using a layer of silicon-based photoresist material |
US5939788A (en) | 1998-03-11 | 1999-08-17 | Micron Technology, Inc. | Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper |
US6071806A (en) * | 1998-07-28 | 2000-06-06 | United Microelectronics Corp. | Method for preventing poisoned vias and trenches |
US6541396B2 (en) * | 1999-05-18 | 2003-04-01 | Nec Corporation | Method of manufacturing a semiconductor device using a low dielectric constant organic film grown in a vacuum above an inlaid interconnection layer |
US6518170B2 (en) * | 2000-06-21 | 2003-02-11 | Nec Corporation | Method of manufacturing a semiconductor device |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070141834A1 (en) * | 2003-06-04 | 2007-06-21 | Samsung Electronics Co., Ltd. | Local interconnection method and structure for use in semiconductor device |
US7498253B2 (en) | 2003-06-04 | 2009-03-03 | Samsung Electronics Co., Ltd. | Local interconnection method and structure for use in semiconductor device |
US7202163B2 (en) * | 2003-06-04 | 2007-04-10 | Samsung Electronics Co., Ltd. | Local interconnection method and structure for use in semiconductor device |
US20040248406A1 (en) * | 2003-06-04 | 2004-12-09 | Sung-Un Kwon | Local interconnection method and structure for use in semiconductor device |
US7400045B2 (en) | 2003-09-26 | 2008-07-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20070187832A1 (en) * | 2003-09-26 | 2007-08-16 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US7215028B2 (en) | 2003-09-26 | 2007-05-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20090017611A1 (en) * | 2003-09-26 | 2009-01-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20050070086A1 (en) * | 2003-09-26 | 2005-03-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US7935623B2 (en) | 2003-09-26 | 2011-05-03 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US20110171824A1 (en) * | 2003-09-26 | 2011-07-14 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US8329572B2 (en) | 2003-09-26 | 2012-12-11 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US8648472B2 (en) | 2003-09-26 | 2014-02-11 | Panasonic Corporation | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US20020151190A1 (en) | 2002-10-17 |
JPH11274122A (en) | 1999-10-08 |
KR19990078156A (en) | 1999-10-25 |
US20010044201A1 (en) | 2001-11-22 |
KR100327297B1 (en) | 2002-03-04 |
TW408437B (en) | 2000-10-11 |
JP3469771B2 (en) | 2003-11-25 |
US6417116B2 (en) | 2002-07-09 |
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