US7019363B1 - MOS transistor with asymmetrical source/drain extensions - Google Patents
MOS transistor with asymmetrical source/drain extensions Download PDFInfo
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- US7019363B1 US7019363B1 US09/476,961 US47696100A US7019363B1 US 7019363 B1 US7019363 B1 US 7019363B1 US 47696100 A US47696100 A US 47696100A US 7019363 B1 US7019363 B1 US 7019363B1
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- extension
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- 230000005669 field effect Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 25
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- 239000004065 semiconductor Substances 0.000 abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 3
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- 239000007943 implant Substances 0.000 description 30
- 239000000758 substrate Substances 0.000 description 18
- 125000006850 spacer group Chemical group 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
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- 229910052751 metal Inorganic materials 0.000 description 3
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- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
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- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Definitions
- the present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a transistor and a method of manufacturing it.
- the transistor includes asymmetrical source/drain extensions.
- Integrated circuits such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more.
- the ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS).
- CMOS complementary metal oxide semiconductor
- FETS field effect transistors
- the transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
- the drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance.
- Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
- the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate.
- the silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process vertically introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
- silicon dioxide spacers which abut lateral sides of the gate structure, are provided over the source and drain extensions.
- the substrate is vertically doped a second time to form the deeper source and drain regions.
- the source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
- the source extension and the drain extension are formed in the same fabrication process step.
- the source extension and drain extension can be formed in the same ion implantation step or the same impurity thermal defusion step.
- the source extension and the drain extension generally have identical characteristics.
- the source extension and the drain extension can have an identical dopant profile, dopant concentration, junction concentration, and junction depth.
- a shallow source extension provides better immunity to short channel effects, such as, threshold voltage-roll off and drain induced barrier lowering.
- the parasitic series resistance of the source extension also plays an important role in transistor drive current.
- the larger the source extension resistance the smaller the gate-to-source bias (Vgs), and hence the smaller the transistor drive current. Accordingly, the source extension should be as conductive as practicable.
- the drain extension may not be as important as the source extension in terms of control of short channel effects and drive current. However, it does play an important role in transistor reliability.
- An exemplary embodiment relates to a method of manufacturing an integrated circuit.
- the method includes: providing a gate structure, providing an angled source extension implant, providing an angled drain extension implant, and providing a deep source/drain implant.
- the gate structure is located between a source location and a drain location in a semiconductor substrate.
- the source extension implant is provided in a direction from the source location to the drain location.
- the drain extension implant is provided in a direction from the drain location to the source location.
- the deep source/drain implant is provided at the source location and the drain location.
- Another exemplary embodiment relates to a method of manufacturing an ultra-light scale integrated circuit including a plurality of field effect transistors.
- the method includes steps of: providing at least part of a gate structure, forming a source extension with dopants of a first conductivity type, forming a drain extension with dopants of the first conductivity type, and forming deep source and drain regions with dopants of the first conductivity type.
- the gate structure is provided at a top surface of the semiconductor substrate.
- the gate structure is located between the source and drain regions.
- the drain extension is deeper than the source extension.
- Another exemplary embodiment relates to an integrated circuit including a plurality of field effect transistors.
- Each of the transistors includes a gate structure disposed over a channel, a deep source region, a deep drain region, a source extension, and a drain extension.
- the deep source region and deep drain region are heavily doped with dopants of a first conductivity type.
- the source extension is the deep source region.
- the drain extension is integral to the deep region.
- the drain extension is deeper than the source extension.
- FIG. 1 is a cross-sectional view of a portion of an integrated circuit having a transistor with optimized source and drain extensions in accordance with an exemplary embodiment
- FIG. 2 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 1 , showing a gate structure formation step;
- FIG. 3 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 1 , showing a tilt angle source extension implant step;
- FIG. 4 is a cross-sectional view of the portion of the integrated circuit illustrated in FIG. 1 , showing a tilt angle drain extension implant step.
- a transistor 12 is disposed on a semiconductor substrate 14 , such as, a single crystal silicon wafer.
- Transistor 12 is part of a portion 10 of an integrated circuit (IC) manufactured on a wafer (such as, a silicon wafer).
- IC integrated circuit
- Transistor 12 can be an N-channel or a P-channel field effect transistor, such as, a metal oxide semiconductor field effect transistor (MOSFET).
- MOSFET metal oxide semiconductor field effect transistor
- Transistor 12 includes a gate structure 18 , a deep source region 22 , and a deep drain region 24 . Regions 22 and 24 have a concentration of 10 19 to 10 20 dopants per cubic centimeter (heavily doped, P+ or N+). Transistor 12 also includes a source extension 23 and a drain extension 25 . Transistor 12 is positioned between insulative structures 52 .
- Gate structure 18 includes a gate oxide 34 and a gate conductor 36 . Gate structure can also include a pair of insulative spacers 26 . Gate structure 18 is above a channel 31 of substrate 14 . Channel 31 is doped to a concentration of 1–5 ⁇ 10 7 P-type dopants per centimeter cubed for an N-channel transistor. Channel 31 can be appropriately configured with profile characteristics including pocket regions. Structure 18 is preferably 50 nm–250 nm wide and 1000–2000 ⁇ thick (depth).
- Spacers 26 can be a silicon nitride (Si 3 N 4 ) or silicon dioxide (SiO 2 ) material.
- Gate oxide 34 is preferably thermally grown on substrate 14 .
- Conductor 36 is preferably a metal conductor or polysilicon deposited by chemical vapor deposition (CVD) and etched to form the particular structure for transistor 12 .
- Spacers 26 are preferably formed by depositing a layer, planarizing and etching the deposited layer to leave spacers 26 . Spacers 26 are 500–800 ⁇ wide and 1000–2000 ⁇ thick.
- Source extension 23 is preferably an ultra-shallow extension (e.g., junction depth is less than 40 nanometers (nm) (e.g., 20–40 nm)), which is thinner than regions 22 and 24 and drain extension 25 .
- Source extension 23 is integral or connected with source region 22 and is disposed partially underneath gate oxide 34 .
- Extension 23 can be 40–60 nm wide.
- Ultra-shallow source extension 23 helps transistor 12 achieve substantial immunity to short-channel effects. Short-channel effects can degrade performance of transistor 12 as well as the manufacturability of the IC associated with transistor 12 .
- Source extension 23 has a concentration of 5 ⁇ 10 19 –1 ⁇ 10 20 (preferably 1 ⁇ 10 20 ) dopants per cubic centimeter.
- the conductivity of source extension 23 reduces parasitic series resistance. Decreased parasitic series resistance reduces the gate-to-source bias (Vgs) and hence increases drive current.
- Drain extension 25 is preferably an extension which is thinner than regions 22 and 24 and thicker than source extension 23 .
- Extension 25 is 40–60 nm wide and 80–120 nm junction depth (thickness).
- Extension 25 is integral or connected with drain region 24 and is disposed partially underneath gate oxide 34 .
- Drain extension 25 may not be as important as source extension 23 in terms of control of short channel effects and drive current.
- the dosage of the implant associated with drain extension 25 can play an important role in transistor reliability.
- a relatively deep and lightly doped drain extension 25 reduces the peak electric field in channel 34 and hence, reduces the possibility of hot-carrier injection into gate oxide 34 .
- transistor 12 with its asymmetric source extension 23 and drain extension 25 has an advantageous transistor performance.
- Drain extension 25 has a concentration of 1 ⁇ 10 19 –5 ⁇ 10 19 dopants per cubic centimeter.
- Transistor 12 can be at least partially covered by an insulative layer and is preferably part of an ultra-large scale integrated (ULSI) circuit that includes one million or more transistors. Conductive vias can be provided through the insulative layer to connect to regions 22 and 24 .
- ULSI ultra-large scale integrated
- transistor 12 including source extension 23 and drain extension 25 is described below as follows.
- the advantageous process allows a transistor 12 with asymmetric extensions 23 and 25 to be formed. Extensions 23 and 25 can vary from each other with respect to depth, size, dopant concentration, junction concentration, dopant, etc.
- Source extension 23 and drain extension 25 are preferably formed in different ion implantation steps. Preferably, tilted implantation steps in which high energy ions which strike substrate 14 at an angle are utilized. Source extension 23 and drain extension 25 can be implanted at different angles and with different dopants at different energies to form asymmetric extensions 23 and 25 . The different angles can satisfy the different requirements for the characteristics of extension 23 and extension 25 .
- transistor 12 can be substantially formed by conventional semiconductor processing techniques to form gate structure 18 including gate oxide 34 and gate conductor 36 .
- Conventional LOCOS or shallow trench isolation processes can be used to form insulative structures 52 .
- Gate structure 18 is formed on substrate 14 which is doped with 1–5 ⁇ 10 17 P-type dopants per cubic centimeter, assuming an N-channel transistor. Gate structure 18 can be formed by depositing or growing a dielectric layer on substrate 14 and a metal or polysilicon layer over the dielectric layer and etching to leave conductor 36 and oxide 34 as structure 18 via a lithographic process. Structure 18 is above channel 31 between structures 52 .
- substrate 14 is subjected to a source extension implant (the source extension implant can be angled (e.g., 30–60°) from a top surface 65 of substrate 14 ) to implant dopants from a source location side 60 to a drain location side 62 .
- a source extension implant can be angled (e.g., 30–60°) from a top surface 65 of substrate 14 ) to implant dopants from a source location side 60 to a drain location side 62 .
- an N-type dopant such as arsenic
- an N-type dopant such as arsenic
- Regions 66 and 68 are 6–8 nm deep (e.g., below surface 65 ) (20 percent of final depth of extension 23 ).
- region 66 extends underneath gate structure 18 while region 68 is set apart from gate structure 18 .
- the shadowing effect associated with gate structure 18 protects drain location side 62 from the N-type dopants.
- P-type dopants such as boron
- P-type dopants can be accelerated to an energy of 200 eV–1 KeV at a dose of 10 14 dopants per centimeters squared to form region 66 .
- substrate 14 is subjected to a drain extension implant.
- the drain extension implant can be angled (e.g., 30–60° from top surface 65 of substrate 14 ) from a drain location side 62 to a source location side 60 .
- an N-dopant such as, phosphorous
- an energy of 5–15 KeV is accelerated to an energy of 5–15 KeV at a dose of 10 14 dopants per centimeter squared to form N-type regions 70 and 72 for an N-channel transistor.
- Regions 70 and 72 are 8–12 nm deep (e.g., below surface 65 ) (20 percent of the final depth of extension 25 ).
- region 72 extends underneath gate structure 18 while region 70 is set apart from gate structure 18 .
- the shadowing effect associated with gate structure 18 protects source location side 60 from N-type dopants.
- P-type dopants such as boron diflouride (BF 2 ) can be accelerated to an energy of 5–10 KeV at a dose of 10 14 dopants per centimeters squared.
- spacers 26 are formed in a conventional deposition and etch back process.
- spacers 26 are silicon dioxide or silicon nitride spacers.
- a deep source/drain implant is provided at an angle of 90° with respect to top surface 65 of substrate 14 .
- the deep source/drain implant is provided at an energy level of 15 KeV–40 KeV (N-type using As) and a dosage of 1 ⁇ 10 15 –4 ⁇ 10 25 dopants per centimeter squared.
- the deep source/drain implant forms deep source region 22 and drain region 24 having a concentration of 10 19-21 dopants per centimeter cubed.
- Conductor 36 can also be doped during the deep source/drain implant.
- substrate 14 is subjected to a rapid thermal anneal to activate dopants in regions 22 and 24 , and extensions 23 and 25 .
- CMOS processes can be utilized to form other structures associated with portion 10 including interconnects, metal layers or other structures.
- the combination of the source extension implant, drain extension implant, and deep source and drain implant results in the source and drain profile illustrated in FIG. 1 .
- the profile advantageously includes extension 23 which is thinner and more conductive than extension 25 .
- Source extension 23 is preferably formed by a low energy and a high dose ion implantation technique.
- the low energy and high dose ion implantation technique makes a shallow and highly conductive junction for extension 23 .
- Shallow source extension 23 provides better control of short-channel effects, while a highly conductive source extension 23 reduces current degradation due to series resistance.
- Drain extension 25 is preferably formed by a medium energy and low dose ion implantation technique.
- the medium and low dose ion implantation technique makes a relatively deeper and lightly doped drain extension 25 .
- a lightly doped drain extension 25 with medium depth provides better reliability under hot-carrier injection stress.
- arsenic is described as utilized for source extension 23 and phosphorous is described as being utilized for extension 25
- other impurities or dopants can be utilized depending upon the design requirements for transistor 12 .
- different thermal annealing techniques can be utilized for source extension 23 and drain extension 25 depending upon transistor design requirement.
- the drain extension implant can be performed before the source extension implant.
- transistor 12 can be fabricated as a P-channel transistor utilizing the method described in FIGS. 1–4 , where N-type dopants are exchanged for P-type dopants and vice versa.
- FIGS. 1–4 the method described in FIGS. 1–4 , where N-type dopants are exchanged for P-type dopants and vice versa.
Abstract
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US09/476,961 US7019363B1 (en) | 2000-01-04 | 2000-01-04 | MOS transistor with asymmetrical source/drain extensions |
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US09/476,961 US7019363B1 (en) | 2000-01-04 | 2000-01-04 | MOS transistor with asymmetrical source/drain extensions |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20050285191A1 (en) * | 2004-06-29 | 2005-12-29 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
US20080302653A1 (en) * | 2007-03-29 | 2008-12-11 | Applied Materials Inc. | Method And Device For Producing An Anti-Reflection Or Passivation Layer For Solar Cells |
US20090121264A1 (en) * | 2007-11-12 | 2009-05-14 | Ching-Hung Kao | Cmos image sensor and method of forming the same |
US8497389B2 (en) | 2008-12-08 | 2013-07-30 | Initio Fuels Llc | Single step transesterification of biodiesel feedstock using a gaseous catalyst |
US20180269303A1 (en) * | 2017-03-16 | 2018-09-20 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor structures and fabrication methods thereof |
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US5935867A (en) * | 1995-06-07 | 1999-08-10 | Advanced Micro Devices, Inc. | Shallow drain extension formation by angled implantation |
US6218276B1 (en) * | 1997-12-22 | 2001-04-17 | Lsi Logic Corporation | Silicide encapsulation of polysilicon gate and interconnect |
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2000
- 2000-01-04 US US09/476,961 patent/US7019363B1/en not_active Expired - Lifetime
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US5793090A (en) | 1997-01-10 | 1998-08-11 | Advanced Micro Devices, Inc. | Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance |
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