US6999462B1 - Mapping layer 2 LAN priorities to a virtual lane in an Infiniband™ network - Google Patents

Mapping layer 2 LAN priorities to a virtual lane in an Infiniband™ network Download PDF

Info

Publication number
US6999462B1
US6999462B1 US09/881,771 US88177101A US6999462B1 US 6999462 B1 US6999462 B1 US 6999462B1 US 88177101 A US88177101 A US 88177101A US 6999462 B1 US6999462 B1 US 6999462B1
Authority
US
United States
Prior art keywords
infiniband
packet
router
service level
vlan tag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime, expires
Application number
US09/881,771
Inventor
Yatin R. Acharya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to US09/881,771 priority Critical patent/US6999462B1/en
Assigned to ADVANCED MICRO DEVICES, INC. reassignment ADVANCED MICRO DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ACHARYA, YATIN R.
Application granted granted Critical
Publication of US6999462B1 publication Critical patent/US6999462B1/en
Adjusted expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46Interconnection of networks
    • H04L12/4641Virtual LANs, VLANs, e.g. virtual private networks [VPN]
    • H04L12/4645Details on frame tagging
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • H04L47/24Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/2491Mapping quality of service [QoS] requirements between different networks

Definitions

  • the present invention relates to an InfiniBandTM router configured for sending and receiving data packets in an InfiniBandTM network and, more particularly, to a router which maps Ethernet (IEEE 802.1P) LAN priorities to a virtual lane of an InfiniBandTM network
  • processors used in servers have encountered substantial improvements, where the microprocessor speed and bandwidth have exceeded the capacity of the connected input/out (I/O) buses, limiting the server throughput to the bus capacity. Accordingly, different server standards have been proposed in an attempt to improve server performance in terms of addressing, processor clustering, and high-speed I/O.
  • the InfiniBandTM Architecture Specification specifies a high-speed networking connection between central processing units, peripherals, and switches inside a server system.
  • the InfiniBandTM network refers to a network within a server system.
  • the InfiniBandTM Architecture Specification specifies both I/O operations and interprocessor communications (IPC).
  • a particular feature of InfiniBandTM Architecture Specification is the proposed implementation in hardware of the transport layer services present in existing networking protocols, such as TCP/IP based protocols.
  • the hardware-based implementation of transport layer services provides the advantage of reducing processing requirements of the central processing unit (i.e., “offloading”), hence offloading the operating system of the server system.
  • the InfiniBandTM Architecture Specification describes a network architecture, illustrated in FIG. 1 .
  • the network 10 includes nodes 11 , each having an associated channel adapter 12 or 14 .
  • the computing node 11 a includes processors 16 and a host channel adapter (HCA) 12 ;
  • the destination target nodes 11 b and 11 c include target channel adapters 14 a and 14 b , and target devices (e.g., peripherals such as Ethernet bridges or storage devices) 18 a and 18 b , respectively.
  • the network 10 also includes routers 20 , and InfiniBandTM switches 22 .
  • Channel adapters operate as interface devices for respective server subsystems (i.e., nodes).
  • host channel adapters (HCAs) 12 are used to provide the computing node 11 a with an interface connection to the InfiniBandTM network 10
  • target channel adapters (TCAs) 14 are used to provide the destination target nodes 11 b and 11 c with an interface connection to the InfiniBandTM network.
  • Host channel adapters 12 may be connected to a memory controller 24 as illustrated in FIG. 1 .
  • Host channel adapters 12 implement the transport layer using a virtual interface referred to as the “verbs” layer that defines in the manner in which the processor 16 and the operating system communicate with the associated HCA 12 : verbs are data structures (e.g., commands) used by application software to communicate with the HCA.
  • Target channel adapters 14 lack the verbs layer, and hence communicate with their respective devices 18 according to the respective device protocol (e.g., PCI, SCSI, etc.).
  • a router is configured for sending and receiving data packets onto an InfiniBandTM network.
  • the router is configured to receive an Ethernet data packet having a VLAN tag indicative of layer 2 priority data of the Ethernet packet.
  • the router includes a mapping table having multiple entries, each entry specifying a VLAN tag and a corresponding service level.
  • a controller is configured for parsing the VLAN tag and determining the service level for the VLAN tag. The controller outputs the Ethernet packet on the InfiniBandTM network within an InfiniBandTM packet according to the determined service level.
  • Another aspect of the present invention provides a method of outputting an Ethernet packet, received by a router, onto an InfiniBandTM network.
  • the method includes receiving, by the router, an Ethernet data packet having a VLAN tag.
  • the VLAN tag is parsed and mapped to a determined service level based on the parsed VLAN tag.
  • the Ethernet packet is outputted on the InfiniBandTM network within an InfiniBandTM packet according to the determined service level.
  • FIG. 1 is a diagram illustrating a conventional network according to the InfiniBandTM Architecture Specification.
  • FIG. 2 is a diagram illustrating in detail a host channel adapter of an InfiniBandTM network according to an embodiment of the present invention.
  • FIG. 3 is a diagram illustrating the mapping layer 2 priorities in an VLAN tag of an Ethernet frame to a virtual lane in an InfiniBandTM packet.
  • FIG. 4 is a diagram illustrating a router having a VLAN tag to service level mapping table for bridging between the Ethernet domain and the InfiniBandTM domain.
  • FIG. 2 is a block diagram illustrating a host channel adapter (HCA) 12 configured for generating and transmitting packets according to an embodiment of the present invention.
  • HCA 12 compliant with the InfiniBandTM Architecture Specification, is implemented in a manner that ensures that hardware resources are efficiently utilized by generating transmit packets according to a priority-based ordering.
  • the disclosed HCA 12 provides flexibility by enabling embedded processes to be added without disruption of traffic flow.
  • the HCA 12 can be implemented in an economical manner with minimal complexity relative to conventional implementation techniques.
  • transport layer service would be performed first, for example by constructing a transport layer header, generating a packet sequence number, validating the service type (e.g., reliable connection, reliable datagram, unreliable connection, unreliable datagram, etc.), and other transport layer operations. Once the transport layer operations have been completed, the packet would be sent to the link layer service for link layer operations, including service layer and virtual lane mapping, link layer flow control packet generation, link layer transmission credit checking, and other operations.
  • this conventional type of implementation has the advantage of precisely following the network layers specified in the InfiniBandTM Architecture Specification, such an arrangement requires a substantially large amount of hardware.
  • the transport layer generally requires more processing power than the link layer because the transport layer involves more complex operations.
  • the implementation of the transport layer in hardware does not result in a substantially complex hardware system.
  • link layer operations are partitioned based on the desirability to determine priorities of data packets to be transmitted.
  • the HCA 12 includes a pre-link module configured for determining a priority of received WQEs, and a post-link module configured for preparing a data packet for transmission on the network.
  • the pre-link module 40 orders the WQEs according to priorities determined by the pre-link module, and outputs the WQEs in the determined order to a transport service module 42 configured for generating the appropriate transport layer headers for the WQEs based on the associated queue pair attributes.
  • the pre-link module 40 prevents the transport service module 42 from wasting resources on low priority WQEs or blocking high priority WQE's within the transport layer process. Hence, higher priority connections obtain improved service at the transport layer through the HCA.
  • the HCA 12 implemented for example as an application-specific integrated circuit, includes a pre-link module 40 , a transport service module 42 , a post-link module 44 , and a media access control (MAC) module 46 .
  • the HCA 12 also has local access to a memory 48 configured for storing transport data and overflow buffers, described below.
  • the pre-link module 40 includes a work queue element FIFO 50 , virtual lane FIFOs 52 , a pre-link process module 54 , a service layer to virtual lane (SL-VL) mapping table 56 , a virtual lane (VL) arbitration table 58 , and a virtual lane (VL) arbitration module 60 .
  • the HCA 12 is configured for receiving data from a central processing unit (CPU) in the form of work queue elements (WQEs), stored in the WQE FIFO 50 .
  • WQEs work queue elements
  • Each WQE specifies a corresponding request, from a consumer application executed by the CPU (i.e., “requester”), for a corresponding prescribed operation to be performed by a destination InfiniBandTM network node (i.e., “responder”), for example a target.
  • the interaction between requester and responder is specified via a queue pair (QP), where a queue pair includes a send work queue and a receive work queue.
  • QP queue pair
  • the WQE includes service level (SL) information, and a pointer to the location of the actual message in the system memory 48 .
  • SL service level
  • the InfiniBandTM Architecture Specification defines a service level (SL) attribute that permits a packet traversing the InfiniBandTM network 10 to operate at one of sixteen available service levels.
  • the requester can select an available service level (e.g., quality of service, priority, etc.) based on a selected priority of the WQE.
  • the pre-link module 40 provides both service level to virtual lane mapping (SL-VL mapping), and virtual lane arbitration.
  • virtual lanes defined in the InfiniBandTM Architecture Specification, enable multiple logical flows to be implemented over a single physical link, where link level flow control can be applied to one virtual lane without affecting other virtual lanes.
  • the pre-link process module 54 is configured for managing and maintaining the service layer-virtual layer mapping table 56 .
  • the pre-link process module 54 retrieves a WQE from the WQE FIFO 50 , and determines the corresponding virtual lane based on the service layer specified within the WQE. Upon identifying the appropriate virtual lane for the retrieved WQE, the pre-link process module 54 forwards the WQE to the corresponding virtual lane FIFO 52 .
  • the pre-link module 40 includes virtual lane FIFOs 52 a , 52 b , 52 c , 52 d , 52 e , and 52 f for storage of WQEs based on the assignment by the pre-link process module 54 .
  • the virtual lane FIFO 52 a is used for storing WQEs associated with embedded processor operations, for example link layer control packets and handling of error conditions.
  • the request is sent to an embedded processor queue 78 for further processing by an embedded processor 80 , described below; hence the embedded processor 80 has its own assigned queue 52 a for outputting packets into the flow of output data traffic.
  • the virtual lane FIFO 52 b is used for storing WQEs associated with management traffic.
  • the virtual lane FIFOs 52 c , 52 d , 52 e , and 52 f are used for storing WQEs associated with respective assigned virtual lanes. Although the disclosed embodiment discloses the use of four assigned virtual lanes, additional virtual lane FIFOs may be added for additional assigned virtual lanes.
  • the VL arbitration module 60 is implemented as a state machine with registers, and is configured for managing the VL arbitration table 58 for servicing of the virtual lanes, including setup, management, and teardown of the virtual lanes.
  • the VL arbitration module 60 also determines which virtual lane to service, and outputs the WQEs from the virtual lane FIFOs 52 based on the determined priority of the virtual lanes.
  • the virtual lane FIFO 52 b typically stores management (high-priority) traffic, hence the VL arbitration module 60 typically would empty the virtual lane FIFO 52 b before servicing the other virtual lane FIFOs 52 c , 52 d , 52 e , or 52 f .
  • the VL arbitration module 60 would then selectively output the WQEs from the virtual lane FIFOs 52 c , 52 d , 52 e , or 52 f based on weighted priorities stored in respective weight tables within the VL arbitration table 58 .
  • the pre-ink module 40 outputs the WQEs in a prescribed order based on a determined priority of the WQEs, for example based on assigned virtual lanes, or whether the WQE is for an embedded process, management traffic, or flow control traffic.
  • the transport service module 42 is configured for managing transport services, including setup, management, and teardown of queue pairs.
  • the HCA 12 includes a queue pair setup FIFO 62 configured for storing queue pair commands received from a communication management agent.
  • the communication management agent is responsible for setup and teardown of transport connections: the communication management agent communicates with a subnet manager to establish the transport connections (i.e., queue pairs) for the HCA 12 .
  • the communication management agents at each end during connection establishment use a bypass service (described below with respect to bypass service submodule 68 a ), as opposed to a conventional transport layer service, to establish the transport connections.
  • the transport service module 42 includes a queue pair attributes database 64 and a queue pair attributes management module 66 .
  • the queue pair attributes management module 66 is configured for processing the queue pair commands in the queue pair setup FIFO 62 , and updating the queue pair attributes database 64 based on the received queue pair commands.
  • the queue pair attributes database 64 stores information relating to a source queue pair number, a destination queue pair number, and possibly source agent and destination agent.
  • the queue pair attributes database 64 will include all information necessary to support the different transport services, including reliable connection service, reliable datagram service, unreliable connection service, unreliable datagram service, and raw datagram service.
  • the queue pair attributes management module 66 manages the transport services by updating the queue pair attributes database 64 during communication between the local and remote communication agents, for example when packet sequence numbers increase as messages are exchanged between the local and remote communication agents.
  • the queue pair attributes management module 66 also includes service submodules 68 , each configured for managing a corresponding transport service type based on a corresponding received WQE from the pre-link module 40 .
  • the bypass service submodule 68 a is configured for managing bypass services during connection establishment or managing queue pairs associated with management operations with network managers that use, for example, the raw datagram service.
  • the CPU aided service submodule 68 b is configured for managing queue pairs based on embedded processor operations using the embedded virtual lane FIFO 52 a ; hence, the CPU aided service submodule 68 b enables coordination between the local and remote embedded processes; moreover, implementation of the CPU aided service submodule 68 b in conjunction with the embedded virtual lane FIFO 52 a enables messages to be retransmitted if a resend request is received from the remote communication agent.
  • the reliable connection (RC) service submodule 68 c and the unreliable connection (UC) service submodule 68 d are configured for managing queue pairs associated with reliable connection and unreliable connection transport services, respectively.
  • the queue pair attributes management module 66 also includes submodules 68 for managing reliable and unreliable datagram services, and raw datagram service.
  • the transport service module 42 upon receiving a WQE from the pre-link module 40 , supplies the WQE to the appropriate submodule 68 for processing (e.g., WQE for RC service handled by the RC service submodule 68 c ).
  • the WQE includes service level (SL) information, and a pointer to the location of the actual message in the system memory 48 .
  • the submodule 68 in response to reception of the appropriate WQE, parses the WQE, and retrieves from the WQE the pointer that identifies the memory location for the transport data (i.e., the payload for the transport layer); the submodule 68 performs a DMA fetch of the transport data, updates the appropriate queue pair attributes within the queue pair attributes database 64 , and creates and stores in the external memory 48 a transport layer header for the WQE in a corresponding transport format; for example, the submodule 68 a may generate a raw transport header, whereas the modules 68 c or 68 d may generate a transport header according to the reliable connection service or the unreliable connection service, respectively.
  • the submodule 68 then creates a header pointer (p 1 ) that identifies the location of the transport layer header.
  • the submodule 68 then sends to the post-link module 44 the payload pointer (p 2 ) and the header pointer (p 1 ) as a packet request 71 enabling the post-link module 44 to assemble the transport packet for transmission based on the supplied pointers.
  • the submodule 68 may generate a frame pointer to a system memory location that stores the transport layer frame, including the transport layer header and the transport data. If preferred, the submodule 68 also could forward the transport layer frame (including transport layer header and transport data) to the post-link module.
  • the CPU may leave blank spaces at the beginning of the data, so that the actual header information that is created within the modules 68 can be stored in the corresponding empty memory space.
  • the pointer passed down to the post-link module 44 could be this pointer which points to the beginning of the frame in the external memory.
  • the post-link module 44 in response to reception of the transport layer information (e.g., transport layer frame, packet request, etc.), fetches the transport layer header and the transport layer payload from the system memory 48 for generation of the transmit packet and storage in a transmit FIFO 70 .
  • the post-link module 44 also includes a link layer control module 72 configured for generating the transmit packet by generating link layer fields (e.g., local and global routing headers, cyclic redundancy check (CRC) fields, etc.), storage of the transmit packet in the transmit FIFO 70 , and handling link layer control operations according to the InfiniBandTM Architecture Specification.
  • link layer fields e.g., local and global routing headers, cyclic redundancy check (CRC) fields, etc.
  • the link layer control module 72 outputs the transmit packets according to a credit-based flow control.
  • the link layer control module 72 monitors the available credits for transmission of a transmit packet on the assignment virtual lane.
  • credits are sent on a per virtual lane basis, where a receiver issues a credit based on packets taken from an incoming virtual lane buffer; the credits are sent to the sender, enabling the sender to manage flow control.
  • the link layer control module 72 determines that an identified virtual lane has an insufficient number of credits, the link layer control module 72 defers transmission of the corresponding transmit packet until a sufficient number of credits have been received. If the virtual lane has a sufficient number of credits, the link layer control module 72 forwards the transmit packet to the MAC module 46 for transmission.
  • the MAC module 46 is configured for outputting the transmit packet stored in the transmit FIFO 70 according to the InfiniBandTM Architecture Specification.
  • the MAC module 46 includes a transmission module 74 , a free buffer manager 76 , an embedded processor input queue 78 , and an embedded processor 80 having a link flow control packet construction module 82 .
  • the transmission module 74 is configured for performing media access control operations, and optionally physical layer transceiver operations, for transmission of the transmit packet onto the InfiniBandTM network 10 .
  • the free buffer manager 76 is configured for releasing available space from the external memory 48 once the transmit packet has been successfully received by the responder.
  • the memory pointers for a transmit packet are sent from the post-link module 44 once the transmit packet has been generated; if a responder sends a message that the transmit packet needs to be resent in a reliable connection service, the transmit packet can be regenerated by the post-link module 44 and retransmitted to the responder. Once the transmit packet is successfully received, the frame pointers can be released for use by another agent.
  • Flow control is handled by the embedded processor 80 based on reception of information from the embedded processor input queue 78 : in particular, the flow control protocol according to the InfiniBandTM Architecture Specification uses a credit-based flow control.
  • the embedded processor 80 generates link flow control packets using the link flow control packet construction module 82 , based on messages stored into the embedded processor input queue 78 .
  • the embedded processor 80 writes the link flow control packet to external memory 48 ; the embedded processor 80 then generates a WQE that includes the associated operation and a pointer specifying the location of a flow control packet into the embedded processor virtual lane FIFO 52 a .
  • the link flow control packet can then be output, specifying a number of available credits for another transmitting note.
  • the embedded processor 80 can generate a link flow control frame including the flow control header, and output the link flow control frame to the error processor input queue 78 for transmission to the network.
  • an Ethernet frame 84 includes a VLAN tag 86 which indicates layer 2 priorities according to IEEE 802.1P.
  • the VLAN tag 86 is read and mapped to a corresponding queue.
  • all nodes in the network will recognize the VLAN tag 86 and give the packet a corresponding priority.
  • there is no layer 2 priority mapping support in the InfiniBandTM network and the packet is simply sent by a router as a raw datagram. Thus, the layer 2 priorities of the packet are not retained.
  • router 20 includes an HCA 90 having an VLAN tag to service to service layer (VLANTag_SL) mapping table 92 .
  • Application software resides on router 20 for generating the VLANTag_SL mapping table 92 .
  • the VLANTag_SL mapping table 92 bridges the Ethernet domain 93 with the InfiniBandTM domain 95 .
  • the router 20 includes an Ethernet interface 97 for connection with the Ethernet domain 93 .
  • An Ethernet to InfiniBandTM controller 99 is provided in the router 20 .
  • the controller 99 is configured for parsing the VLAN tag 86 and for determining the service level for the VLAN tag 86 .
  • the controller 99 outputs an Ethernet data packet on InfiniBandTM network within an InfiniBandTM packet according to the determined service level.
  • the HCA 90 is configured for generating the InfiniBandTM packet 102 based on a request from the controller 99 .
  • the HCA 90 includes an SL-VL mapping table 101 configured for assigning the InfiniBandTM packet to a prescribed virtual lane based on the determined service level specified in the request.
  • an InfiniBandTM packet 102 is established which includes a virtual lane (VL) field 96 containing packet application level priority, with VL15 being highest priority and VL0 being lowest priority.
  • VL virtual lane
  • the VLANTag_SL mapping table can be populated by a network processor or packet processor together with content addressable memory containing VLAN tags 86 and corresponding SL numbers. Alternatively, populating the VLANTag_SL mapping table can be done by management software.

Abstract

A router is configured for sending and receiving data packets on an InfiniBand™ network. When placed between an Ethernet network and an InfiniBand™ network, the router is configured to receive an Ethernet data packet having a VLAN tag indicative of layer 2 priority data of the Ethernet packet. The router includes a mapping table having multiple entries, each entry specifying a VLAN tag and a corresponding service level. A controller is configured for parsing the VLAN tag and determining the service level for the VLAN tag. The controller outputs the Ethernet packet on the InfiniBand™ network within an InfiniBand™ packet according to the determined service level.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an InfiniBand™ router configured for sending and receiving data packets in an InfiniBand™ network and, more particularly, to a router which maps Ethernet (IEEE 802.1P) LAN priorities to a virtual lane of an InfiniBand™ network
2. Background Art
Networking technology has encountered improvements in server architectures and design with a goal toward providing servers that are more robust and reliable in mission critical networking applications. In particular, the use of servers for responding to client requests has resulted in a necessity that servers have an extremely high reliability to ensure that the network remains operable. Hence, there has been a substantial concern about server reliability, accessibility, and serviceability.
In addition, processors used in servers have encountered substantial improvements, where the microprocessor speed and bandwidth have exceeded the capacity of the connected input/out (I/O) buses, limiting the server throughput to the bus capacity. Accordingly, different server standards have been proposed in an attempt to improve server performance in terms of addressing, processor clustering, and high-speed I/O.
These different proposed server standards led to the development of the InfiniBand™ Architecture Specification, (Release 1.0), adopted by the InfiniBand™ Trade Association. The InfiniBand™ Architecture Specification specifies a high-speed networking connection between central processing units, peripherals, and switches inside a server system. Hence, the term “InfiniBand™ network” refers to a network within a server system. The InfiniBand™ Architecture Specification specifies both I/O operations and interprocessor communications (IPC).
A particular feature of InfiniBand™ Architecture Specification is the proposed implementation in hardware of the transport layer services present in existing networking protocols, such as TCP/IP based protocols. The hardware-based implementation of transport layer services provides the advantage of reducing processing requirements of the central processing unit (i.e., “offloading”), hence offloading the operating system of the server system.
The InfiniBand™ Architecture Specification describes a network architecture, illustrated in FIG. 1. The network 10 includes nodes 11, each having an associated channel adapter 12 or 14. For example, the computing node 11 a includes processors 16 and a host channel adapter (HCA) 12; the destination target nodes 11 b and 11 c include target channel adapters 14 a and 14 b, and target devices (e.g., peripherals such as Ethernet bridges or storage devices) 18 a and 18 b, respectively. The network 10 also includes routers 20, and InfiniBand™ switches 22.
Channel adapters operate as interface devices for respective server subsystems (i.e., nodes). For example, host channel adapters (HCAs) 12 are used to provide the computing node 11 a with an interface connection to the InfiniBand™ network 10, and target channel adapters (TCAs) 14 are used to provide the destination target nodes 11 b and 11 c with an interface connection to the InfiniBand™ network. Host channel adapters 12 may be connected to a memory controller 24 as illustrated in FIG. 1. Host channel adapters 12 implement the transport layer using a virtual interface referred to as the “verbs” layer that defines in the manner in which the processor 16 and the operating system communicate with the associated HCA 12: verbs are data structures (e.g., commands) used by application software to communicate with the HCA. Target channel adapters 14, however, lack the verbs layer, and hence communicate with their respective devices 18 according to the respective device protocol (e.g., PCI, SCSI, etc.).
Presently, when an Ethernet frame containing layer 2 priorities is received at an InfiniBand™ network, there is no mapping support in the InfiniBand™ network for layer 2 layer priorities and the packet is simply sent by a router as a raw datagram. Thus, the application layer priorities of the packet are not retained.
SUMMARY OF THE INVENTION
When a Ethernet frame, having layer 2 priorities identified in a VLAN tag, is received at an InfiniBand™ network, there is a need to map the VLAN tag to a service level in the InfiniBand™ network.
These and other needs are attained by the present invention, where a router is configured for sending and receiving data packets onto an InfiniBand™ network. The router is configured to receive an Ethernet data packet having a VLAN tag indicative of layer 2 priority data of the Ethernet packet. The router includes a mapping table having multiple entries, each entry specifying a VLAN tag and a corresponding service level. A controller is configured for parsing the VLAN tag and determining the service level for the VLAN tag. The controller outputs the Ethernet packet on the InfiniBand™ network within an InfiniBand™ packet according to the determined service level.
Another aspect of the present invention provides a method of outputting an Ethernet packet, received by a router, onto an InfiniBand™ network. The method includes receiving, by the router, an Ethernet data packet having a VLAN tag. The VLAN tag is parsed and mapped to a determined service level based on the parsed VLAN tag. The Ethernet packet is outputted on the InfiniBand™ network within an InfiniBand™ packet according to the determined service level.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
Reference is made to the attached drawings, wherein elements having the same reference numeral designations represent like elements throughout and wherein:
FIG. 1 is a diagram illustrating a conventional network according to the InfiniBand™ Architecture Specification.
FIG. 2 is a diagram illustrating in detail a host channel adapter of an InfiniBand™ network according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating the mapping layer 2 priorities in an VLAN tag of an Ethernet frame to a virtual lane in an InfiniBand™ packet.
FIG. 4 is a diagram illustrating a router having a VLAN tag to service level mapping table for bridging between the Ethernet domain and the InfiniBand™ domain.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 2 is a block diagram illustrating a host channel adapter (HCA) 12 configured for generating and transmitting packets according to an embodiment of the present invention. The HCA 12, compliant with the InfiniBand™ Architecture Specification, is implemented in a manner that ensures that hardware resources are efficiently utilized by generating transmit packets according to a priority-based ordering. In addition, the disclosed HCA 12 provides flexibility by enabling embedded processes to be added without disruption of traffic flow. Hence, the HCA 12 can be implemented in an economical manner with minimal complexity relative to conventional implementation techniques.
One problem with conventional arrangements for implementing the HCA 12 according to the InfiniBand™ Architecture Specification is that transport layer service would be performed first, for example by constructing a transport layer header, generating a packet sequence number, validating the service type (e.g., reliable connection, reliable datagram, unreliable connection, unreliable datagram, etc.), and other transport layer operations. Once the transport layer operations have been completed, the packet would be sent to the link layer service for link layer operations, including service layer and virtual lane mapping, link layer flow control packet generation, link layer transmission credit checking, and other operations. Although this conventional type of implementation has the advantage of precisely following the network layers specified in the InfiniBand™ Architecture Specification, such an arrangement requires a substantially large amount of hardware. In particular, the transport layer generally requires more processing power than the link layer because the transport layer involves more complex operations. Hence, there is a need that the implementation of the transport layer in hardware does not result in a substantially complex hardware system. In addition, there is a concern with unnecessarily wasting transport layer resources on low priority operations.
According to the disclosed embodiment, link layer operations are partitioned based on the desirability to determine priorities of data packets to be transmitted. In particular, the HCA 12 includes a pre-link module configured for determining a priority of received WQEs, and a post-link module configured for preparing a data packet for transmission on the network. The pre-link module 40 orders the WQEs according to priorities determined by the pre-link module, and outputs the WQEs in the determined order to a transport service module 42 configured for generating the appropriate transport layer headers for the WQEs based on the associated queue pair attributes. In other words, the pre-link module 40 prevents the transport service module 42 from wasting resources on low priority WQEs or blocking high priority WQE's within the transport layer process. Hence, higher priority connections obtain improved service at the transport layer through the HCA.
The HCA 12, implemented for example as an application-specific integrated circuit, includes a pre-link module 40, a transport service module 42, a post-link module 44, and a media access control (MAC) module 46. The HCA 12 also has local access to a memory 48 configured for storing transport data and overflow buffers, described below.
The pre-link module 40 includes a work queue element FIFO 50, virtual lane FIFOs 52, a pre-link process module 54, a service layer to virtual lane (SL-VL) mapping table 56, a virtual lane (VL) arbitration table 58, and a virtual lane (VL) arbitration module 60.
The HCA 12 is configured for receiving data from a central processing unit (CPU) in the form of work queue elements (WQEs), stored in the WQE FIFO 50. Each WQE specifies a corresponding request, from a consumer application executed by the CPU (i.e., “requester”), for a corresponding prescribed operation to be performed by a destination InfiniBand™ network node (i.e., “responder”), for example a target. The interaction between requester and responder is specified via a queue pair (QP), where a queue pair includes a send work queue and a receive work queue.
The WQE includes service level (SL) information, and a pointer to the location of the actual message in the system memory 48. The InfiniBand™ Architecture Specification defines a service level (SL) attribute that permits a packet traversing the InfiniBand™ network 10 to operate at one of sixteen available service levels. Hence, the requester can select an available service level (e.g., quality of service, priority, etc.) based on a selected priority of the WQE.
The pre-link module 40 provides both service level to virtual lane mapping (SL-VL mapping), and virtual lane arbitration. In particular, virtual lanes, defined in the InfiniBand™ Architecture Specification, enable multiple logical flows to be implemented over a single physical link, where link level flow control can be applied to one virtual lane without affecting other virtual lanes. The pre-link process module 54 is configured for managing and maintaining the service layer-virtual layer mapping table 56. In particular, the pre-link process module 54 retrieves a WQE from the WQE FIFO 50, and determines the corresponding virtual lane based on the service layer specified within the WQE. Upon identifying the appropriate virtual lane for the retrieved WQE, the pre-link process module 54 forwards the WQE to the corresponding virtual lane FIFO 52.
The pre-link module 40 includes virtual lane FIFOs 52 a, 52 b, 52 c, 52 d, 52 e, and 52 f for storage of WQEs based on the assignment by the pre-link process module 54. For example, the virtual lane FIFO 52 a is used for storing WQEs associated with embedded processor operations, for example link layer control packets and handling of error conditions. In other words, when a prescribed operation is not implemented in hardware, the request is sent to an embedded processor queue 78 for further processing by an embedded processor 80, described below; hence the embedded processor 80 has its own assigned queue 52 a for outputting packets into the flow of output data traffic. The virtual lane FIFO 52 b is used for storing WQEs associated with management traffic. The virtual lane FIFOs 52 c, 52 d, 52 e, and 52 f are used for storing WQEs associated with respective assigned virtual lanes. Although the disclosed embodiment discloses the use of four assigned virtual lanes, additional virtual lane FIFOs may be added for additional assigned virtual lanes.
The VL arbitration module 60 is implemented as a state machine with registers, and is configured for managing the VL arbitration table 58 for servicing of the virtual lanes, including setup, management, and teardown of the virtual lanes. The VL arbitration module 60 also determines which virtual lane to service, and outputs the WQEs from the virtual lane FIFOs 52 based on the determined priority of the virtual lanes. For example, the virtual lane FIFO 52 b typically stores management (high-priority) traffic, hence the VL arbitration module 60 typically would empty the virtual lane FIFO 52 b before servicing the other virtual lane FIFOs 52 c, 52 d, 52 e, or 52 f. The VL arbitration module 60 would then selectively output the WQEs from the virtual lane FIFOs 52 c, 52 d, 52 e, or 52 f based on weighted priorities stored in respective weight tables within the VL arbitration table 58.
Hence, the pre-ink module 40 outputs the WQEs in a prescribed order based on a determined priority of the WQEs, for example based on assigned virtual lanes, or whether the WQE is for an embedded process, management traffic, or flow control traffic.
The transport service module 42 is configured for managing transport services, including setup, management, and teardown of queue pairs. In particular, the HCA 12 includes a queue pair setup FIFO 62 configured for storing queue pair commands received from a communication management agent. The communication management agent is responsible for setup and teardown of transport connections: the communication management agent communicates with a subnet manager to establish the transport connections (i.e., queue pairs) for the HCA 12. In addition, the communication management agents at each end during connection establishment use a bypass service (described below with respect to bypass service submodule 68 a), as opposed to a conventional transport layer service, to establish the transport connections.
The transport service module 42 includes a queue pair attributes database 64 and a queue pair attributes management module 66. The queue pair attributes management module 66 is configured for processing the queue pair commands in the queue pair setup FIFO 62, and updating the queue pair attributes database 64 based on the received queue pair commands. For example, the queue pair attributes database 64 stores information relating to a source queue pair number, a destination queue pair number, and possibly source agent and destination agent. Hence, the queue pair attributes database 64 will include all information necessary to support the different transport services, including reliable connection service, reliable datagram service, unreliable connection service, unreliable datagram service, and raw datagram service.
The queue pair attributes management module 66 manages the transport services by updating the queue pair attributes database 64 during communication between the local and remote communication agents, for example when packet sequence numbers increase as messages are exchanged between the local and remote communication agents.
The queue pair attributes management module 66 also includes service submodules 68, each configured for managing a corresponding transport service type based on a corresponding received WQE from the pre-link module 40. For example, the bypass service submodule 68 a is configured for managing bypass services during connection establishment or managing queue pairs associated with management operations with network managers that use, for example, the raw datagram service. The CPU aided service submodule 68 b is configured for managing queue pairs based on embedded processor operations using the embedded virtual lane FIFO 52 a; hence, the CPU aided service submodule 68 b enables coordination between the local and remote embedded processes; moreover, implementation of the CPU aided service submodule 68 b in conjunction with the embedded virtual lane FIFO 52 a enables messages to be retransmitted if a resend request is received from the remote communication agent. The reliable connection (RC) service submodule 68 c and the unreliable connection (UC) service submodule 68 d are configured for managing queue pairs associated with reliable connection and unreliable connection transport services, respectively. Although not shown, the queue pair attributes management module 66 also includes submodules 68 for managing reliable and unreliable datagram services, and raw datagram service.
Hence, the transport service module 42, upon receiving a WQE from the pre-link module 40, supplies the WQE to the appropriate submodule 68 for processing (e.g., WQE for RC service handled by the RC service submodule 68 c). The WQE includes service level (SL) information, and a pointer to the location of the actual message in the system memory 48. The submodule 68, in response to reception of the appropriate WQE, parses the WQE, and retrieves from the WQE the pointer that identifies the memory location for the transport data (i.e., the payload for the transport layer); the submodule 68 performs a DMA fetch of the transport data, updates the appropriate queue pair attributes within the queue pair attributes database 64, and creates and stores in the external memory 48 a transport layer header for the WQE in a corresponding transport format; for example, the submodule 68 a may generate a raw transport header, whereas the modules 68 c or 68 d may generate a transport header according to the reliable connection service or the unreliable connection service, respectively.
The submodule 68 then creates a header pointer (p1) that identifies the location of the transport layer header. The submodule 68 then sends to the post-link module 44 the payload pointer (p2) and the header pointer (p1) as a packet request 71 enabling the post-link module 44 to assemble the transport packet for transmission based on the supplied pointers. Alternately, the submodule 68 may generate a frame pointer to a system memory location that stores the transport layer frame, including the transport layer header and the transport data. If preferred, the submodule 68 also could forward the transport layer frame (including transport layer header and transport data) to the post-link module. Alternately, while writing to the external memory, the CPU may leave blank spaces at the beginning of the data, so that the actual header information that is created within the modules 68 can be stored in the corresponding empty memory space. The pointer passed down to the post-link module 44 could be this pointer which points to the beginning of the frame in the external memory.
The post-link module 44, in response to reception of the transport layer information (e.g., transport layer frame, packet request, etc.), fetches the transport layer header and the transport layer payload from the system memory 48 for generation of the transmit packet and storage in a transmit FIFO 70. In particular, the post-link module 44 also includes a link layer control module 72 configured for generating the transmit packet by generating link layer fields (e.g., local and global routing headers, cyclic redundancy check (CRC) fields, etc.), storage of the transmit packet in the transmit FIFO 70, and handling link layer control operations according to the InfiniBand™ Architecture Specification. Once the transmit packet has been generated, the pointers are forwarded to the free buffer manager 76, described below.
The link layer control module 72 outputs the transmit packets according to a credit-based flow control. In particular, the link layer control module 72 monitors the available credits for transmission of a transmit packet on the assignment virtual lane. In particular, credits are sent on a per virtual lane basis, where a receiver issues a credit based on packets taken from an incoming virtual lane buffer; the credits are sent to the sender, enabling the sender to manage flow control. Hence, if the link layer control module 72 determines that an identified virtual lane has an insufficient number of credits, the link layer control module 72 defers transmission of the corresponding transmit packet until a sufficient number of credits have been received. If the virtual lane has a sufficient number of credits, the link layer control module 72 forwards the transmit packet to the MAC module 46 for transmission.
The MAC module 46 is configured for outputting the transmit packet stored in the transmit FIFO 70 according to the InfiniBand™ Architecture Specification. In particular, the MAC module 46 includes a transmission module 74, a free buffer manager 76, an embedded processor input queue 78, and an embedded processor 80 having a link flow control packet construction module 82. The transmission module 74 is configured for performing media access control operations, and optionally physical layer transceiver operations, for transmission of the transmit packet onto the InfiniBand™ network 10.
The free buffer manager 76 is configured for releasing available space from the external memory 48 once the transmit packet has been successfully received by the responder. In particular, the memory pointers for a transmit packet are sent from the post-link module 44 once the transmit packet has been generated; if a responder sends a message that the transmit packet needs to be resent in a reliable connection service, the transmit packet can be regenerated by the post-link module 44 and retransmitted to the responder. Once the transmit packet is successfully received, the frame pointers can be released for use by another agent.
Flow control is handled by the embedded processor 80 based on reception of information from the embedded processor input queue 78: in particular, the flow control protocol according to the InfiniBand™ Architecture Specification uses a credit-based flow control. The embedded processor 80 generates link flow control packets using the link flow control packet construction module 82, based on messages stored into the embedded processor input queue 78. The embedded processor 80 writes the link flow control packet to external memory 48; the embedded processor 80 then generates a WQE that includes the associated operation and a pointer specifying the location of a flow control packet into the embedded processor virtual lane FIFO 52 a. The link flow control packet can then be output, specifying a number of available credits for another transmitting note.
Hence, the embedded processor 80 can generate a link flow control frame including the flow control header, and output the link flow control frame to the error processor input queue 78 for transmission to the network.
With reference to FIG. 3, an Ethernet frame 84 includes a VLAN tag 86 which indicates layer 2 priorities according to IEEE 802.1P. When an Ethernet frame is received at a router, the VLAN tag 86 is read and mapped to a corresponding queue. Thus, when a packet is sent, from a node A to a node B, from end to end, all nodes in the network will recognize the VLAN tag 86 and give the packet a corresponding priority. Typically, when an Ethernet frame is sent to an InfiniBand™ network, there is no layer 2 priority mapping support in the InfiniBand™ network and the packet is simply sent by a router as a raw datagram. Thus, the layer 2 priorities of the packet are not retained.
According to the disclosed embodiment, support is provided in the InfiniBand™ network to recognize the layer 2 priorities identified in a VLAN tag of an Ethernet frame and to map the VLAN tag to a service level in the InfiniBand™ network. With reference to FIGS. 2 and 3, router 20 includes an HCA 90 having an VLAN tag to service to service layer (VLANTag_SL) mapping table 92. Application software resides on router 20 for generating the VLANTag_SL mapping table 92. Thus, the VLANTag_SL mapping table 92 bridges the Ethernet domain 93 with the InfiniBand™ domain 95. The router 20 includes an Ethernet interface 97 for connection with the Ethernet domain 93. An Ethernet to InfiniBand™ controller 99 is provided in the router 20. The controller 99 is configured for parsing the VLAN tag 86 and for determining the service level for the VLAN tag 86. The controller 99 outputs an Ethernet data packet on InfiniBand™ network within an InfiniBand™ packet according to the determined service level. In particular, the HCA 90 is configured for generating the InfiniBand™ packet 102 based on a request from the controller 99. With reference to FIG. 4, the HCA 90 includes an SL-VL mapping table 101 configured for assigning the InfiniBand™ packet to a prescribed virtual lane based on the determined service level specified in the request. As shown in FIG. 3, an InfiniBand™ packet 102 is established which includes a virtual lane (VL) field 96 containing packet application level priority, with VL15 being highest priority and VL0 being lowest priority.
The VLANTag_SL mapping table can be populated by a network processor or packet processor together with content addressable memory containing VLAN tags 86 and corresponding SL numbers. Alternatively, populating the VLANTag_SL mapping table can be done by management software.
While this invention has been described with what is presently considered to be the most practical preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (11)

1. A router configured for sending and receiving data packets on an InfiniBand™ network, the router being configured to receive an Ethernet data packet having a VLAN tag indicative of layer 2 priority data of the Ethernet packet, the router comprising:
a mapping table having multiple entries, each entry specifying a VLAN tag and a corresponding service level, and
a controller configured for parsing the VLAN tag and determining the service level for the VLAN tag, the controller outputting the Ethernet packet on the InfiniBand™ network within an InfiniBand™ packet according to the determined service level.
2. The router of claim 1, further including a host channel adapter configured for generating the InfiniBand™ packet based on a request from the controller.
3. The router of claim 2, wherein the host channel adapter includes a service level to virtual lane mapping table configured for assigning the InfiniBand™ packet to a prescribed virtual lane based on the determined service level specified in the request.
4. A method of outputting an Ethernet packet, received by a router, onto an InfiniBand™ network, the method comprising:
receiving, by the router, an Ethernet data packet having a VLAN tag;
parsing the VLAN tag and mapping the VLAN tag to a determined service level based on the parsed VLAN tag; and
outputting the Ethernet packet on the InfiniBand™ network within an InfiniBand™ packet according to the determined service level.
5. The method of claim 4, further including, prior to outputting step, the step of mapping the service level to a virtual lane and establishing an InfiniBand™ packet header including a virtual lane field that contains priority data relating to the priority data of the Ethernet packet.
6. The method of claim 4, wherein, prior to the parsing step, the method includes populating within the router a VLAN tag to service level mapping table with VLAN tag values and corresponding service level numbers.
7. A router configured for sending and receiving data packets on an InfiniBand™ network, the router being configured to receive an Ethernet data packet having a VLAN tag indicative of a layer 2 priority data of the Ethernet packet, the router comprising:
means for a mapping a VLAN tag to a corresponding service level, and
means for parsing the VLAN tag and determining the service level for the VLAN tag, and for outputting the Ethernet packet on the InfiniBand™ network within an InfiniBand™ packet according to the determined service level.
8. The router of claim 7, wherein the means for mapping is a mapping table having multiple entries, each entry specifying a VLAN tag value and a corresponding service level.
9. The router of claim 7, wherein the means for parsing is a controller.
10. The router of claim 9, further including a host channel adapter configured for generating the InfiniBand™ packet based on a request from the controller.
11. The router of claim 10, wherein the host channel adapter includes a service level to virtual lane mapping table configured for assigning the InfiniBand™ packet to a prescribed virtual lane based on the determined service level specified in the request.
US09/881,771 2001-06-18 2001-06-18 Mapping layer 2 LAN priorities to a virtual lane in an Infiniband™ network Expired - Lifetime US6999462B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/881,771 US6999462B1 (en) 2001-06-18 2001-06-18 Mapping layer 2 LAN priorities to a virtual lane in an Infiniband™ network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/881,771 US6999462B1 (en) 2001-06-18 2001-06-18 Mapping layer 2 LAN priorities to a virtual lane in an Infiniband™ network

Publications (1)

Publication Number Publication Date
US6999462B1 true US6999462B1 (en) 2006-02-14

Family

ID=35767996

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/881,771 Expired - Lifetime US6999462B1 (en) 2001-06-18 2001-06-18 Mapping layer 2 LAN priorities to a virtual lane in an Infiniband™ network

Country Status (1)

Country Link
US (1) US6999462B1 (en)

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030193942A1 (en) * 2002-04-10 2003-10-16 Gil Mercedes E. Method and apparatus for fast integer within-range compare
US20040013088A1 (en) * 2002-07-19 2004-01-22 International Business Machines Corporation Long distance repeater for digital information
US20050100033A1 (en) * 2003-11-06 2005-05-12 International Business Machines Corporation Infiniband general services queue pair virtualization for multiple logical ports on a single physical port
US20050226242A1 (en) * 2004-03-30 2005-10-13 Parker David K Pipelined packet processor
US20060087989A1 (en) * 2004-10-22 2006-04-27 Cisco Technology, Inc., A Corporation Of California Network device architecture for consolidating input/output and reducing latency
US20060098681A1 (en) * 2004-10-22 2006-05-11 Cisco Technology, Inc. Fibre channel over Ethernet
US20060101140A1 (en) * 2004-10-22 2006-05-11 Cisco Technology, Inc. Ethernet extension for the data center
US20060098589A1 (en) * 2004-10-22 2006-05-11 Cisco Technology, Inc. Forwarding table reduction and multipath network forwarding
US20060251067A1 (en) * 2004-10-22 2006-11-09 Cisco Technology, Inc., A Corporation Of California Fibre channel over ethernet
US20070081454A1 (en) * 2005-10-11 2007-04-12 Cisco Technology, Inc. A Corporation Of California Methods and devices for backward congestion notification
US20070153808A1 (en) * 2005-12-30 2007-07-05 Parker David K Method of providing virtual router functionality
US20080186968A1 (en) * 2007-02-02 2008-08-07 Cisco Technology, Inc. Triple-tier anycast addressing
US20090052326A1 (en) * 2007-08-21 2009-02-26 Cisco Technology, Inc., A Corporation Of California Backward congestion notification
US20090059957A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Layer-4 transparent secure transport protocol for end-to-end application protection
US20090201959A1 (en) * 2008-02-07 2009-08-13 Board Of Regents, The University Of Texas System Wavelength and Intensity Monitoring of Optical Cavity
US20090288135A1 (en) * 2008-05-19 2009-11-19 Rohati Systems, Inc. Method and apparatus for building and managing policies
US20090285228A1 (en) * 2008-05-19 2009-11-19 Rohati Systems, Inc. Multi-stage multi-core processing of network packets
US20090288136A1 (en) * 2008-05-19 2009-11-19 Rohati Systems, Inc. Highly parallel evaluation of xacml policies
US20090288104A1 (en) * 2008-05-19 2009-11-19 Rohati Systems, Inc. Extensibility framework of a network element
US20100070471A1 (en) * 2008-09-17 2010-03-18 Rohati Systems, Inc. Transactional application events
US7817633B1 (en) 2005-12-30 2010-10-19 Extreme Networks, Inc. Method of providing virtual router functionality through abstracted virtual identifiers
US7822033B1 (en) 2005-12-30 2010-10-26 Extreme Networks, Inc. MAC address detection device for virtual routers
US20100302940A1 (en) * 2009-05-28 2010-12-02 Microsoft Corporation Load balancing across layer-2 domains
US7889750B1 (en) 2004-04-28 2011-02-15 Extreme Networks, Inc. Method of extending default fixed number of processing cycles in pipelined packet processor architecture
US8149710B2 (en) 2007-07-05 2012-04-03 Cisco Technology, Inc. Flexible and hierarchical dynamic buffer allocation
US8605732B2 (en) 2011-02-15 2013-12-10 Extreme Networks, Inc. Method of providing virtual router functionality
US8902743B2 (en) 2010-06-28 2014-12-02 Microsoft Corporation Distributed and scalable network address translation
US9391716B2 (en) 2010-04-05 2016-07-12 Microsoft Technology Licensing, Llc Data center using wireless communication
US9497039B2 (en) 2009-05-28 2016-11-15 Microsoft Technology Licensing, Llc Agile data center network architecture
US9602355B2 (en) 2013-07-31 2017-03-21 Cisco Technology, Inc. Network interface with adjustable rate
US9954751B2 (en) 2015-05-29 2018-04-24 Microsoft Technology Licensing, Llc Measuring performance of a network using mirrored probe packets

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619500A (en) * 1994-09-01 1997-04-08 Digital Link Corporation ATM network interface
US6438128B1 (en) * 2001-05-08 2002-08-20 International Business Machines Corporation Alternate use of data packet fields to convey information
US6459698B1 (en) * 2001-06-18 2002-10-01 Advanced Micro Devices, Inc. Supporting mapping of layer 3 priorities in an infiniband ™ network
US20020141424A1 (en) * 2001-03-28 2002-10-03 Gasbarro Dominic J. Host-fabric adapter having work queue entry (WQE) ring hardware assist (HWA) mechanism
US20020172195A1 (en) * 2001-03-23 2002-11-21 Pekkala Richard E. Apparatus amd method for disparate fabric data and transaction buffering within infiniband device
US20020184368A1 (en) * 2001-04-06 2002-12-05 Yunsen Wang Network system, method and protocols for hierarchical service and content distribution via directory enabled network
US20030014544A1 (en) * 2001-02-15 2003-01-16 Banderacom Infiniband TM work queue to TCP/IP translation
US6594712B1 (en) * 2000-10-20 2003-07-15 Banderacom, Inc. Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619500A (en) * 1994-09-01 1997-04-08 Digital Link Corporation ATM network interface
US6594712B1 (en) * 2000-10-20 2003-07-15 Banderacom, Inc. Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link
US20030014544A1 (en) * 2001-02-15 2003-01-16 Banderacom Infiniband TM work queue to TCP/IP translation
US20020172195A1 (en) * 2001-03-23 2002-11-21 Pekkala Richard E. Apparatus amd method for disparate fabric data and transaction buffering within infiniband device
US20020141424A1 (en) * 2001-03-28 2002-10-03 Gasbarro Dominic J. Host-fabric adapter having work queue entry (WQE) ring hardware assist (HWA) mechanism
US20020184368A1 (en) * 2001-04-06 2002-12-05 Yunsen Wang Network system, method and protocols for hierarchical service and content distribution via directory enabled network
US6438128B1 (en) * 2001-05-08 2002-08-20 International Business Machines Corporation Alternate use of data packet fields to convey information
US6459698B1 (en) * 2001-06-18 2002-10-01 Advanced Micro Devices, Inc. Supporting mapping of layer 3 priorities in an infiniband ™ network

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Daniel Cassiday, InfiniBand(TM) Architecture Tutorial, Hot Chips, Aug. 2000, Sun Microsystems, 79 pages.

Cited By (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7191259B2 (en) * 2002-04-10 2007-03-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and apparatus for fast integer within-range compare
US20030193942A1 (en) * 2002-04-10 2003-10-16 Gil Mercedes E. Method and apparatus for fast integer within-range compare
US20040013088A1 (en) * 2002-07-19 2004-01-22 International Business Machines Corporation Long distance repeater for digital information
US7233570B2 (en) * 2002-07-19 2007-06-19 International Business Machines Corporation Long distance repeater for digital information
US20050100033A1 (en) * 2003-11-06 2005-05-12 International Business Machines Corporation Infiniband general services queue pair virtualization for multiple logical ports on a single physical port
US7555002B2 (en) * 2003-11-06 2009-06-30 International Business Machines Corporation Infiniband general services queue pair virtualization for multiple logical ports on a single physical port
US20050226242A1 (en) * 2004-03-30 2005-10-13 Parker David K Pipelined packet processor
US7649879B2 (en) 2004-03-30 2010-01-19 Extreme Networks, Inc. Pipelined packet processor
US7889750B1 (en) 2004-04-28 2011-02-15 Extreme Networks, Inc. Method of extending default fixed number of processing cycles in pipelined packet processor architecture
US20060251067A1 (en) * 2004-10-22 2006-11-09 Cisco Technology, Inc., A Corporation Of California Fibre channel over ethernet
US20060101140A1 (en) * 2004-10-22 2006-05-11 Cisco Technology, Inc. Ethernet extension for the data center
US20060087989A1 (en) * 2004-10-22 2006-04-27 Cisco Technology, Inc., A Corporation Of California Network device architecture for consolidating input/output and reducing latency
US7969971B2 (en) * 2004-10-22 2011-06-28 Cisco Technology, Inc. Ethernet extension for the data center
US20110007741A1 (en) * 2004-10-22 2011-01-13 Cisco Technology, Inc. Forwarding table reduction and multipath network forwarding
US7801125B2 (en) 2004-10-22 2010-09-21 Cisco Technology, Inc. Forwarding table reduction and multipath network forwarding
US9246834B2 (en) 2004-10-22 2016-01-26 Cisco Technology, Inc. Fibre channel over ethernet
US8842694B2 (en) 2004-10-22 2014-09-23 Cisco Technology, Inc. Fibre Channel over Ethernet
US7830793B2 (en) 2004-10-22 2010-11-09 Cisco Technology, Inc. Network device architecture for consolidating input/output and reducing latency
US8160094B2 (en) 2004-10-22 2012-04-17 Cisco Technology, Inc. Fibre channel over ethernet
US20060098589A1 (en) * 2004-10-22 2006-05-11 Cisco Technology, Inc. Forwarding table reduction and multipath network forwarding
US20090252038A1 (en) * 2004-10-22 2009-10-08 Cisco Technology, Inc. Fibre channel over ethernet
US8565231B2 (en) 2004-10-22 2013-10-22 Cisco Technology, Inc. Ethernet extension for the data center
US8532099B2 (en) 2004-10-22 2013-09-10 Cisco Technology, Inc. Forwarding table reduction and multipath network forwarding
US8238347B2 (en) 2004-10-22 2012-08-07 Cisco Technology, Inc. Fibre channel over ethernet
US20060098681A1 (en) * 2004-10-22 2006-05-11 Cisco Technology, Inc. Fibre channel over Ethernet
US7564869B2 (en) 2004-10-22 2009-07-21 Cisco Technology, Inc. Fibre channel over ethernet
US20070081454A1 (en) * 2005-10-11 2007-04-12 Cisco Technology, Inc. A Corporation Of California Methods and devices for backward congestion notification
US8792352B2 (en) 2005-10-11 2014-07-29 Cisco Technology, Inc. Methods and devices for backward congestion notification
US7961621B2 (en) 2005-10-11 2011-06-14 Cisco Technology, Inc. Methods and devices for backward congestion notification
US7822033B1 (en) 2005-12-30 2010-10-26 Extreme Networks, Inc. MAC address detection device for virtual routers
US7817633B1 (en) 2005-12-30 2010-10-19 Extreme Networks, Inc. Method of providing virtual router functionality through abstracted virtual identifiers
US7894451B2 (en) * 2005-12-30 2011-02-22 Extreme Networks, Inc. Method of providing virtual router functionality
US20070153808A1 (en) * 2005-12-30 2007-07-05 Parker David K Method of providing virtual router functionality
US8743738B2 (en) 2007-02-02 2014-06-03 Cisco Technology, Inc. Triple-tier anycast addressing
US8259720B2 (en) 2007-02-02 2012-09-04 Cisco Technology, Inc. Triple-tier anycast addressing
US20080186968A1 (en) * 2007-02-02 2008-08-07 Cisco Technology, Inc. Triple-tier anycast addressing
US8149710B2 (en) 2007-07-05 2012-04-03 Cisco Technology, Inc. Flexible and hierarchical dynamic buffer allocation
US8121038B2 (en) 2007-08-21 2012-02-21 Cisco Technology, Inc. Backward congestion notification
US8804529B2 (en) 2007-08-21 2014-08-12 Cisco Technology, Inc. Backward congestion notification
US20090052326A1 (en) * 2007-08-21 2009-02-26 Cisco Technology, Inc., A Corporation Of California Backward congestion notification
US20090063747A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Application network appliances with inter-module communications using a universal serial bus
US20090063625A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Highly scalable application layer service appliances
US9491201B2 (en) 2007-08-28 2016-11-08 Cisco Technology, Inc. Highly scalable architecture for application network appliances
US7913529B2 (en) 2007-08-28 2011-03-29 Cisco Technology, Inc. Centralized TCP termination with multi-service chaining
US7921686B2 (en) 2007-08-28 2011-04-12 Cisco Technology, Inc. Highly scalable architecture for application network appliances
US20090059957A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Layer-4 transparent secure transport protocol for end-to-end application protection
US9100371B2 (en) 2007-08-28 2015-08-04 Cisco Technology, Inc. Highly scalable architecture for application network appliances
US20110173441A1 (en) * 2007-08-28 2011-07-14 Cisco Technology, Inc. Highly scalable architecture for application network appliances
US7895463B2 (en) 2007-08-28 2011-02-22 Cisco Technology, Inc. Redundant application network appliances using a low latency lossless interconnect link
US20090063688A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Centralized tcp termination with multi-service chaining
US20090063701A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Layers 4-7 service gateway for converged datacenter fabric
US8161167B2 (en) 2007-08-28 2012-04-17 Cisco Technology, Inc. Highly scalable application layer service appliances
US20090064288A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Highly scalable application network appliances with virtualized services
US8180901B2 (en) 2007-08-28 2012-05-15 Cisco Technology, Inc. Layers 4-7 service gateway for converged datacenter fabric
US8621573B2 (en) 2007-08-28 2013-12-31 Cisco Technology, Inc. Highly scalable application network appliances with virtualized services
US20090064287A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Application protection architecture with triangulated authorization
US8295306B2 (en) 2007-08-28 2012-10-23 Cisco Technologies, Inc. Layer-4 transparent secure transport protocol for end-to-end application protection
US20090063665A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Highly scalable architecture for application network appliances
US8443069B2 (en) 2007-08-28 2013-05-14 Cisco Technology, Inc. Highly scalable architecture for application network appliances
US20090063893A1 (en) * 2007-08-28 2009-03-05 Rohati Systems, Inc. Redundant application network appliances using a low latency lossless interconnect link
US20090201959A1 (en) * 2008-02-07 2009-08-13 Board Of Regents, The University Of Texas System Wavelength and Intensity Monitoring of Optical Cavity
US8094560B2 (en) 2008-05-19 2012-01-10 Cisco Technology, Inc. Multi-stage multi-core processing of network packets
US20090288135A1 (en) * 2008-05-19 2009-11-19 Rohati Systems, Inc. Method and apparatus for building and managing policies
US8667556B2 (en) 2008-05-19 2014-03-04 Cisco Technology, Inc. Method and apparatus for building and managing policies
US8677453B2 (en) 2008-05-19 2014-03-18 Cisco Technology, Inc. Highly parallel evaluation of XACML policies
US20090288104A1 (en) * 2008-05-19 2009-11-19 Rohati Systems, Inc. Extensibility framework of a network element
US20090285228A1 (en) * 2008-05-19 2009-11-19 Rohati Systems, Inc. Multi-stage multi-core processing of network packets
US20090288136A1 (en) * 2008-05-19 2009-11-19 Rohati Systems, Inc. Highly parallel evaluation of xacml policies
US20100070471A1 (en) * 2008-09-17 2010-03-18 Rohati Systems, Inc. Transactional application events
US8416692B2 (en) 2009-05-28 2013-04-09 Microsoft Corporation Load balancing across layer-2 domains
US20100302940A1 (en) * 2009-05-28 2010-12-02 Microsoft Corporation Load balancing across layer-2 domains
US9497039B2 (en) 2009-05-28 2016-11-15 Microsoft Technology Licensing, Llc Agile data center network architecture
US9391716B2 (en) 2010-04-05 2016-07-12 Microsoft Technology Licensing, Llc Data center using wireless communication
US10110504B2 (en) 2010-04-05 2018-10-23 Microsoft Technology Licensing, Llc Computing units using directional wireless communication
US8902743B2 (en) 2010-06-28 2014-12-02 Microsoft Corporation Distributed and scalable network address translation
US8605732B2 (en) 2011-02-15 2013-12-10 Extreme Networks, Inc. Method of providing virtual router functionality
US9602355B2 (en) 2013-07-31 2017-03-21 Cisco Technology, Inc. Network interface with adjustable rate
US9954751B2 (en) 2015-05-29 2018-04-24 Microsoft Technology Licensing, Llc Measuring performance of a network using mirrored probe packets

Similar Documents

Publication Publication Date Title
US6459698B1 (en) Supporting mapping of layer 3 priorities in an infiniband ™ network
US6999462B1 (en) Mapping layer 2 LAN priorities to a virtual lane in an Infiniband™ network
US6480500B1 (en) Arrangement for creating multiple virtual queue pairs from a compressed queue pair based on shared attributes
US6912604B1 (en) Host channel adapter having partitioned link layer services for an infiniband server system
US7346707B1 (en) Arrangement in an infiniband channel adapter for sharing memory space for work queue entries using multiply-linked lists
US6973085B1 (en) Using application headers to determine InfiniBand™ priorities in an InfiniBand™ network
US7076569B1 (en) Embedded channel adapter having transport layer configured for prioritizing selection of work descriptors based on respective virtual lane priorities
US7996583B2 (en) Multiple context single logic virtual host channel adapter supporting multiple transport protocols
US7233570B2 (en) Long distance repeater for digital information
US7555002B2 (en) Infiniband general services queue pair virtualization for multiple logical ports on a single physical port
US5790530A (en) Message-passing multiprocessor system
US7865633B2 (en) Multiple context single logic virtual host channel adapter
US7133405B2 (en) IP datagram over multiple queue pairs
US7095750B2 (en) Apparatus and method for virtualizing a queue pair space to minimize time-wait impacts
US7283473B2 (en) Apparatus, system and method for providing multiple logical channel adapters within a single physical channel adapter in a system area network
US6957269B2 (en) Method and apparatus for performing priority-based flow control
US20050018669A1 (en) Infiniband subnet management queue pair emulation for multiple logical ports on a single physical port
US20070211741A1 (en) Receive Queue Descriptor Pool
US20080059686A1 (en) Multiple context single logic virtual host channel adapter supporting multiple transport protocols
US6816889B1 (en) Assignment of dual port memory banks for a CPU and a host channel adapter in an InfiniBand computing node
US20020198927A1 (en) Apparatus and method for routing internet protocol frames over a system area network
US6742075B1 (en) Arrangement for instigating work in a channel adapter based on received address information and stored context information
US7209489B1 (en) Arrangement in a channel adapter for servicing work notifications based on link layer virtual lane processing
JP2002305535A (en) Method and apparatus for providing a reliable protocol for transferring data
US6885673B1 (en) Queue pair wait state management in a host channel adapter

Legal Events

Date Code Title Description
AS Assignment

Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ACHARYA, YATIN R.;REEL/FRAME:011912/0513

Effective date: 20010615

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12