US6933174B1 - Leadless leadframe package design that provides a greater structural integrity - Google Patents

Leadless leadframe package design that provides a greater structural integrity Download PDF

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Publication number
US6933174B1
US6933174B1 US10/956,268 US95626804A US6933174B1 US 6933174 B1 US6933174 B1 US 6933174B1 US 95626804 A US95626804 A US 95626804A US 6933174 B1 US6933174 B1 US 6933174B1
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Prior art keywords
stems
recited
contacts
stem
interior surface
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US10/956,268
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Harry Kam Cheng Hong
Hu Ah Lek
Santhiran Nadarajah
Sharon Ko Mei Wan
Chan Peng Yeen
Jaime Bayan
Peter Howard Spalding
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National Semiconductor Corp
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National Semiconductor Corp
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Priority claimed from US09/724,728 external-priority patent/US6677667B1/en
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Publication of US6933174B1 publication Critical patent/US6933174B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates generally to the packaging of small-scale integrated circuits. More particularly, the invention relates to leadless leadframe package designs.
  • a leadless leadframe package is a relatively new integrated circuit package design that contemplates the use of a metal (typically copper) substrate in the formation of a chip scale package (CSP).
  • a copper leadframe strip or panel 10 is patterned to define a plurality of arrays or matrixes 11 of semiconductor device areas 12 .
  • Each device area 12 includes a die attach pad 13 and a plurality of contacts 15 disposed about their associated die attach pad 13 .
  • Very fine tie bars 16 are used to support the die attach pads 13 and contacts 15 .
  • FIG. 2 illustrates a cross-sectional view of a typical resulting leadless leadframe package 14 .
  • the die attach pad 13 supports a die 17 which is electrically connected to its associated contacts 15 by bonding wires 18 .
  • a molded cap 20 encapsulates the die 17 and bonding wires 18 , and fills the gaps between the die attach pad 13 and the contacts 15 thereby serving to hold the contacts 15 in place. It should be appreciated that during singulation of the individual packages 14 , the tie bars 16 are cut and therefore the only materials holding the contacts 15 in place is the molding material.
  • the resulting packaged chip can then be surface mounted on a printed circuit board or other substrate using conventional techniques.
  • FIG. 3A illustrates a bottom plan, perspective view of an improved leadless leadframe package 14 ′
  • FIG. 3B illustrates a fragmentary and enlarged view of one of the contacts 15 and the molding material immediately surrounding the contact 15
  • an edge portion of each contact 15 has been removed to define a stem 26 , which extends from an interior surface 25 of the contact 15 toward a respective peripheral surface 24 .
  • the molding material surrounds the stems 26 while leaving a peripheral surface 27 of the stems 26 exposed on the peripheral surfaces 24 of the package 14 ′.
  • the portion of the molded cap 20 that covers the bottom surface 28 of the stem 26 is indicated by the phantom lines 29 , and is referred to as the bar portion 30 .
  • the contacts 15 of this package design 14 ′ provide the above-mentioned advantages, the bar portions 30 have been found to occasionally break-away from the molded cap 20 by the frictional forces introduced during singulation. This results in structurally damaged leadless leadframe packages. Consequently, it would be desirable to further improve leadless leadframe package designs to have a greater degree of structural integrity.
  • the present invention is directed towards a leadless leadframe package that has a greater degree of structural integrity such that portions of the molded cap do not break off during singulation processes.
  • One aspect of the invention pertains to a method for singulating device areas from a leadless leadframe panel having a top and a bottom surface. The method includes at least providing a conductive substrate panel having at least one array of device areas. Each array of device areas has a plurality of tie bars and a plurality of contacts. The contacts have contact surfaces on the bottom surface of the leadless leadframe panel assembly and each of the contacts has at least one integrally formed stem that extends towards and connects to one of the tie bars. The stems each have a width and a height that are less than a width and height of their corresponding contacts. The method further includes cutting through at least some of the stems to singulate each device area from the conductive substrate panel.
  • a method of the present invention includes at least providing a conductive substrate panel having at least one array of device areas.
  • Each array of device areas has a plurality of tie bars and a plurality of contacts.
  • the contacts have contact surfaces on the bottom surface of the leadless leadframe panel assembly.
  • the contacts also have integrally formed first and second stems that extend towards and connect to one of the tie bars.
  • the first and second stems each have a width and height that are less than a width and height of their corresponding contacts.
  • the method also includes cutting through the first and second stems to singulate each device area from the conductive substrate panel.
  • a method of the present invention includes at least providing a conductive substrate panel having at least one array of device areas wherein each array of device areas has a plurality of tie bars and a plurality of contacts.
  • the contacts have contact surfaces on the bottom surface of the leadless leadframe panel assembly.
  • Each of the contacts also have at least one integrally formed stem that extends towards and connects to one of the tie bars.
  • the stems each have a width and height that are less than a width and height of their corresponding contacts.
  • the method further includes at least attaching a semiconductor die within each of the device areas, electrically connecting each of the semiconductor die to at least one contact, encapsulating the semiconductor die within a molded cap, and cutting through the molded cap and at least some of the stems to singulate each device area from the conductive substrate panel.
  • FIG. 1 is a top plan view of a conventional lead frame strip suitable for use in forming leadless leadframe packages.
  • FIG. 1B is an enlarged top plan view of one end of the lead frame strip of FIG. 1A , illustrating one array of device areas.
  • FIG. 2 is a cross-sectional side view of a conventional leadless leadframe package.
  • FIG. 3A is a bottom plan, perspective view of an improved leadless leadframe package.
  • FIG. 3B is an enlarged fragmentary view of a contact within the leadless leadframe package of FIG. 3A , including the molding material immediately surrounding the contact.
  • FIG. 4A illustrates a perspective view of the bottom of a packaged semiconductor device according to one embodiment of the present invention.
  • FIG. 4B is an enlarged fragmentary view of a contact within the leadless leadframe package of FIG. 4A , including the molding material immediately surrounding the contact.
  • FIG. 5 is a bottom plan, fragmentary view of a tie bar within a leadless leadframe panel according to one embodiment of the present invention.
  • FIG. 6 illustrates a side elevation view of the tie bar in FIG. 5 , at a cross-section along the plane of line 6 — 6 .
  • FIG. 7 is a bottom plan, fragmentary view of a tie bar within a leadless leadframe panel according to an alternative embodiment of the present invention.
  • FIG. 8A illustrates a perspective view of the bottom of a packaged semiconductor device that results from a leadless leadframe panel having a structure as illustrated in FIG. 7 .
  • FIG. 8B is an enlarged fragmentary view of a contact within the leadless leadframe package of FIG. 8A , including the molding material immediately surrounding the contact.
  • FIG. 9 is a bottom plan, fragmentary view of a tie bar within a leadless leadframe panel according to yet another alternative embodiment of the present invention.
  • FIG. 10A illustrates a perspective view of the bottom of a packaged semiconductor device that results from a leadless leadframe panel having a structure as illustrated in FIG. 9 .
  • FIG. 10B is an enlarged fragmentary view of a contact within the leadless leadframe package of FIG. 9 , including the molding material immediately surrounding the contact.
  • a leadless leadframe package 55 of the present invention includes a plurality of contacts 15 that each have stems 26 which extend to the peripheral surface 24 of the packages 55 .
  • the stems 26 have heights (H 1 ) and widths (W 1 ) less than the heights (H 2 ) and widths (W 2 ) of their respective contacts 15 (See FIGS. 5 and 6 ).
  • a molded cap 20 encapsulates the contacts 15 such that contact surfaces 47 of the contacts are exposed on the bottom surface 57 of the packages 55 .
  • the molded cap 20 also encapsulates the stems 26 such that after singulation a corresponding peripheral surface 27 thereof is exposed at the peripheral surface 24 of the packages 55 .
  • the reduced width dimension (W 1 ) of the stems correspondingly result in a reduced width dimension of the bar portions 30 of the molded cap 55 to cover a bottom surface 28 of the stems 26 . Consequently, the reduced width dimension of the molded bar portion 30 , versus its transverse cross-sectional dimension (i.e., the length ⁇ the height), improve the structural integrity and integral bond thereof to the molded cap 20 . Therefore, the bar portions 30 are less likely to break off during the singulation processes. Further, the smaller cross-sectional dimension of the sized stems 26 also reduce wear and tear of the singulating saw blades since the saw blade are required to pass through less metal during the singulation process.
  • FIG. 5 illustrates a bottom plan, fragmentary view of a tie bar 16 within a leadless leadframe panel according to one embodiment of the present invention.
  • FIG. 6 illustrates a side elevation view of the tie bar 16 at a cross-section along line 6 — 6 .
  • Electrical contacts 15 are integrally connected to the tie bar 16 through stems 26 .
  • the stems 26 have a width (W 1 ) and a height (H 1 ) that is less than the width (W 2 ) and the height (H 2 ) of their corresponding contacts 15 .
  • the stems 26 extend from the sidewalls 16 a of the tie bar 16 to the contacts 15 .
  • the tie bar 16 has a height that is substantially equal to the height, H 1 , of the stems 26 .
  • the section of the tie bar 16 between stems 26 on opposing sidewalls 16 a of tie bar 16 have heights that are substantially equal to the height of the stems 26 , while the remaining portions of the tie bars 16 have heights that are approximately equal to that of the contacts 15 .
  • the entire length of the tie bars 16 may have heights equal to that of the contacts 15 leaving only the stems 26 with relatively shorter heights.
  • the stems 26 preferably extend from an upper corner of the interior surface 25 of the contacts 15 .
  • the stems 26 are aligned along one of the sidewalls 23 of the contacts 15 and along the upper edge of the interior surface 25 such that a top wall of the stem is substantially co-planar with that of the contact, and a side wall of the stem is substantially co-planar with the sidewall 23 of the contact.
  • the structural configuration of the contacts, tie bars and stems are formed by selectively etching the leadless leadframe panel, such as panel 10 in FIGS. 1A and 1B .
  • Other conventional fabrication techniques may be employed however.
  • semiconductor dice (not shown) are attached to the panel, and connected to the contacts 15 with electrical connectors (not shown).
  • the encapsulation cap 20 is then formed through flood molding techniques or the like. Upon application of the molding material, at least a portion of the dice, the connectors, the tie bars and the contacts are encapsulated therein. As best viewed in FIGS.
  • the molding material further surrounds the stems 26 , while the bottom or contact surfaces 47 of the contacts 15 remain exposed at the bottom surface of the packaged device. These exposed surfaces of the contacts form connection points to an electrical substrate (not shown).
  • the individual semiconductor device packages are then singulated from the panel by passing a singulating saw blade in the path of phantom lines 50 . As the saw blade passes along phantom lines 50 , the tie bar 16 and part of the stems 26 , in the path of the blade, are essentially removed. Therefore, the resulting packages have stems 26 with lengths (L 1 ).
  • the singulation process exposes the peripheral surfaces 27 of the stems 26 , as well as peripheral surface 24 of the package 55 ( FIGS. 4A and 4B ).
  • the contact surfaces 47 of the contacts 15 and the die attach pad 13 are also exposed on the bottom surface 57 of the package 55 . These contact surfaces 47 are further offset from the peripheral surfaces 24 of the package 55 and the peripheral surfaces 27 of the stems 26 are offset from the bottom surface 57 of the package 55 .
  • FIG. 4B illustrates a fragmentary, perspective view of one of the contacts 15 and the molding material that immediately surrounds the contact 15 .
  • the phantom lines 59 designate the bar portion 30 of the molded cap 20 that covers the bottom surface 28 of the stems 26 .
  • the width dimension (W 1 ) of the stems 26 are significantly reduced (versus the length (L 1 ) and height (H 1 )) so that the relative structural integrity between the corresponding bar portions 30 , the interior surface 25 of the contacts, stems and molded cap 20 are improved. Consequently, the frictional forces induced by singulating saw blade during singulation are less likely to breakaway and separate bar portion 30 from the package 55 .
  • the widths (W 1 ) of the stems 26 are one of the primary stem dimension components which dictate the structural integrity between the integral bar portions 30 and the molded cap 20 .
  • the wider the stem dimensions, the wider the resulting bar portions 30 which correspondingly exposes a greater amount of the bar portions' surface area to the singulating saw blade. Wider bar portions are therefore more vulnerable to pull out during singulation.
  • the width of the stems 26 may be varied depending upon the design requirements of each package.
  • the stem heights also affect the integrity of the bar portions 30 .
  • Taller stems decrease the bar portion heights and thereby, the bar portion surface areas. Therefore, the stem heights may also be varied to obtain different degrees of structural integrity.
  • Stem length affects the integrity of the bar portions 30 even though the surface area of the bar portions is not affected. Longer stems result in longer bar portions 30 , which allow the bar portions to be integrally connected to the molded cap through larger connection points. Longer stems therefore allow bar portions to exhibit greater structural integrity.
  • the relative structural integrity between the bar portions 30 and the molded cap 20 can be altered by varying the dimensions of the stems 26 .
  • the bar portions 30 have the greatest amount of structural integrity when the stems 26 are sized such that the length, width and height of the bar portions are substantially equal, e.g., cubical in shape. It should be noted, however, that the dimensions of the stems 26 should not be so small that they would not be able to properly support the corresponding contacts 15 in the leadframe panel.
  • the width of stems 26 should not be less than approximately 0.004 inches. However, as technological advances enable the size and weight of the contacts to diminish, the width of the stems may correspondingly be sized less than 0.004 inches.
  • the stem 26 can be formed to extend from various positions on the interior surface 25 of the contacts 15 , so long as they are offset from the bottom surface 47 of the contacts 15 .
  • the stems 26 extend from a position that is offset from both of the sidewalls 23 .
  • the stems preferably extend from the center of the contact interior surface 25 , and are aligned such that the top wall of the stem is substantially co-planar with that of the contact. Similar to the previous arrangements, the relative structural integrity between the bar portions 30 and the molded cap 20 can be altered by varying the dimensions of the stems 26 .
  • FIGS. 9–10B yet another alternative embodiment of the leadless leadframe panel is illustrated having a pair of stems 26 supporting each respective contact 15 to the tie bar 16 .
  • the stems 26 preferably extend from the outer edges of the contacts 15 such that an open channel 63 passes from the top surface to the bottom surface of the stems 26 and tie bars 16 .
  • FIG. 10A illustrates a bottom plan, perspective view of a packaged device 65 resulting from a leadless leadframe panel having a structure as shown in FIG. 9 .
  • FIG. 10B illustrates a fragmentary, perspective view of a contact 15 within the packaged device, including the portion of the molded cap immediately surrounding the contact, in FIG. 8A .
  • the two stems 26 of each contact 15 are each surrounded by molding material of the molded cap 20 such that a bar portion 30 covers the bottom surface of each stem 26 .

Abstract

A leadless leadframe semiconductor package having a plurality of contacts, which have contact surfaces on the bottom surface of the package. At least some of the contacts have integrally formed stems that extend outward to the peripheral surface of the package. These stems have heights and widths less than the heights and widths of their corresponding contacts. A molded cap encapsulates at least a portion of the die, the stems and the contacts. Another aspect of the invention pertains to a leadless leadframe panel assembly having a conductive substrate panel that has at least one array of device areas, each array of device areas having a plurality of tie bars and a plurality of contacts. The contacts also have integrally formed stems that extend towards and connect to one of the tie bars. The stems have widths and heights that are less than the widths and heights of their corresponding contacts.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This patent application is a continuation of prior application Ser. No. 10/639,226, filed Aug. 11, 2003 now U.S. Pat. No. 6,818,970, entitled “Leadless Leadframe Package Design that Provides a Greater Structural Integrity”, which is a continuation of Ser. No. 09/724,728 now U.S. Pat. No. 6,677,667, filed Nov. 28, 2000, entitled “Leadless Leadframe Package Design that Provides a Greater Structural Integrity”, the content of both of which are hereby incorporated by reference.
This application is related to U.S. patent application Ser. No. 09/470,826 filed Dec. 23, 1999, and entitled “LEAD FRAME DESIGN FOR BURR-FREE SINGULATION OF MOLDED ARRAY,” the content of which is hereby incorporated by reference.
FIELD OF THE INVENTION
The present invention relates generally to the packaging of small-scale integrated circuits. More particularly, the invention relates to leadless leadframe package designs.
BACKGROUND
A leadless leadframe package (LLP) is a relatively new integrated circuit package design that contemplates the use of a metal (typically copper) substrate in the formation of a chip scale package (CSP). As illustrated in FIGS. 1A and 1B, in typical leadless leadframe packages, a copper leadframe strip or panel 10 is patterned to define a plurality of arrays or matrixes 11 of semiconductor device areas 12. Each device area 12 includes a die attach pad 13 and a plurality of contacts 15 disposed about their associated die attach pad 13. Very fine tie bars 16 are used to support the die attach pads 13 and contacts 15.
FIG. 2 illustrates a cross-sectional view of a typical resulting leadless leadframe package 14. The die attach pad 13 supports a die 17 which is electrically connected to its associated contacts 15 by bonding wires 18. A molded cap 20 encapsulates the die 17 and bonding wires 18, and fills the gaps between the die attach pad 13 and the contacts 15 thereby serving to hold the contacts 15 in place. It should be appreciated that during singulation of the individual packages 14, the tie bars 16 are cut and therefore the only materials holding the contacts 15 in place is the molding material. The resulting packaged chip can then be surface mounted on a printed circuit board or other substrate using conventional techniques.
FIG. 3A illustrates a bottom plan, perspective view of an improved leadless leadframe package 14′, while FIG. 3B illustrates a fragmentary and enlarged view of one of the contacts 15 and the molding material immediately surrounding the contact 15. In this improved design, an edge portion of each contact 15 has been removed to define a stem 26, which extends from an interior surface 25 of the contact 15 toward a respective peripheral surface 24. The molding material surrounds the stems 26 while leaving a peripheral surface 27 of the stems 26 exposed on the peripheral surfaces 24 of the package 14′. The portion of the molded cap 20 that covers the bottom surface 28 of the stem 26 is indicated by the phantom lines 29, and is referred to as the bar portion 30. These bar portions 30, integrally formed into the molded cap 20, function to lock the contact 15 into the molded cap 20 so that they are not pulled out by the singulating saw blade during the singulation process. Furthermore, the thinned peripheral edges of the contacts 15 reduce stress on the singulating saw blade since it is only required to cut through a smaller amount of metal during the singulation process. For further details, refer to U.S. patent application Ser. No. 09/470,826.
Although the contacts 15 of this package design 14′ provide the above-mentioned advantages, the bar portions 30 have been found to occasionally break-away from the molded cap 20 by the frictional forces introduced during singulation. This results in structurally damaged leadless leadframe packages. Consequently, it would be desirable to further improve leadless leadframe package designs to have a greater degree of structural integrity.
SUMMARY
The present invention is directed towards a leadless leadframe package that has a greater degree of structural integrity such that portions of the molded cap do not break off during singulation processes. One aspect of the invention pertains to a method for singulating device areas from a leadless leadframe panel having a top and a bottom surface. The method includes at least providing a conductive substrate panel having at least one array of device areas. Each array of device areas has a plurality of tie bars and a plurality of contacts. The contacts have contact surfaces on the bottom surface of the leadless leadframe panel assembly and each of the contacts has at least one integrally formed stem that extends towards and connects to one of the tie bars. The stems each have a width and a height that are less than a width and height of their corresponding contacts. The method further includes cutting through at least some of the stems to singulate each device area from the conductive substrate panel.
In another embodiment, a method of the present invention includes at least providing a conductive substrate panel having at least one array of device areas. Each array of device areas has a plurality of tie bars and a plurality of contacts. The contacts have contact surfaces on the bottom surface of the leadless leadframe panel assembly. The contacts also have integrally formed first and second stems that extend towards and connect to one of the tie bars. The first and second stems each have a width and height that are less than a width and height of their corresponding contacts. The method also includes cutting through the first and second stems to singulate each device area from the conductive substrate panel.
In yet another embodiment, a method of the present invention includes at least providing a conductive substrate panel having at least one array of device areas wherein each array of device areas has a plurality of tie bars and a plurality of contacts. The contacts have contact surfaces on the bottom surface of the leadless leadframe panel assembly. Each of the contacts also have at least one integrally formed stem that extends towards and connects to one of the tie bars. The stems each have a width and height that are less than a width and height of their corresponding contacts. The method further includes at least attaching a semiconductor die within each of the device areas, electrically connecting each of the semiconductor die to at least one contact, encapsulating the semiconductor die within a molded cap, and cutting through the molded cap and at least some of the stems to singulate each device area from the conductive substrate panel.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures that illustrate by way of example the principles of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a top plan view of a conventional lead frame strip suitable for use in forming leadless leadframe packages.
FIG. 1B is an enlarged top plan view of one end of the lead frame strip of FIG. 1A, illustrating one array of device areas.
FIG. 2 is a cross-sectional side view of a conventional leadless leadframe package.
FIG. 3A is a bottom plan, perspective view of an improved leadless leadframe package.
FIG. 3B is an enlarged fragmentary view of a contact within the leadless leadframe package of FIG. 3A, including the molding material immediately surrounding the contact.
FIG. 4A illustrates a perspective view of the bottom of a packaged semiconductor device according to one embodiment of the present invention.
FIG. 4B is an enlarged fragmentary view of a contact within the leadless leadframe package of FIG. 4A, including the molding material immediately surrounding the contact.
FIG. 5 is a bottom plan, fragmentary view of a tie bar within a leadless leadframe panel according to one embodiment of the present invention.
FIG. 6 illustrates a side elevation view of the tie bar in FIG. 5, at a cross-section along the plane of line 6—6.
FIG. 7 is a bottom plan, fragmentary view of a tie bar within a leadless leadframe panel according to an alternative embodiment of the present invention.
FIG. 8A illustrates a perspective view of the bottom of a packaged semiconductor device that results from a leadless leadframe panel having a structure as illustrated in FIG. 7.
FIG. 8B is an enlarged fragmentary view of a contact within the leadless leadframe package of FIG. 8A, including the molding material immediately surrounding the contact.
FIG. 9 is a bottom plan, fragmentary view of a tie bar within a leadless leadframe panel according to yet another alternative embodiment of the present invention.
FIG. 10A illustrates a perspective view of the bottom of a packaged semiconductor device that results from a leadless leadframe panel having a structure as illustrated in FIG. 9.
FIG. 10B is an enlarged fragmentary view of a contact within the leadless leadframe package of FIG. 9, including the molding material immediately surrounding the contact.
 DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to not unnecessarily obscure the present invention.
The present invention pertains to leadless leadframe packages with improved structural integrity. Specifically, referring now to FIGS. 4A and 4B, the leadless leadframe packages 55 are designed to significantly reduce the breakaway problems of the bar portions 30 of the molded cap 20 occurring during the singulation of the leadframe panels. A leadless leadframe package 55 of the present invention includes a plurality of contacts 15 that each have stems 26 which extend to the peripheral surface 24 of the packages 55. The stems 26 have heights (H1) and widths (W1) less than the heights (H2) and widths (W2) of their respective contacts 15 (See FIGS. 5 and 6). A molded cap 20 encapsulates the contacts 15 such that contact surfaces 47 of the contacts are exposed on the bottom surface 57 of the packages 55. The molded cap 20 also encapsulates the stems 26 such that after singulation a corresponding peripheral surface 27 thereof is exposed at the peripheral surface 24 of the packages 55.
Accordingly, the reduced width dimension (W1) of the stems correspondingly result in a reduced width dimension of the bar portions 30 of the molded cap 55 to cover a bottom surface 28 of the stems 26. Consequently, the reduced width dimension of the molded bar portion 30, versus its transverse cross-sectional dimension (i.e., the length×the height), improve the structural integrity and integral bond thereof to the molded cap 20. Therefore, the bar portions 30 are less likely to break off during the singulation processes. Further, the smaller cross-sectional dimension of the sized stems 26 also reduce wear and tear of the singulating saw blades since the saw blade are required to pass through less metal during the singulation process.
FIG. 5 illustrates a bottom plan, fragmentary view of a tie bar 16 within a leadless leadframe panel according to one embodiment of the present invention. FIG. 6 illustrates a side elevation view of the tie bar 16 at a cross-section along line 6—6. Electrical contacts 15 are integrally connected to the tie bar 16 through stems 26. The stems 26 have a width (W1) and a height (H1) that is less than the width (W2) and the height (H2) of their corresponding contacts 15. The stems 26 extend from the sidewalls 16 a of the tie bar 16 to the contacts 15. Referring to FIG. 5, the tie bar 16 has a height that is substantially equal to the height, H1, of the stems 26. In alternative embodiments, the section of the tie bar 16 between stems 26 on opposing sidewalls 16 a of tie bar 16 have heights that are substantially equal to the height of the stems 26, while the remaining portions of the tie bars 16 have heights that are approximately equal to that of the contacts 15. In yet another alternative embodiment, the entire length of the tie bars 16 may have heights equal to that of the contacts 15 leaving only the stems 26 with relatively shorter heights.
In the preferred embodiment, the stems 26 preferably extend from an upper corner of the interior surface 25 of the contacts 15. Thus, the stems 26 are aligned along one of the sidewalls 23 of the contacts 15 and along the upper edge of the interior surface 25 such that a top wall of the stem is substantially co-planar with that of the contact, and a side wall of the stem is substantially co-planar with the sidewall 23 of the contact.
Generally, the structural configuration of the contacts, tie bars and stems are formed by selectively etching the leadless leadframe panel, such as panel 10 in FIGS. 1A and 1B. Other conventional fabrication techniques may be employed however. Once the leadless leadframe panel has been properly etched, briefly, semiconductor dice (not shown) are attached to the panel, and connected to the contacts 15 with electrical connectors (not shown). The encapsulation cap 20 is then formed through flood molding techniques or the like. Upon application of the molding material, at least a portion of the dice, the connectors, the tie bars and the contacts are encapsulated therein. As best viewed in FIGS. 4A and 4B, the molding material further surrounds the stems 26, while the bottom or contact surfaces 47 of the contacts 15 remain exposed at the bottom surface of the packaged device. These exposed surfaces of the contacts form connection points to an electrical substrate (not shown). The individual semiconductor device packages are then singulated from the panel by passing a singulating saw blade in the path of phantom lines 50. As the saw blade passes along phantom lines 50, the tie bar 16 and part of the stems 26, in the path of the blade, are essentially removed. Therefore, the resulting packages have stems 26 with lengths (L1).
The singulation process exposes the peripheral surfaces 27 of the stems 26, as well as peripheral surface 24 of the package 55 (FIGS. 4A and 4B). The contact surfaces 47 of the contacts 15 and the die attach pad 13 are also exposed on the bottom surface 57 of the package 55. These contact surfaces 47 are further offset from the peripheral surfaces 24 of the package 55 and the peripheral surfaces 27 of the stems 26 are offset from the bottom surface 57 of the package 55.
FIG. 4B illustrates a fragmentary, perspective view of one of the contacts 15 and the molding material that immediately surrounds the contact 15. The phantom lines 59 designate the bar portion 30 of the molded cap 20 that covers the bottom surface 28 of the stems 26. The width dimension (W1) of the stems 26 are significantly reduced (versus the length (L1) and height (H1)) so that the relative structural integrity between the corresponding bar portions 30, the interior surface 25 of the contacts, stems and molded cap 20 are improved. Consequently, the frictional forces induced by singulating saw blade during singulation are less likely to breakaway and separate bar portion 30 from the package 55.
In the present invention, the widths (W1) of the stems 26 are one of the primary stem dimension components which dictate the structural integrity between the integral bar portions 30 and the molded cap 20. The wider the stem dimensions, the wider the resulting bar portions 30, which correspondingly exposes a greater amount of the bar portions' surface area to the singulating saw blade. Wider bar portions are therefore more vulnerable to pull out during singulation.
The width of the stems 26 may be varied depending upon the design requirements of each package. The stem heights also affect the integrity of the bar portions 30. Taller stems decrease the bar portion heights and thereby, the bar portion surface areas. Therefore, the stem heights may also be varied to obtain different degrees of structural integrity. Stem length affects the integrity of the bar portions 30 even though the surface area of the bar portions is not affected. Longer stems result in longer bar portions 30, which allow the bar portions to be integrally connected to the molded cap through larger connection points. Longer stems therefore allow bar portions to exhibit greater structural integrity.
Therefore, the relative structural integrity between the bar portions 30 and the molded cap 20 can be altered by varying the dimensions of the stems 26. The bar portions 30 have the greatest amount of structural integrity when the stems 26 are sized such that the length, width and height of the bar portions are substantially equal, e.g., cubical in shape. It should be noted, however, that the dimensions of the stems 26 should not be so small that they would not be able to properly support the corresponding contacts 15 in the leadframe panel. Currently the width of stems 26 should not be less than approximately 0.004 inches. However, as technological advances enable the size and weight of the contacts to diminish, the width of the stems may correspondingly be sized less than 0.004 inches.
It should be noted that the stem 26 can be formed to extend from various positions on the interior surface 25 of the contacts 15, so long as they are offset from the bottom surface 47 of the contacts 15. For instance, as shown in FIGS. 7–8B, the stems 26 extend from a position that is offset from both of the sidewalls 23. In this embodiment, the stems preferably extend from the center of the contact interior surface 25, and are aligned such that the top wall of the stem is substantially co-planar with that of the contact. Similar to the previous arrangements, the relative structural integrity between the bar portions 30 and the molded cap 20 can be altered by varying the dimensions of the stems 26.
Referring now FIGS. 9–10B, yet another alternative embodiment of the leadless leadframe panel is illustrated having a pair of stems 26 supporting each respective contact 15 to the tie bar 16. The stems 26 preferably extend from the outer edges of the contacts 15 such that an open channel 63 passes from the top surface to the bottom surface of the stems 26 and tie bars 16. FIG. 10A illustrates a bottom plan, perspective view of a packaged device 65 resulting from a leadless leadframe panel having a structure as shown in FIG. 9. FIG. 10B illustrates a fragmentary, perspective view of a contact 15 within the packaged device, including the portion of the molded cap immediately surrounding the contact, in FIG. 8A. The two stems 26 of each contact 15 are each surrounded by molding material of the molded cap 20 such that a bar portion 30 covers the bottom surface of each stem 26.
While this invention has been described in terms of several preferred embodiments, there are alteration, permutations, and equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.

Claims (27)

1. A method for singulating device areas from a leadless leadframe panel having a top and a bottom surface, the method comprising:
providing a conductive substrate panel having at least one array of device areas, each array of device areas having a plurality of tie bars and a plurality of contacts, the contacts having contact surfaces on the bottom surface of the leadless leadframe panel assembly, each of the contacts also having at least one integrally formed stem that extends towards and connects to one of the tie bars, the stems each having a width and height that are less than a width and height of their corresponding contacts; and
cutting through at least some of the stems to singulate each device area from the conductive substrate panel.
2. A method as recited in claim 1 wherein the cutting operation cuts in a direction that is parallel to a respective tie bar.
3. A method as recited in claim 1 wherein the cutting operation cuts along a respective tie bar such that the tie bar and a portion of each cut stem is removed.
4. A method as recited in claim 1 wherein the cutting operation is performed by a saw blade.
5. A method as recited in claim 1 further comprising:
attaching a semiconductor die within each of the device areas;
electrically connecting each of the semiconductor die to at least one contact; and
encapsulating the semiconductor die within a molded cap.
6. A method as recited in claim 5 wherein the cutting operation also cuts through the molded cap.
7. A method as recited in claim 1 wherein at least one contact includes an interior surface, and said stem extending from the respective interior surface.
8. A method as recited in claim 7 wherein the stem is offset from a bottom edge of the interior surface.
9. A method as recited in claim 7 wherein the interior surface of the one contact is positioned between opposed side walls thereof, and the stem is positioned offset from said opposed side walls.
10. A method as recited in claim 9 wherein the stem extends from an upper edge of the interior surface.
11. A method as recited in claim 1 wherein the stem is generally rectangular-shaped.
12. A method as recited in claim 1 wherein at least one contact includes one stem that extends toward the tie bars along an axis perpendicular to a corresponding contact surface.
13. A method for singulating device areas from a leadless leadframe panel having a top and a bottom surface, the method comprising:
providing a conductive substrate panel having at least one array of device areas, each array of device areas having a plurality of tie bars and a plurality of contacts, the contacts having contact surfaces on the bottom surface of the leadless leadframe panel assembly,
wherein the contacts also have integrally formed first and second stems that extend towards and connect to one of the tie bars, the frat and second stems each having a width and height that are less than a width and height of their corresponding contacts; and
cutting through the first and second stems to singulate each device area from the conductive substrate panel.
14. A method as recited in claim 13 wherein the cuts operation cuts in a direction that is parallel to a respective tie bar.
15. A method as recited in claim 13 wherein the cutting operation cuts along a respective tie bar such that the tie bar and a portion of each cut stem is removed.
16. A method as recited in claim 13 wherein the cutting operation is performed by a saw blade.
17. A method as recited in claim 13 fiber comprising:
attaching a semiconductor die within each of the device areas;
electrically connecting each of the semiconductor die to at least one contact; and
encapsulating the semiconductor die within a molded cap.
18. A method as recited in claim 13 wherein at least one contact includes an interior surface, and said first and second stems extending from the respective interior surface.
19. A method as recited in claim 18 wherein the first stems and the second stems are offset from a bottom edge of the interior surface.
20. A method as recited in claim 18 wherein the first stems and the second stems from an upper edge of the interior surface.
21. A method as recited in claim 20 wherein the first stems and the second stems extend from opposite corners on the upper edge of the interior surface.
22. A method as recited in claim 13 wherein the fast stems and the second stems are generally rectangular-shaped.
23. A method for singulating device areas from a leadless leadframe panel having a top and a bottom surface, the method comprising:
providing a conductive substrate panel having at least one array of device areas, each array of device areas having a plurality of tie bars and a plurality of contacts, the contacts having contact surfaces on the bottom surface of the leadless leadframe panel assembly, each of the contacts also having at least one integrally formed stem that extends towards and connects to one of the tie bars, the stems each having a width and height that are less than a width and height of their corresponding contacts;
attaching a semiconductor die within each of the device areas;
electrically connecting each of the semiconductor die to at least one contact; and
encapsulating the semiconductor die within a molded cap; and
cutting through the molded cap and at least some of the stems to singulate each device area from the conductive substrate panel.
24. A method as recited in claim 23 wherein the cutting operation cuts in a direction that is parallel to a respective tie bar.
25. A method as recited in claim 23 wherein the cutting operation cuts along a respective tie bar such that the tie bar and a portion of each cut stem is removed.
26. A method as recited in claim 23 wherein at least one contact includes an interior surface, and said stem extending from the respective interior surface.
27. A method as recited in claim 26 wherein the stem is offset from a bottom edge of the interior surface.
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Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157480A (en) 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5157475A (en) 1988-07-08 1992-10-20 Oki Electric Industry Co., Ltd. Semiconductor device having a particular conductive lead structure
US5172214A (en) 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
US5521429A (en) 1993-11-25 1996-05-28 Sanyo Electric Co., Ltd. Surface-mount flat package semiconductor device
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5783861A (en) 1994-03-29 1998-07-21 Lg Semicon Co., Ltd. Semiconductor package and lead frame
US5835988A (en) 1996-03-27 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Packed semiconductor device with wrap around external leads
US5859387A (en) 1996-11-29 1999-01-12 Allegro Microsystems, Inc. Semiconductor device leadframe die attach pad having a raised bond pad
US5861668A (en) 1996-06-14 1999-01-19 Lg Semicon Co., Ltd. Semiconductor package
US5886397A (en) 1996-09-05 1999-03-23 International Rectifier Corporation Crushable bead on lead finger side surface to improve moldability
US5942794A (en) 1996-10-22 1999-08-24 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
US6201292B1 (en) 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
US6201294B1 (en) 1996-12-28 2001-03-13 Hyundai Electronics Industries Co., Ltd. Ball grid array semiconductor package comprised of two lead frames
US6483180B1 (en) 1999-12-23 2002-11-19 National Semiconductor Corporation Lead frame design for burr-free singulation of molded array packages

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157475A (en) 1988-07-08 1992-10-20 Oki Electric Industry Co., Ltd. Semiconductor device having a particular conductive lead structure
US5157480A (en) 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5172214A (en) 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
US5521429A (en) 1993-11-25 1996-05-28 Sanyo Electric Co., Ltd. Surface-mount flat package semiconductor device
US5783861A (en) 1994-03-29 1998-07-21 Lg Semicon Co., Ltd. Semiconductor package and lead frame
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5835988A (en) 1996-03-27 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Packed semiconductor device with wrap around external leads
US5861668A (en) 1996-06-14 1999-01-19 Lg Semicon Co., Ltd. Semiconductor package
US5886397A (en) 1996-09-05 1999-03-23 International Rectifier Corporation Crushable bead on lead finger side surface to improve moldability
US5942794A (en) 1996-10-22 1999-08-24 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
US5859387A (en) 1996-11-29 1999-01-12 Allegro Microsystems, Inc. Semiconductor device leadframe die attach pad having a raised bond pad
US6201294B1 (en) 1996-12-28 2001-03-13 Hyundai Electronics Industries Co., Ltd. Ball grid array semiconductor package comprised of two lead frames
US6201292B1 (en) 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
US6483180B1 (en) 1999-12-23 2002-11-19 National Semiconductor Corporation Lead frame design for burr-free singulation of molded array packages

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