US6920470B2 - Signal processing integrated circuit - Google Patents
Signal processing integrated circuit Download PDFInfo
- Publication number
- US6920470B2 US6920470B2 US09/803,349 US80334901A US6920470B2 US 6920470 B2 US6920470 B2 US 6920470B2 US 80334901 A US80334901 A US 80334901A US 6920470 B2 US6920470 B2 US 6920470B2
- Authority
- US
- United States
- Prior art keywords
- integrated circuit
- bus
- processor
- sinc
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/17—Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Microcomputers (AREA)
Abstract
A low power programmable digital filter integrated circuit architecture has a programmable front end servicing up to 4 digital sources. Changing the programming of the front end permits digital outputs from different sensor types to be accommodated. Digital filtering is accomplished using a digital signal processor that is programmable to accommodate different decimation ratios. A serial data output register receives the filtered digital signals and provides them to an output port. The digital filter integrated circuit may be connected in a token passing configuration with other digital filter integrated circuits to increase the number of sources accommodated.
Description
This application is related to abandoned U.S. patent application Ser. No. 09/802,744, filed concurrently herewith by inventors Joel Page, Wai Liang Lee and Erng Sing Wee, entitled “AN INTEGRATED CIRCUIT ARRANGEMENT FOR MULTIPLE-SENSOR WPES WITH SELECTING A DIGITAL FILTER INPUT SIGNAL.”
This application is related to U.S. Pat. No. 6,434,213, filed concurrently herewith, by inventor Trenton J. Grale, entitled “LOW-POWER LOW-AREA SHIFT REGISTER.”
This application is related to abandoned U.S. patent application Ser. No. 09/803,350, filed concurrently herewith, by inventors Trenton J. Grale and Sijian Chen, entitled “PROGRAMMABLE TEST MODULATOR FOR SELECTIVELY GENERATING TEST SIGNALS OF DELTA-SIGMA ORDER N”.
1. Field of the Invention
The invention is directed to a programmable integrated circuit, and more particularly, to an integrated circuit having a programmable front end.
2. Description of Related Art
Systems for conducting seismic exploration are well known in the art. On land, a plurality of transducers are deployed over a region and configured to receive reflections of an acoustic signal from different geophysical layers beneath the surface of the earth. In the ocean, arrays of transducers may be towed behind a boat in a spaced configuration in order to detect those reflections. In transition regions, between land and ocean, sensors may be positioned underwater at fixed locations. Different types of sensors may be utilized for the different environments in which they may be deployed.
When utilizing a seismic system, a strong acoustic signal is generated by, for example, setting off an explosion or by utilizing an acoustic signal generator having a relatively high power output. Reflections of the acoustic signals from the geophysical layers are then received at the seismic sensors deployed over a given area and the signals recorded, typically, for later analysis.
In some configurations, a seismic sensor is co-located with an analog to digital converter, such as a delta-sigma modulator, which converts an analog signal from the sensor into a digital signal for recording and processing. Seismic exploration has exacting requirements for seismic sensors and for the electronics which process the signals derived from those sensors. There is therefore a need to be able to test both the sensors and related equipment to ensure that both devices and the associated electronics are functioning properly.
The invention is directed to a programmable integrated circuit, and, more particularly, to an integrated circuit having a programmable front end for selectively processing incoming signals having different characteristics.
Still other objects and advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.
FIGS. 30C1 through 30C10 identify symbols used in FIGS. 30D through 30H .
FIG. 30F1 shows one implementation of the digital Σ modulator of FIG. 30B using a pipeline to perform feedward summing and integration.
FIG. 30F2 is a system state table for the implementation shown in FIG. 30F1.
FIG. 30G1 shows one implementation of the digital Σ modulator of FIG. 30B using a hybrid memory system.
FIG. 30G2 is a system state table for the implementation shown in FIG. 30G2.
FIG. 30H1 shows one implementation of the digital Σ modulator of FIG. 30B that attempts to reuse hardware as much as possible.
FIG. 30H2 is a system state table for the implementation shown in FIG. 30H1.
This architecture is based on using look up tables instead of performing multiplications. The coefficients are symmetric and this permits one to use one half the expected number of look up tables.
The Sinc1 b filter is represented mathematically as shown in FIG. 9. The impulse response of this filter is shown mathematically in this Figure as well.
Once each of the many Sinc filters have been arranged for shifts and adds and organized into accumulator and output subroutines, one needs to arrange the order of the execution of the subroutines to accommodate all the calculations. The number of additions/subtractions one can perform is based on the spacing between input values received from Sinc1. Because Sinc2 runs at 512 kHz, for an input from Sinc1 of 64 kHz, we have the ability to do eight addition/subtractions per input word.
The steps which can be utilized to create a program for operating the Sinc filters will be described with respect to an example.
-
-
Step 1—Chose the desired decimation rate. In this example, we will utilize 16. -
Step 2—Select which filters need to be involved in the decimation. This can be done conveniently by reference toFIG. 6 , where one can readily see that mini-sinc filters 2 a, 2 b, 2 d and 2 e can be utilized to achieve a decimation ratio of 16. -
Step 3—Separate coefficients into form suitable for shift-add operations. This can be done from the mathematical representation using an approach similar to that shown in FIG. 12. -
Step 4—Check for overflow after each addition in the filter. See the discussion ofFIG. 22 which follows. -
Step 5—Perform the necessary truncation to 24-bits and scaling of subsequent coefficients in mini-sincs. See the discussion of FIG. 22. -
Step 6—Time multiplex accumulate in output subroutines so that a maximum of eight operations can occur from each input from Sinc1. -
Step 7—Create code for RAM2 (Accumulate and Output Subroutines) in the form: [Coeff 1] [Src 1] [Src 2] [Dest] [Coeff2] [Done Subroutine]. -
Step 8—Create code for RAM1 (Main Control code): [Line #] [Wait for new data] [Done program].
-
If saturation does not occur (2220-no), one checks (2230) to see if the complete Sinc filter processing has been completed, if not, one returns to step 2210 for further processing. If processing has been completed (2230-yes), the process ends (2250).
The TMOD is designed to perform digital delta-sigma modulation, receiving 24-bit input data and generating 1-bit output data and CLK. It is implemented using a programmable microsequencer. It produces an output bit by executing a sequence of microinstructions. Because of its programming flexibility, it can perform several variations on the basic digital delta-sigma modulator algorithm.
FIGS. 30C1 through 30C10 identify symbols used in FIGS. 30D through 30H .
FIG. 30F1 shows one implementation of the digital Σ modulator of FIG. 30B using a pipeline to perform feedward summing and integration.
FIG. 30F2 is a system state table for the implementation shown in FIG. 30F1.
FIG. 30G1 shows one implementation of the digital Σ modulator of FIG. 30B using a hybrid memory system. The circuit uses a RAM and a 2 stage data pipeline to reduce the number of RAM reads/writes.
FIG. 30G2 is a system state table for the implementation shown in FIG. 30G2. Since many of the components are reused for similar operations, the control for the hybrid memory system has more states than the other system.
FIG. 30H1 shows one implementation of the digital Σ modulator of FIG. 30B that attempts to reuse hardware as much as possible.
FIG. 30H2 is a system state table for the implementation shown in FIG. 30H1.
By nature of their design, these systems can easily be adapted or modified for different configurations. The programmable nature of the integrated circuit described herein permits selective implementation of two or more of these different architectural implementations of a Σ modulator. Not only can the particular implementation, be selected, but the order N of a particular implementation can be selected by selecting different coefficient sets.
The particular architecture of an implementation, as well as the order N of the algorithm can be set and changed by control signals, for example by those originating from a sequencer.
An example will now be given of the programming of the TMOD buffer and filter device in carrying an exemplary algorithm.
The TMOD architecture consists of data and control registers, arithmetic logic units and buses. Most of the registers are internal and are accessible to the DSP indirectly. Internal registers include microprogram registers; feedback constant registers; configuration bits for interpolation factor, CLK rate, output and output delay, and data registers for integration in a feed forward sum. The DSP interfaces to the TMOD through two DSP I/O registers, TMODCFG and TMODDAT. The DSP uses TMODCFG and TMODDAT to configure the TMOD and uses TMODDAT to supply data during operation. During programming, the DSP writes control bits in TMODCFG which causes the contents of TMODDAT and some bits of TMODCFG to be strobed into a selected internal register. When the TMOD is running the DSP supplies the input data by writing to TMODDAT.
An example of the translation from the algorithm shown in FIG. 33 to the programming required to implement that algorithm in the hardware shown in FIG. 32 is shown in FIG. 34. Thus, the binary programming needed for the microinstruction registers 3100I of FIG. 31 is that shown in FIG. 34. By loading these instructions from FIG. 34 into the instruction registers of 3100I, of FIG. 31 , one can implement the algorithm shown in FIG. 33.
The architecture described results in a much simpler implementation from that which would be required to achieve a commensurate delay flexibility in the prior art.
The register illustrated achieves a delay of from 0- to 63-bits selectively. It does so in this manner by having a 15-bit register D with 16 individual taps shown which will permit delays from 0- to 15-bits.
If more than 16-bits delay is required, one or more of the 16-bit untapped shift registers A through C are selected for receiving the undelayed input. Thus, the delays are divided into four segments. Three of the segments have fixed delays of 16-bits. And one segment has a selectable delay from 0- to 15-bits. The amount of the delay is specified by a 6-bit word. The bits of that word are described in FIG. 35B. The undelayed incoming data is applied to a pin that is unique to each data segment of a selector. The particular segment to receive the undelayed data is selected by bits 4 and 5 of the delay word. If the bits are 00, then the undelayed data is applied to segment D only. If the bits are 01, the undelayed data is applied to segment C and followed by being applied to segment D with an output tab specified by bits 0 through 3 of the delay word. In this manner, one can achieve 0-63-bits delay using only 16 taps and in a way that permits power to be reduced considerably.
The maximum number of bits of delay in a segment and the maximum number of segments to be used in a shift register can be set for a particular application by adjusting the number of bits allocated to segment selection and to output stage selection. For example, if 3 bits were allocated to segment selection, instead of 2, up to 8 segments could be utilized instead of just 4. Further, if each segment contained a maximum of 32 or 8 delay increments, instead of 16, one would allocate 5 or 3 bits, respectively, to output phase selection instead of the 4 bits shown.
It has been found particularly advantageous to generate all clocks internal to the chip so that they coincide with the rising edge of the chip clock. All noise critical clocks provided external to the chip, are created on the falling edge of the chip clock.
All clocks in item 140 of FIG. 1 are programmable. That is, the division ratio used to obtain a particular clock rate from the chip clock can be programmed. Not only that, they can be programmed during the operation of the chip. The registers setting the dividers for the various clocks can be programmed over the bus using information received over a command line or interface. The arrangement for execution of a change in the programming for a particular clock occurs when a chip sync pulse occurs. This can occur, for example, at a 32 kHz rate.
By switching the programming of a clock during the sync pulse, the clock can be reprogrammed during operation without cause causing glitches in the data. Further, data interfacing among devices on the chip is easier when all clocks on the chip are synchronized.
Appendix A shows exemplary compilation tools for obtaining the content of ram1 and ram2 for the Sinc filter stage 2 and for converting bit codes generating from a perl script to DSP code.
Appendix B is matlab code utilized to generate mini-sinc impulse responses and calculates Sinc filter attenuation and rolloff.
Appendix C gives programming details for programming the Sinc2 filter.
Appendix D and Appendix E give exemplary code for the main program and the accumulate and output subroutines for the Sinc filters, respectively.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims and their equivalents.
Claims (14)
1. A programmable integrated circuit, comprising:
a. a bus;
b. a processor, connected to said bus, for performing digital filtering on digital signals;
c. a data interface, connected to said bus, for receiving external digital signals having respectively different characteristics for filtering by said processor, wherein said data interface provides an output selectively to one of two different sinc filters provided by said processor; and
d. a serial data output register, for receiving filtered digital signals from said processor and providing them to an output port.
2. The integrated circuit of claim 1 , further comprising at least one test modulator, connected to said bus, for generating a test signal having a controlled delay.
3. The integrated circuit of claim 2 , in which said at least one test modulator is programmable to selectively generate a test signal using different algorithms.
4. The integrated circuit of claim 1 , further comprising a serial control interface.
5. The integrated circuit of claim 1 further comprising a serial peripheral interface.
6. The integrated circuit of claim 1 , further comprising a general purpose Input/Output interface.
7. The integrated circuit of claim 1 , in which said processor is configured to provide programmable decimation and filtering.
8. The integrated circuit of claim 1 , in which separate power supplies are provided respectively to said data interface, said processor and to said serial data output register.
9. The integrated circuit of claim 1 , formed on an integrated circuit.
10. The integrated circuit of claim 9 , in which said integrated circuit includes a token input pin and a token output pin.
11. A plurality of programmable digital filters of claim 10 , serially connected from token output pin of one integrated circuit to token input pin of the next integrated circuit in which the token input pin of a first programmable digital filter is connected to a microcontroller and the token output pin of a last programmable digital filter is connected to said microcontroller.
12. A programmable integrated circuit, comprising:
a. a bus;
b. a processor, connected to said bus, for performing digital filtering on digital signals;
c. a data interface, connected to said bus, for receiving external digital signals having respectively different characteristics for filtering by said processor; and
d. a serial data output register, for receiving filtered digital signals from said processor and providing them to an output port, cells of the register not needed for delay operated in a reduced power mode in which power is removed from said cells not needed for delay during said reduced power mode.
13. A method of designing an integrated circuit, comprising the steps of:
a. providing for a bus;
b. providing for a processor, connected to said bus, for performing digital filtering on digital signals
c. providing for a data interface, connected to said bus, for receiving external digital signals having respectively different characteristics for filtering by said processor, wherein said data interface provides an output selectively to one of two different sinc filters provided by said processor; and
d. providing for a serial data output register, for receiving filtered digital signals from said processor and providing them to an output port.
14. A method of fabricating an integrated circuit, comprising the steps of:
a. providing a bus;
b. providing a processor, connected to said bus, for performing digital filtering on digital signals;
c. providing a data interface, connected to said bus, for receiving external digital signals having respectively different characteristics for filtering by said processor; and
d. providing a serial data output register, for receiving filtered digital signals from said processor and providing them to an output port, cells of the register not needed for delay operated in a reduced power mode in which power is removed from said cells not needed for delay during said reduced power mode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/803,349 US6920470B2 (en) | 2001-03-08 | 2001-03-08 | Signal processing integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/803,349 US6920470B2 (en) | 2001-03-08 | 2001-03-08 | Signal processing integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020129073A1 US20020129073A1 (en) | 2002-09-12 |
US6920470B2 true US6920470B2 (en) | 2005-07-19 |
Family
ID=25186305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/803,349 Expired - Lifetime US6920470B2 (en) | 2001-03-08 | 2001-03-08 | Signal processing integrated circuit |
Country Status (1)
Country | Link |
---|---|
US (1) | US6920470B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050149801A1 (en) * | 2002-12-27 | 2005-07-07 | Hideyuki Oshima | Semiconductor test device |
US20070050438A1 (en) * | 2005-08-31 | 2007-03-01 | Microchip Technology Incorporated | Programmable digital filter |
US20090271005A1 (en) * | 2008-04-25 | 2009-10-29 | Tannoy Limited | Control system |
US10216678B2 (en) | 2014-10-07 | 2019-02-26 | Infineon Technologies Ag | Serial peripheral interface daisy chain communication with an in-frame response |
US10310109B2 (en) | 2014-06-06 | 2019-06-04 | Austin Star Detonator Company | Method and apparatus for confirmation time break (CTB) determination and shotpoint in-situ recording in seismic electronic detonators |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8019035B2 (en) | 2003-08-05 | 2011-09-13 | Stmicroelectronics Nv | Noise shaped interpolator and decimator apparatus and method |
US9541658B2 (en) * | 2007-08-02 | 2017-01-10 | Westerngeco L. L. C. | Dynamically allocating different numbers of bits to windows of a series representing a seismic trace |
JP2009164786A (en) * | 2007-12-28 | 2009-07-23 | Nec Electronics Corp | Data transfer system and data transfer method |
US8959137B1 (en) | 2008-02-20 | 2015-02-17 | Altera Corporation | Implementing large multipliers in a programmable integrated circuit device |
US8484265B1 (en) * | 2010-03-04 | 2013-07-09 | Altera Corporation | Angular range reduction in an integrated circuit device |
US8510354B1 (en) | 2010-03-12 | 2013-08-13 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US8862650B2 (en) | 2010-06-25 | 2014-10-14 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US8589463B2 (en) | 2010-06-25 | 2013-11-19 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US9053045B1 (en) | 2011-09-16 | 2015-06-09 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US8949298B1 (en) | 2011-09-16 | 2015-02-03 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US9207909B1 (en) | 2012-11-26 | 2015-12-08 | Altera Corporation | Polynomial calculations optimized for programmable integrated circuit device structures |
US9189200B1 (en) | 2013-03-14 | 2015-11-17 | Altera Corporation | Multiple-precision processing block in a programmable integrated circuit device |
US9703574B2 (en) * | 2013-03-15 | 2017-07-11 | Micron Technology, Inc. | Overflow detection and correction in state machine engines |
US9348795B1 (en) | 2013-07-03 | 2016-05-24 | Altera Corporation | Programmable device using fixed and configurable logic to implement floating-point rounding |
US10942706B2 (en) | 2017-05-05 | 2021-03-09 | Intel Corporation | Implementation of floating-point trigonometric functions in an integrated circuit device |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6167415A (en) * | 1998-02-10 | 2000-12-26 | Lucent Technologies, Inc. | Recursive digital filter with reset |
US6321246B1 (en) * | 1998-09-16 | 2001-11-20 | Cirrus Logic, Inc. | Linear phase FIR sinc filter with multiplexing |
US6456219B1 (en) * | 2000-02-22 | 2002-09-24 | Texas Instruments Incorporated | Analog-to-digital converter including two-wire interface circuit |
US6539052B1 (en) * | 1997-11-03 | 2003-03-25 | Harris Corporation | System for accelerating the reconfiguration of a transceiver and method therefor |
US6546408B2 (en) * | 1998-09-16 | 2003-04-08 | Cirrus Logic, Inc. | Sinc filter using twisting symmetry |
US6593925B1 (en) * | 2000-06-22 | 2003-07-15 | Microsoft Corporation | Parameterized animation compression methods and arrangements |
-
2001
- 2001-03-08 US US09/803,349 patent/US6920470B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6539052B1 (en) * | 1997-11-03 | 2003-03-25 | Harris Corporation | System for accelerating the reconfiguration of a transceiver and method therefor |
US6167415A (en) * | 1998-02-10 | 2000-12-26 | Lucent Technologies, Inc. | Recursive digital filter with reset |
US6321246B1 (en) * | 1998-09-16 | 2001-11-20 | Cirrus Logic, Inc. | Linear phase FIR sinc filter with multiplexing |
US6546408B2 (en) * | 1998-09-16 | 2003-04-08 | Cirrus Logic, Inc. | Sinc filter using twisting symmetry |
US6456219B1 (en) * | 2000-02-22 | 2002-09-24 | Texas Instruments Incorporated | Analog-to-digital converter including two-wire interface circuit |
US6593925B1 (en) * | 2000-06-22 | 2003-07-15 | Microsoft Corporation | Parameterized animation compression methods and arrangements |
Non-Patent Citations (1)
Title |
---|
Emad et al., Decimation filters: low-power design and optimization, 1997, IEEE, pp. 850-853. * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050149801A1 (en) * | 2002-12-27 | 2005-07-07 | Hideyuki Oshima | Semiconductor test device |
US7078889B2 (en) * | 2002-12-27 | 2006-07-18 | Advantest Corp. | Semiconductor test apparatus for testing semiconductor device that produces output data by its internal clock timing |
US20070050438A1 (en) * | 2005-08-31 | 2007-03-01 | Microchip Technology Incorporated | Programmable digital filter |
US20090271005A1 (en) * | 2008-04-25 | 2009-10-29 | Tannoy Limited | Control system |
US8260442B2 (en) * | 2008-04-25 | 2012-09-04 | Tannoy Limited | Control system for a transducer array |
US10310109B2 (en) | 2014-06-06 | 2019-06-04 | Austin Star Detonator Company | Method and apparatus for confirmation time break (CTB) determination and shotpoint in-situ recording in seismic electronic detonators |
US10216678B2 (en) | 2014-10-07 | 2019-02-26 | Infineon Technologies Ag | Serial peripheral interface daisy chain communication with an in-frame response |
Also Published As
Publication number | Publication date |
---|---|
US20020129073A1 (en) | 2002-09-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6920470B2 (en) | Signal processing integrated circuit | |
US6321246B1 (en) | Linear phase FIR sinc filter with multiplexing | |
US7409417B2 (en) | Polyphase filter with optimized silicon area | |
US6546408B2 (en) | Sinc filter using twisting symmetry | |
EP0428326A1 (en) | Processor array system | |
JPH09135149A (en) | Wideband digital filtering method and filter using the method | |
US5721696A (en) | Method and system for performing an FIR filtering operation | |
US6594284B1 (en) | Network synchronization | |
US6317765B1 (en) | Sinc filter with selective decimation ratios | |
US5657263A (en) | Computer processor having a pipelined architecture which utilizes feedback and method of using same | |
KR100240158B1 (en) | Real time probe device for internals of signal processor | |
EP0285317A2 (en) | Phase coordinated multistage digital filter | |
GB2303009A (en) | Finite impulse response filter | |
US5479363A (en) | Programmable digital signal processor using switchable unit-delays for optimal hardware allocation | |
US6337636B1 (en) | System and techniques for seismic data acquisition | |
US20040225809A1 (en) | Integrated circuit arrangement for multiple-sensor types with a programmable interface for selecting a digital filter input signal | |
EP0285316A2 (en) | Programmable multistage digital filter | |
WO1997008609A1 (en) | Computer processor having a pipelined architecture and method of using same | |
US6434213B1 (en) | Low-power low-area shift register | |
US20080204072A1 (en) | Programmable Logic Device | |
US20020126029A1 (en) | Programmable test modulator for selectively generating test signals of delta-sigma order N | |
US5790439A (en) | Reduced test time finite impulse response digital filter | |
US6085209A (en) | Method and system for performing an IIR filtering operation | |
US6281718B1 (en) | Noise management using a switched converter | |
Valls et al. | Fast FPGA-based pipelined digit-serial/parallel multipliers |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CIRRUS LOGIC, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PAGE, JOEL;GRALE, TRENTON JOHN;YE, ZHUAN;AND OTHERS;REEL/FRAME:011802/0457;SIGNING DATES FROM 20010430 TO 20010504 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |