US6884713B2 - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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Publication number
US6884713B2
US6884713B2 US10/608,082 US60808203A US6884713B2 US 6884713 B2 US6884713 B2 US 6884713B2 US 60808203 A US60808203 A US 60808203A US 6884713 B2 US6884713 B2 US 6884713B2
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Prior art keywords
metal line
via contact
conductive layer
contact plug
lower metal
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US10/608,082
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US20040137719A1 (en
Inventor
Won Hwa Jin
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JIN, WON HWA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention generally relates to methods for forming metal line of semiconductor device, and more specifically, to methods for forming metal line of semiconductor device wherein via contact plug is formed without the deposition process of Ti/TiN liner layer and conductive layer filling a via contact hole so that the formation processes of a conductive layer for lower metal line and a conductive layer for via contact plug are performed successively without interruption to minimize the contact resistance between the lower metal line and the via contact plug, thereby simplifying the manufacturing process and improving productivity, characteristics and reliability of the device.
  • conductive lines of semiconductor devices used for electrical connection between devices and between a device and an external circuit is formed by filling a contact hole and via hole with conductive material and performing subsequent processes.
  • Metal lines are used where low resistance is required.
  • Aluminum alloys formed by adding silicon, copper or both of silicon and copper to aluminum, are used as materials for the metal lines for its low resistivity and excellent process characteristics.
  • FIGS. 1 a through 1 g are cross-sectional diagrams illustrating a conventional method for forming metal line of semiconductor device.
  • a lower metal line 11 is formed on a semiconductor substrate(not shown).
  • the lower metal line 11 is an aluminum alloy film, and comprises Ti layers or Ti/TiN layers thereon and thereunder.
  • a photoresist film pattern 15 is then formed on the interlayer insulating film 13 .
  • the photoresist film pattern 15 is formed by exposure and development process using metal line contact mask(not shown) for forming a via contact hole.
  • the interlayer insulating film 13 is etched using the photoresist film pattern 15 as a mask to form a via contact hole 17 exposing the lower metal line 11 .
  • the photoresist film pattern 15 is then removed, and Ti/TiN liner layer 19 , which is a bonding layer/diffusion barrier layer, is formed on the entire surface including the inner surface of the via contact hole 17 .
  • a tungsten layer 21 filling the via contact hole 17 is formed on the entire surface.
  • the entire surface is planarized using the interlayer insulating film 13 as an etch stop layer to form a via contact plug 21 filling the via contact hole 17 .
  • a conductive layer 23 for upper metal line is formed to be electrically connected to the via contact plug 21 .
  • the conductive layer 23 comprises a stacked structure of a lower Ti/TiN film, a main conductive layer for metal line, and an upper Ti/TiN film.
  • the lower Ti/TiN film prevents the main conductive layer from reacting with the interlayer insulating film 13 which is a oxide film when the main conductive layer is an aluminum alloy or a tungsten alloy.
  • the lower Ti/TiN film also allows uniform deposition of the aluminum alloy.
  • the upper Ti/TiN film serves as an anti-reflective film and improves characteristics of electro-migration.
  • a photoresist film patter 25 is formed on the conductive layer 23 .
  • the photoresist film pattern 25 is formed by exposure and development process using an upper metal line mask(not shown).
  • the conductive layer 23 is etched using the photoresist film pattern 25 as a mask to form an upper metal line electrically connected to the lower metal line 11 .
  • FIGS. 2 a through 2 c are SEM photographs illustrating a metal line manufactured in accordance with the conventional method.
  • FIG. 2 a illustrates a multi-layer metal line.
  • FIG. 2 b illustrates a portion of the multi-layer metal line of FIG. 2 a around the via contact plug, where seams are generated due to unstable deposition of the Ti/TiN liner film 19 .
  • FIG. 2 c illustrates the tungsten layer 21 poorly deposited on the unstable Ti/TiN liner film 19 .
  • a forming metal line of semiconductor device comprising the steps of: (a) sequentially forming a conductive layer for lower metal line and a conductive layer for via contact plug on a planarized first interlayer insulating film having a contact plug; (b) etching the conductive layer for via contact plug and the conductive layer for lower metal line using lower metal line mask to form a lower metal line; (c) forming a second interlayer insulating film on the entire surface; (d) etching the second interlayer insulating film and the conductive layer for via contact plug using a via contact mask to form a via contact plug; (e) forming a third interlayer insulating film on the entire surface; (f) performing a planarization process to expose a upper surface of the via contact plug; and (g) forming an upper metal line electrically connected to the via contact plug.
  • FIGS. 1 a through 1 g are cross-sectional diagrams illustrating a conventional method for forming metal line of semiconductor device.
  • FIGS. 2 a through 2 c are SEM photographs illustrating a metal line manufactured in accordance with the conventional method.
  • FIGS. 3 a through 3 i are cross-sectional diagrams illustrating method for forming metal line of semiconductor device in accordance with the present invention.
  • FIGS. 3 a through 3 i are cross-sectional diagrams illustrating a method for forming metal line of semiconductor device in accordance with the present invention.
  • a first interlayer insulating film 43 is formed on the semiconductor substrate 41 having a device isolation film(not shown), a wordline(not shown), a bitline(not shown), and a capacitor(not shown) thereon. Thereafter, the first interlayer insulating film 43 is etched using lower metal line contact mask(not shown) to form a contact hole. The contact hole is then filled to form a contact plug 45 for lower metal line.
  • a conductive layer for lower metal line electrically connected to the contact plug 45 and a conductive layer 53 for via contact plug are sequentially formed on the entire surface.
  • the conductive layer for lower metal line comprises a stacked structure of a first Ti/TiN layer 47 , a metal layer 49 and a second Ti/TiN layer 51 .
  • the metal layer 49 comprises aluminum, copper, tungsten, cobalt, silicon, or combinations thereof.
  • the conductive layer for via contact plug comprises aluminum, copper, tungsten, cobalt, silicon, or combinations thereof.
  • the materials for the conductive layer 53 are selected to have etch selectivity over the second Ti/TiN layer 51 so that the second Ti/TiN layer 51 serves as an etch stop film in the subsequent etch process of the conductive layer 53 .
  • the conductive layer 53 for via contact plug and the conductive layer for lower metal line are etched using lower metal line mask(not shown), which covers a predetermined region of the conductive layer 53 where lower metal line is to be formed, to form a lower metal line 55 .
  • a second interlayer insulating film 57 is deposited on the entire surface.
  • a via contact plug 59 is formed by etching the second interlayer insulating film 57 and the conductive layer 53 for via contact plug using a mask(not shown) which exposes a portion of the second interlayer insulating film above the metal line 55 except a predetermined region where the via contact plug 59 is to be formed.
  • the via contact plug 59 can also be formed by performing a double-exposure using the lower metal line mask(not shown) and a via contact mask and then etching the double-exposed portion of the second interlayer insulating film 57 and the conductive layer 53 for via contact plug.
  • a third interlayer insulating film 61 is deposited on the entire surface.
  • a planarization process is performed to expose a top surface of the via contact plug 59 .
  • the planarization process is an etch-back process or a CMP(Chemical Mechanical Polishing) process.
  • a conductive layer 63 for upper metal line electrically connected to the via contact plug 59 is formed.
  • the conductive layer 63 for upper metal line comprises the same materials as those of the lower metal line 55 .
  • the conductive layer 63 for upper metal line is etched using upper metal line mask(not shown) to form an upper metal line 65 .
  • the above-describe method in accordance with the present invention can be applied to formation of a metal line having a structure of three or more layers, in addition to upper and lower metal lines.
  • the methods in accordance with the present invention provides simplified manufacturing process and improved productivity, characteristics and reliability by forming the via contact plug without the deposition process of Ti/TiN layer and conductive layer filling a via contact hole so that the formation processes of a conductive layer for lower metal line and a conductive layer for via contact plug are performed successively without interruption to minimize the contact resistance between the lower metal line and the via contact plug.

Abstract

Methods for forming metal line of semiconductor device wherein via contact plug is formed without the deposition process of Ti/TiN liner layer and conductive layer filling a via contact hole so that the formation processes of a conductive layer for lower metal line and a conductive layer for via contact plug can be performed successively without interruption is disclosed. The method comprises the steps of: (a) sequentially forming a conductive layer for lower metal line and a conductive layer for via contact plug on a planarized first interlayer insulating film having a contact plug; (b) etching the conductive layer for via contact plug and the conductive layer for lower metal line using lower metal line mask to form a lower metal line; (c) forming a second interlayer insulating film on the entire surface; (d) etching the second interlayer insulating film and the conductive layer for via contact plug using a via contact mask to form a via contact plug; (e) forming a third interlayer insulating film on the entire surface; (f) performing a planarization process to expose a upper surface of the via contact plug; and (g) forming an upper metal line electrically connected to the via contact plug.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to methods for forming metal line of semiconductor device, and more specifically, to methods for forming metal line of semiconductor device wherein via contact plug is formed without the deposition process of Ti/TiN liner layer and conductive layer filling a via contact hole so that the formation processes of a conductive layer for lower metal line and a conductive layer for via contact plug are performed successively without interruption to minimize the contact resistance between the lower metal line and the via contact plug, thereby simplifying the manufacturing process and improving productivity, characteristics and reliability of the device.
2. Description of the Prior Art
Generally, conductive lines of semiconductor devices used for electrical connection between devices and between a device and an external circuit is formed by filling a contact hole and via hole with conductive material and performing subsequent processes.
Metal lines are used where low resistance is required. Aluminum alloys, formed by adding silicon, copper or both of silicon and copper to aluminum, are used as materials for the metal lines for its low resistivity and excellent process characteristics.
FIGS. 1 a through 1 g are cross-sectional diagrams illustrating a conventional method for forming metal line of semiconductor device.
Referring to FIG. 1 a, a lower metal line 11 is formed on a semiconductor substrate(not shown). The lower metal line 11 is an aluminum alloy film, and comprises Ti layers or Ti/TiN layers thereon and thereunder.
Thereafter, a planarized interlayer insulating film 13 formed on the entire surface. A photoresist film pattern 15 is then formed on the interlayer insulating film 13. The photoresist film pattern 15 is formed by exposure and development process using metal line contact mask(not shown) for forming a via contact hole.
Referring to FIG. 1 b, the interlayer insulating film 13 is etched using the photoresist film pattern 15 as a mask to form a via contact hole 17 exposing the lower metal line 11. The photoresist film pattern 15 is then removed, and Ti/TiN liner layer 19, which is a bonding layer/diffusion barrier layer, is formed on the entire surface including the inner surface of the via contact hole 17.
Referring to FIG. 1 c, a tungsten layer 21 filling the via contact hole 17 is formed on the entire surface.
Referring to FIG. 1 d, the entire surface is planarized using the interlayer insulating film 13 as an etch stop layer to form a via contact plug 21 filling the via contact hole 17.
Referring to FIG. 1 e, a conductive layer 23 for upper metal line is formed to be electrically connected to the via contact plug 21. The conductive layer 23 comprises a stacked structure of a lower Ti/TiN film, a main conductive layer for metal line, and an upper Ti/TiN film. The lower Ti/TiN film prevents the main conductive layer from reacting with the interlayer insulating film 13 which is a oxide film when the main conductive layer is an aluminum alloy or a tungsten alloy. The lower Ti/TiN film also allows uniform deposition of the aluminum alloy. The upper Ti/TiN film serves as an anti-reflective film and improves characteristics of electro-migration.
Referring to FIG. 1 f, a photoresist film patter 25 is formed on the conductive layer 23. The photoresist film pattern 25 is formed by exposure and development process using an upper metal line mask(not shown).
Referring to FIG. 1 g, the conductive layer 23 is etched using the photoresist film pattern 25 as a mask to form an upper metal line electrically connected to the lower metal line 11.
FIGS. 2 a through 2 c are SEM photographs illustrating a metal line manufactured in accordance with the conventional method.
FIG. 2 a illustrates a multi-layer metal line. FIG. 2 b illustrates a portion of the multi-layer metal line of FIG. 2 a around the via contact plug, where seams are generated due to unstable deposition of the Ti/TiN liner film 19.
FIG. 2 c illustrates the tungsten layer 21 poorly deposited on the unstable Ti/TiN liner film 19.
As described above, in the conventional method for manufacturing metal lines, seams generated during the formation process of via contact plug, poor quality tungsten film and high contact resistance degrades the characteristics of the device. Moreover, the manufacturing method is complex so that undesired impurities such as particles, which degrades the characteristics and reliability of the device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide methods for forming metal line of semiconductor device wherein via contact plug is formed without the deposition process of Ti/TiN liner layer and conductive layer filling a via contact hole so that the formation processes of a conductive layer for lower metal line and a conductive layer for via contact plug are performed successively without interruption to minimize the contact resistance between the lower metal line and the via contact plug, thereby simplifying the manufacturing process and improving productivity, characteristics and reliability of the device.
In order to achieve the above object of the present invention, there is provided a forming metal line of semiconductor device, comprising the steps of: (a) sequentially forming a conductive layer for lower metal line and a conductive layer for via contact plug on a planarized first interlayer insulating film having a contact plug; (b) etching the conductive layer for via contact plug and the conductive layer for lower metal line using lower metal line mask to form a lower metal line; (c) forming a second interlayer insulating film on the entire surface; (d) etching the second interlayer insulating film and the conductive layer for via contact plug using a via contact mask to form a via contact plug; (e) forming a third interlayer insulating film on the entire surface; (f) performing a planarization process to expose a upper surface of the via contact plug; and (g) forming an upper metal line electrically connected to the via contact plug.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 a through 1 g are cross-sectional diagrams illustrating a conventional method for forming metal line of semiconductor device.
FIGS. 2 a through 2 c are SEM photographs illustrating a metal line manufactured in accordance with the conventional method.
FIGS. 3 a through 3 i are cross-sectional diagrams illustrating method for forming metal line of semiconductor device in accordance with the present invention.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention will be explained in detail referring to the accompanying drawings.
FIGS. 3 a through 3 i are cross-sectional diagrams illustrating a method for forming metal line of semiconductor device in accordance with the present invention.
Referring to FIG. 3 a, a first interlayer insulating film 43 is formed on the semiconductor substrate 41 having a device isolation film(not shown), a wordline(not shown), a bitline(not shown), and a capacitor(not shown) thereon. Thereafter, the first interlayer insulating film 43 is etched using lower metal line contact mask(not shown) to form a contact hole. The contact hole is then filled to form a contact plug 45 for lower metal line.
Referring to FIG. 3 b, a conductive layer for lower metal line electrically connected to the contact plug 45 and a conductive layer 53 for via contact plug are sequentially formed on the entire surface. The conductive layer for lower metal line comprises a stacked structure of a first Ti/TiN layer 47, a metal layer 49 and a second Ti/TiN layer 51. Preferably, the metal layer 49 comprises aluminum, copper, tungsten, cobalt, silicon, or combinations thereof.
Preferably, The conductive layer for via contact plug comprises aluminum, copper, tungsten, cobalt, silicon, or combinations thereof. The materials for the conductive layer 53 are selected to have etch selectivity over the second Ti/TiN layer 51 so that the second Ti/TiN layer 51 serves as an etch stop film in the subsequent etch process of the conductive layer 53.
Referring to FIG. 3 c, the conductive layer 53 for via contact plug and the conductive layer for lower metal line are etched using lower metal line mask(not shown), which covers a predetermined region of the conductive layer 53 where lower metal line is to be formed, to form a lower metal line 55.
Referring to FIG. 3 d, a second interlayer insulating film 57 is deposited on the entire surface.
Referring to FIG. 3 e, a via contact plug 59 is formed by etching the second interlayer insulating film 57 and the conductive layer 53 for via contact plug using a mask(not shown) which exposes a portion of the second interlayer insulating film above the metal line 55 except a predetermined region where the via contact plug 59 is to be formed. The via contact plug 59 can also be formed by performing a double-exposure using the lower metal line mask(not shown) and a via contact mask and then etching the double-exposed portion of the second interlayer insulating film 57 and the conductive layer 53 for via contact plug.
Referring to FIG. 3 f, a third interlayer insulating film 61 is deposited on the entire surface.
Referring to FIG. 3 g, a planarization process is performed to expose a top surface of the via contact plug 59. Preferably, the planarization process is an etch-back process or a CMP(Chemical Mechanical Polishing) process.
Referring to FIG. 3 h, a conductive layer 63 for upper metal line electrically connected to the via contact plug 59 is formed. Preferably, the conductive layer 63 for upper metal line comprises the same materials as those of the lower metal line 55.
Referring to FIG. 3 i, the conductive layer 63 for upper metal line is etched using upper metal line mask(not shown) to form an upper metal line 65.
The above-describe method in accordance with the present invention can be applied to formation of a metal line having a structure of three or more layers, in addition to upper and lower metal lines.
As discussed earlier, the methods in accordance with the present invention provides simplified manufacturing process and improved productivity, characteristics and reliability by forming the via contact plug without the deposition process of Ti/TiN layer and conductive layer filling a via contact hole so that the formation processes of a conductive layer for lower metal line and a conductive layer for via contact plug are performed successively without interruption to minimize the contact resistance between the lower metal line and the via contact plug.

Claims (5)

1. A method for forming metal line of semiconductor device, comprising the steps of:
(a) sequentially forming a conductive layer for lower metal line and a conductive layer for via contact plug on a planarized first interlayer insulating film having a contact plug;
(b) etching the conductive layer for via contact plug and the conductive layer for lower metal line using a lower metal line mask to form a lower metal line;
(c) forming a second interlayer insulating film on the entire surface;
(d) etching the second interlayer insulating film and the conductive layer for via contact plug using a via contact mask to form a via contact plug;
(e) forming a third interlayer insulating film on the entire surface;
(f) performing a planarization process to expose a upper surface of the via contact plug; and
(g) forming an upper metal line electrically connected to the via contact plug.
2. The method according to claim 1, wherein the conductive layer for lower metal line, the conductive layer for via contact plug and the upper metal line are respectively selected from the group consisting of aluminum layer, copper layer, tungsten layer, cobalt layer, silicon layer, and combinations thereof.
3. The method according to claim 1, wherein the via contact mask exposes a portion of the second interlayer insulating film above the lower metal line except a predetermined region where the via contact plug is to be formed.
4. The method according to claim 1, wherein the step (d) utilizes difference in etch selectivity between the conductive layer for lower metal line and the conductive layer for via contact plug.
5. The method according to claim 1, wherein the planarization process is an etch-back process or a CMP process.
US10/608,082 2002-12-31 2003-06-30 Method for forming metal line of semiconductor device Expired - Fee Related US6884713B2 (en)

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KR1020020088117A KR20040061817A (en) 2002-12-31 2002-12-31 A method for forming a metal line of a semiconductor device

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KR20050070794A (en) * 2003-12-31 2005-07-07 동부아남반도체 주식회사 Method for fabricating metal interconnect of semiconductor device
KR100571416B1 (en) * 2003-12-31 2006-04-14 동부아남반도체 주식회사 Method of forming multi-layered metal wiring of semiconductor device
US7361585B2 (en) * 2004-12-23 2008-04-22 Advantech Global, Ltd System for and method of planarizing the contact region of a via by use of a continuous inline vacuum deposition
US7268431B2 (en) * 2004-12-30 2007-09-11 Advantech Global, Ltd System for and method of forming via holes by use of selective plasma etching in a continuous inline shadow mask deposition process
US7132361B2 (en) * 2004-12-23 2006-11-07 Advantech Global, Ltd System for and method of forming via holes by multiple deposition events in a continuous inline shadow mask deposition process
CN110571189B (en) * 2018-06-05 2022-04-29 中芯国际集成电路制造(上海)有限公司 Conductive plug and forming method thereof and integrated circuit
EP4050644A1 (en) * 2021-02-24 2022-08-31 Imec VZW A method for forming an interconnect structure

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US20040137719A1 (en) 2004-07-15

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