US6864177B2 - Method for manufacturing metal line contact plug of semiconductor device - Google Patents
Method for manufacturing metal line contact plug of semiconductor device Download PDFInfo
- Publication number
- US6864177B2 US6864177B2 US10/329,938 US32993802A US6864177B2 US 6864177 B2 US6864177 B2 US 6864177B2 US 32993802 A US32993802 A US 32993802A US 6864177 B2 US6864177 B2 US 6864177B2
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- US
- United States
- Prior art keywords
- slurry solution
- insulating film
- line contact
- metal
- metal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09G—POLISHING COMPOSITIONS; SKI WAXES
- C09G1/00—Polishing compositions
- C09G1/02—Polishing compositions containing abrasives or grinding agents
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Definitions
- a method for forming a metal line contact plug of a semiconductor device includes performing Chemical Mechanical Polishing (hereinafter, referred to as ‘CMP’) processes using (1) a first slurry solution having a high etching selectivity of metal/insulating film and (2) a second slurry solution having a low etching selectivity of metal/insulating film, thereby easily separating a metal line contact plug.
- CMP Chemical Mechanical Polishing
- a device can comprise about 8,000,000 transistors per cm 2 .
- metal lines of high quality which enable devices to be connected are required for high integration.
- Such multi-layered lines can be embodied by efficiently planarizing dielectrics inserted between metal lines.
- CMP processes have been developed.
- materials which need to be removed are chemically eliminated by using chemical materials which have good reactivity in CMP slurries.
- the wafer surface is polished mechanically with ultrafine abrasives.
- a CMP process is performed by injecting a liquid slurry between the top surface of a wafer and a rotating elastic pad.
- a noble line technique should be required for the multi-layered lines by using a metal CMP technique.
- a slurry used in the metal CMP process includes oxidizers for forming oxide films on the surface of metal and abrasives. When a metal is removed by a CMP process using the slurry, the metal surface is oxidized by oxidizers, and then the oxidized portion is mechanically polished and repeatedly removed by abrasives contained in the slurry.
- FIG. 1 a is a top plan view after forming a bit line pattern.
- FIG. 1 b is a top plan view after etching a metal line contact plug.
- FIGS. 2 a through 2 d illustrate schematically conventional methods for manufacturing metal line contact plugs of semiconductor devices.
- FIG. 2 a is a diagram illustrating a condition wherein an interlayer insulating film is stacked on an A-A′ cross section of FIG. 1 a .
- Bit lines 13 with mask insulating films 15 stacked thereon are formed on a semiconductor substrate 11 .
- the mask insulating films 15 are composed of nitride films with a thickness t 1 .
- an interlayer insulating film 17 is formed on top surface of the resultant structure.
- the interlayer insulating film 17 is composed of an oxide film (see FIG. 2 a ).
- FIG. 2 b is a diagram illustrating a B-B′ cross section of FIG. 1 b .
- a metal line contact hole 19 is formed by etching the interlayer insulating film 17 using a metal line contact mask as an etching mask.
- a region “C” shown in FIG. 1 b represents a region wherein the metal line contact hole 19 is formed by etching the interlayer insulating film 17 while a region “D” represents a region wherein the metal line contact hole 19 is not formed.
- an oxide film spacers 21 are formed along the sidewalls of the metal line contact hole 19 and bit lines 13 are formed by blanket etching the deposited oxide film.
- the thickness of the mask insulating films 15 on the bit lines 13 formed in the metal line contact hole 19 decreases to t2 due to etching processes to form the metal line contact hole 19 and to form the oxide film spacer 21 (see FIG. 2 b ).
- a metal layer 23 is stacked on top surface of the resultant structure.
- the metal layer 23 has step coverage of t3 in the metal line contact hole 19 and of t4 from the mask insulating film 15 (see FIG. 2 c ).
- a metal line contact plug 25 is formed by removing portions of the metal layer 23 , the interlayer insulating film 17 and the predetermined thickness of the mask insulating film 15 using a CMP process.
- a depth of t4 should be polished using a slurry to remove portions of the metal layer 23 .
- a polishing speed should be similar between films to remove the above multilayered films.
- a polishing speed of metal layers is over 20 times faster than that of oxide films when a CMP process is performed using conventional CMP slurry for metal to remove a metal.
- a metal line contact plug is not separated (see FIG. 2 d ), and an equipment vibration phenomenon is generated, resulting in deteriorating stability of the process.
- a method for manufacturing a metal line contact plug of a semiconductor device which comprises performing a two step CMP process in which a metal line contact plug is easily separated and a polishing speed of peripheral circuit regions is decreased, thereby improving stability of the process.
- FIG. 1 a is a top plan view after formation of a bit line pattern
- FIG. 1 b is a top plan view after etching of a metal line contact plug
- FIGS. 2 a through 2 d illustrate, schematically, conventional methods of manufacturing metal line contact plugs of semiconductor devices.
- FIGS. 3 a through 3 e illustrate, schematically, disclosed methods for manufacturing metal line contact plugs of semiconductor devices in accordance with this disclosure.
- a disclosed method for manufacturing a metal line contact plug of a semiconductor device by a CMP process comprises (a) performing a first CMP process using a first slurry solution, the first slurry solution comprising 1 to 20 wt % of abrasive, 0.1 to 15 wt % of oxidizer and 0.01 to 10 wt % of complexing agent based on the total weight of the first slurry solution respectively, and having an etching selectivity of more than 10 for a metal/insulating film and a pH ranging from 2 to 9; and (b) performing a second CMP process using a second slurry solution, the second slurry solution comprising 5 to 30 wt % of abrasive and 0.01 to 5 wt % of oxidizer based on the total weight of the second slurry solution respectively, and having an etching selectivity of less than 3 in the metal/insulating film and a pH ranging from 6 to 12 to easily separate a metal contact plug.
- a disclosed method for manufacturing a metal line contact plug of a semiconductor device comprises:
- the insulating film is an oxide or a nitride film.
- FIGS. 3 a through 3 e illustrate methods for manufacturing a metal line contact plug of semiconductor devices.
- FIG. 3 a is a diagram illustrating a condition wherein an interlayer insulating film is stacked on an A-A′ cross section of FIG. 1 a .
- Bit lines 103 whereon mask insulating patterns 105 are stacked are formed on a semiconductor substrate 101 .
- the bit lines 103 are formed of tungsten, and Ti/TiN films as a diffusion barrier film disposed on the lower portion of the bit lines 103 (not shown).
- the Ti/TiN films are formed by a chemical vapor deposition method using TiCl 4 as a source.
- the mask insulating films 105 are formed of a nitride film at a temperature ranging from about 500 to about 600° C. by a plasma chemical deposition method, and its thickness is indicated as t 1 .
- an interlayer insulating film 107 is formed on top surface of the resultant structure.
- the interlayer insulating film 107 is formed of an oxide film (see FIG. 3 a ).
- FIG. 3 b is a B-B′ cross section of FIG. 1 b .
- a metal line contact hole 109 is formed by etching the interlayer insulating film 107 using a metal line contact mask as an etching mask.
- an oxide film spacer 111 is formed at sidewalls of the metal line contact hole 109 and the bit lines 103 by depositing a predetermined thickness of oxide film on top surface and then blanket etching it.
- the thickness of the mask insulating film 105 on the bit line 103 formed in the metal line contact hole 109 decreases to t2 due to the etching processes to form the metal line contact hole 109 and to form the oxide film spacer 111 (see FIG. 3 b ).
- a metal layer 113 is then deposited on top surface.
- the metal layer 113 consisting of TiN is deposited using an atomic layer deposition method has step coverage of t3 in the metal line contact hole 109 and of t4 from the mask insulating pattern 105 .
- a first CMP process is performed on the metal layer 113 , the interlayer insulating film 107 and the predetermined thickness of the mask insulating film 105 , using (1) a first slurry solution having etching selectivity of more than 10 for metal/insulating film and a pH ranging from 2 to 9.
- a second CMP process is performed on the metal layer 113 , the interlayer insulating film 107 and the predetermined thickness of the mask insulating film 105 , using (2) a second slurry solution having etching selectivity of less than 3 for metal/insulating film and a pH ranging from 6 to 12.
- the first slurry solution comprises an abrasive in an amount ranging from 1 to 20 wt % of the slurry, an oxidizer in an amount ranging from 0.1 to 15 wt % of the slurry and a complexing agent in an amount ranging from 0.01 to 10 wt % of the slurry
- the second slurry solution comprises an abrasive in an amount ranging from 5 to 30 wt % of the slurry and an oxidizer in an amount ranging from 0.01 to 5 wt % of the slurry.
- the first slurry solution preferably comprises SiO 2 , Al 2 O 3 , MnO 2 or mixtures thereof as the abrasive, H 2 O 2 , H 5 IO 6 , FeNO 3 or mixtures thereof as the oxidizer and citric acid, tartaric acid, succinic acid, malic acid, maleic acid, fumaric acid, malonic acid, EDTA(ethylene diamine tetra acetate), glycolic acid, salts thereof or mixtures thereof as the complexing agent.
- the first slurry solution preferably comprises the abrasive in an amount ranging from 5 to 10 wt % of the slurry, the oxidizer in an amount ranging from 5 to 10 wt % of the slurry and the complexing agent in an amount ranging from 0.1 to 1 wt % of the slurry.
- the pH of the first slurry solution ranges from 4 to 7.
- the second slurry solution preferably comprises SiO 2 , Al 2 O 3 , MnO 2 or mixtures thereof as the abrasive and H 2 O 2 , H 5 IO 6 , FeNO 3 or mixtures thereof as the oxidizer.
- the second slurry solution preferably comprises the abrasive in an amount ranging from 10 to 25 wt % of the slurry and the oxidizer in an amount ranging from 0.1 to 3 wt % of the slurry.
- the pH of the second slurry solution ranges from 8 to 10 and the second slurry solution further comprises KOH, NH 4 OH, Na 2 CO 3 or mixtures thereof as pH control agent.
- the abrasive of the first and the second slurries has the size ranging from 50 to 300 nm.
- a metal line contact plug 113 a wherein the metal layer 113 is more polished than the interlayer insulating film 107 and the mask insulating film 105 is formed via the first CMP process (see FIG. 3 d ). Then, a metal line contact plug 113 b wherein a region P 1 and a region P 2 are completely separated is formed via the second CMP process (see FIG. 3 e ).
- the interlayer insulating film 107 and the metal layer 113 are polished at a thickness of more than t3 ( FIG. 3 c ) via the first CMP process. Then, the mask insulating film 105 , the interlayer insulating film 107 and the metal layer 113 are polished at a thickness of more than t4 via the second CMP process. As a result, the thickness of the mask insulating film 105 above the bit line 103 decreases to t 5 ( FIG. 3 c ) smaller than t2 ( FIG. 3 b ).
- the CMP process is performed in two steps to remove a top portion of metal layer and then separate a metal line contact plug, thereby preventing a phenomenon that a metal line contact plug is not separated well because a metal layer having a portion with a low step coverage is not removed.
- a metal line contact plug is manufactured by performing a two step CMP process using (1) a first slurry solution having high etching selectivity of metal/insulating film and (2) a second slurry solution having low etching selectivity of metal/insulating.
- a metal line contact plug is not separated well because a metal layer having a portion with a low step coverage is not removed.
- the disclosed stabilized CMP process can minimize dependency on CMP equipment and ultimately improve operation characteristics and reliability of the resultant semiconductor devices.
Abstract
Description
-
- forming a stack pattern of a bit line and a mask insulating film on a semiconductor substrate;
- forming an interlayer insulating film on the entire surface of the resultant structure;
- forming a metal line contact hole by defining the metal line contact hole region and selectively etching the interlayer insulating film to expose the semiconductor substrate and the stack patterns present in the contact hole region;
- forming oxide film spacers on sidewalls of the metal line contact hole and stack patterns in the metal line contact hole;
- depositing a metal layer in the metal line contact hole and on remaining portions of the interlayer insulating film; and
- performing a two step of CMP process onto the entire surface of the resultant structure until exposing the mask insulating film of the stack pattern to form a metal line contact plug contact to the semiconductor substrate, wherein the CMP process comprises: (a) performing a first CMP process using a first slurry solution having an etching selectivity of more than 10 for metal/insulating film and a pH ranging from 2 to 9; and (b) performing a second CMP process using a second slurry solution having an etching selectivity of less than 3 for metal/insulating film and a pH ranging from 6 to 12, wherein the first slurry solution comprises 1 to 20 wt % of abrasive, 0.1 to 15 wt % of oxidizer and 0.001 to 10 wt % of complexing agent based on the total weight of the first slurry solution, and wherein the second slurry solution comprises 5 to 30 wt % of abrasive and 0.01 to 5 wt % of oxidizer based on the total weight of the second slurry solution.
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR2001-84904 | 2001-12-26 | ||
KR10-2001-0084904A KR100442962B1 (en) | 2001-12-26 | 2001-12-26 | Method for manufacturing of metal line contact plug of semiconductor device |
Publications (2)
Publication Number | Publication Date |
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US20030119324A1 US20030119324A1 (en) | 2003-06-26 |
US6864177B2 true US6864177B2 (en) | 2005-03-08 |
Family
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US10/329,938 Expired - Fee Related US6864177B2 (en) | 2001-12-26 | 2002-12-26 | Method for manufacturing metal line contact plug of semiconductor device |
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US (1) | US6864177B2 (en) |
KR (1) | KR100442962B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060003586A1 (en) * | 2004-06-30 | 2006-01-05 | Matrix Semiconductor, Inc. | Nonselective unpatterned etchback to expose buried patterned features |
US20080268557A1 (en) * | 2007-04-24 | 2008-10-30 | Nanya Technology Corp. | Method for measuring a thin film thickness |
US20100159698A1 (en) * | 2008-12-23 | 2010-06-24 | Dupoint Air Products Nanomaterials Llc | Combination, Method, and Composition for Chemical Mechanical Planarization of A Tungsten-Containing Substrate |
US8921226B2 (en) | 2013-01-14 | 2014-12-30 | United Microelectronics Corp. | Method of forming semiconductor structure having contact plug |
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KR100583118B1 (en) * | 2003-12-19 | 2006-05-23 | 주식회사 하이닉스반도체 | Method for Forming Capacitor of Semiconductor Device |
CN100429043C (en) * | 2003-12-29 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Chemical and mechanical grinding method for aluminium |
KR101025926B1 (en) * | 2004-02-19 | 2011-03-30 | 매그나칩 반도체 유한회사 | Method for manufacturing EEPROM cell |
US7351662B2 (en) * | 2005-01-07 | 2008-04-01 | Dupont Air Products Nanomaterials Llc | Composition and associated method for catalyzing removal rates of dielectric films during chemical mechanical planarization |
US7521351B2 (en) * | 2005-06-30 | 2009-04-21 | Infineon Technologies Ag | Method for forming a semiconductor product and semiconductor product |
CN102371534B (en) * | 2010-08-24 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method for surface of wafer |
CN104979277B (en) * | 2014-04-11 | 2019-06-14 | 中国科学院微电子研究所 | A kind of process of the chemical-mechanical planarization of the device of 40nm or less size |
US10510601B2 (en) * | 2017-09-28 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing metal plug corrosion and device |
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KR100546153B1 (en) * | 1998-12-28 | 2006-03-31 | 주식회사 하이닉스반도체 | Contact Forming Method of Semiconductor Device |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060003586A1 (en) * | 2004-06-30 | 2006-01-05 | Matrix Semiconductor, Inc. | Nonselective unpatterned etchback to expose buried patterned features |
US7307013B2 (en) * | 2004-06-30 | 2007-12-11 | Sandisk 3D Llc | Nonselective unpatterned etchback to expose buried patterned features |
US20080268557A1 (en) * | 2007-04-24 | 2008-10-30 | Nanya Technology Corp. | Method for measuring a thin film thickness |
US20100159698A1 (en) * | 2008-12-23 | 2010-06-24 | Dupoint Air Products Nanomaterials Llc | Combination, Method, and Composition for Chemical Mechanical Planarization of A Tungsten-Containing Substrate |
US8506831B2 (en) * | 2008-12-23 | 2013-08-13 | Air Products And Chemicals, Inc. | Combination, method, and composition for chemical mechanical planarization of a tungsten-containing substrate |
US8790521B2 (en) | 2008-12-23 | 2014-07-29 | Air Products And Chemicals, Inc. | Combination, method, and composition for chemical mechanical planarization of a tungsten-containing substrate |
US8921226B2 (en) | 2013-01-14 | 2014-12-30 | United Microelectronics Corp. | Method of forming semiconductor structure having contact plug |
Also Published As
Publication number | Publication date |
---|---|
KR20030055392A (en) | 2003-07-04 |
US20030119324A1 (en) | 2003-06-26 |
KR100442962B1 (en) | 2004-08-04 |
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