US6759318B1 - Translation pad flip chip (TPFC) method for improving micro bump pitch IC substrate structure and manufacturing process - Google Patents

Translation pad flip chip (TPFC) method for improving micro bump pitch IC substrate structure and manufacturing process Download PDF

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US6759318B1
US6759318B1 US10/414,597 US41459703A US6759318B1 US 6759318 B1 US6759318 B1 US 6759318B1 US 41459703 A US41459703 A US 41459703A US 6759318 B1 US6759318 B1 US 6759318B1
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layer
bump
pads
metal
dielectric layer
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Chien-Wei Chang
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Kinsus Interconnect Technology Corp
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/385—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by conversion of the surface of the metal, e.g. by oxidation, whether or not followed by reaction or removal of the converted layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Definitions

  • the invention relates to a method used in Translation Pad Flip Chip (TPFC) IC substrate manufacturing process, and more particularly to a method used in manufacturing micro bump pitch IC substrates.
  • TPFC Translation Pad Flip Chip
  • the conventional structure of IC substrates is a 4 to 10 layers of multi-layer printed circuit board, which is made of ceramics or organic materials.
  • the conductive circuits between the layers are micro vias, mechanical or laser drilled, and wired to form bump pads for connecting IC bumps.
  • Solder resist is used to define bump pad lands, and solders are applied by stencil printing. Conventionally, there are two ways to define the bump pad lands. The first is use solder resist to define the lands, as shown in FIG. 1, and the other is called metal defined lands, as shown in FIG. 2 .
  • the line between the bump pads will decrease the area of bump pad lands, which may cause solder paste unable to enter and fill solder mask opening where the grain size of the solder 102 is too large to be applied into the bump pad 101 .
  • This is problematic as the bonding strength is not sufficient to hold the IC chips, due to the lack of sufficient solder applied, as shown in FIG. 1 .
  • the solder resist 201 , 202 covers less than 75 um in width, the solder resist 202 usually will not stick and is prone to peel off, as shown in FIG. 2 .
  • conventional methods are unable to manufacture micro bump pitch substrates.
  • the present invention provides a method to improve micro bump pitch IC substrates manufacturing process. It uses a dielectric layer to replace the conventional solder resist, then uses CCD high precision alignment laser drill to open up the defined bump pad lands, fills them with via plating filled metal accompanied by etching to enlarge the bump pads, and finally surface finishing the bump pads with various materials, such as solder, Ni/Au, or organic coating. This can simultaneously solve the problems of insufficient strength of bump pads, limitation of printing technology and being unable to apply the solder in the conventional technologies. Furthermore, the present invention can also translate the bump pads, passive component pads (e.g., capacitor pads), fiducial marks to the surface level, and avoid burying the pads in the solder resist that occurs in the conventional methods.
  • passive component pads e.g., capacitor pads
  • the substrate structure also improves the underfilling step following the IC connection in the packaging process, and solves the micro bump pitch IC packaging problem.
  • the present invention applies small bump pad at original design bump layer, and provides more circuit routability and higher packaging density. Further more, it can reduce layer count, get higher yield rate, and provide a total solution to the next generation high density IC design.
  • FIG. 1 shows the conventional method of solder resist defined bump pad lands
  • FIG. 2 shows the conventional method of metal defined bump pad lands
  • FIGS. 3A to 3 V show a method of manufacturing micro bump pitch IC substrates, where the present invention is applicable.
  • FIGS. 3A to 3 V show the complete method of manufacturing Translation Pad for Micro bump pad pitch IC substrates, with feature steps of the present invention in FIGS. 3P to 3 V.
  • FIGS. 3A to 3 C show a process of providing a substrate.
  • FIG. 3A shows a core 301 which may be a laminate made of Bismaleimide Triazine (BT), other organic material, or even ceramics.
  • a first metal layer 302 which may be made of copper (Cu), is made on said substrate 301 .
  • FIG. 3B shows a plurality of through holes 303 drilled on said substrate 301 .
  • FIG. 3C shows that a first metal plated layer 304 , which may be made of copper (Cu), is formed on said first metal layer 302 and said through holes 303 .
  • FIGS. 3D to 3 E show a step of forming an inner layer circuit.
  • FIG. 3D uses a dry film 305 by image transfer pattern as the inner layer circuit.
  • a part of said first metal plated layer 304 and a part of said first metal layer 302 are etched to form traces 306 .
  • the remained portions of said first metal plated layer 304 and said first metal layer 302 are left as the inner layer circuit 306 .
  • FIG. 3F shows a step of black-oxidizing the inner layer circuit.
  • a black oxide inner layer circuit 307 is formed in said inner layer circuit 306 by oxidizing the inner layer circuit 306 .
  • FIGS. 3G to 3 H show a step of forming a dielectric layer and a second metal layer.
  • FIG. 3G shows using the dielectric material in the traces and the through holes of the substrate to form a dielectric layer 308 .
  • the dielectric layer 308 is made of Bismaleimide Triazing (BT) or other dielectric material.
  • a metal foil 309 which may be made of copper (Cu), is laminated on said dielectric layer 308 .
  • FIG. 3G shows the metal foil thickness of said foil 309 is reduced, by chemical micro etching, to form the second metal layer 309 a.
  • FIGS. 3I to 3 L show a step of forming vias in the dielectric layer.
  • FIG. 3I shows the dry film 310 used to form laser conformal mask 311 , as shown in FIG. 3J.
  • a plurality of micro vias 312 are drilled as shown in FIG. 3K.
  • a second metal plated layer 313 is formed in said micro vias 312 and said second metal plated layer 313 , as shown in FIG. 3 L.
  • FIGS. 3M to 3 O show a step of forming a circuit layer.
  • FIG. 3M shows an image of photo resist 315 is used as a mask.
  • Plating filled copper 314 is applied in said dielectric circuit second metal plated layer 313 and said vias 312 according to the area exposed by said photo resist mask 315 .
  • a Ni/Au or Sn/Pb 316 is plated to act as an etching resist as FIG. 3N shows.
  • FIG. 3M shows an image of photo resist 315 is used as a mask.
  • Plating filled copper 314 is applied in said dielectric circuit second metal plated layer 313 and said vias 312 according to the area exposed by said photo resist mask 315 .
  • a Ni/Au or Sn/Pb 316 is plated to act as an etching resist as FIG. 3N shows.
  • FIG. 3N shows an etching resist
  • 3O shows the stripping of said photo resist mask 315 , using said Ni/Au or Sn/Pb 316 as an etching resist to etch on said second metal layer 309 a wherein the remained portion is the circuit layer 317 , including bump pads 318 a , 318 b , and 318 c.
  • FIG. 3P shows a step of forming a layer of dielectric.
  • a layer of dielectric 319 is formed on the bump pad side of the substrate to replace the solder resist used in conventional methods.
  • a solder resist layer 320 is formed on the ball pad side of the substrate.
  • FIGS. 3Q to 3 R show a step of forming a plurality of micro vias drilled by CCD alignment then laser ablation.
  • Use CCD alignment laser to ablate a plurality of micro vias 321 on said dielectric layer 319 , so that the bump pads, passive component pads and fiducial marks are open to the surface level.
  • use the conventional exposure printing method to form solder resist ball pads 322 on said solder resist 320 , and electro-plate a thin metal conductive layer, as shown in FIG. 3 Q.
  • FIG. 3R shows the plating filled vias step.
  • Use plating resist 323 to protect said ball pads from electro-plating, and the exposed bump pads are applied with a layer of plating filled metal 324 to fill up said micro vias.
  • FIGS. 3S-3U shows a step enlarging the bump pads. Remove the electro-plating resist 323 protecting said ball pads to expose the ball pads. Apply photo plating resist 325 on bump pad side, and use the image as a mask. The exposed areas (such as passive component pads, fiducial marks) and exposed ball pads are applied with a layer of Ni/Au or Sn/Pb 326 , as shown in FIG. 3 S.
  • FIG. 3T shows the stripping of the photo plating resist 325 , applying photo etching resist 327 . Use the image as a mask to cover the areas of the enlarged bump pads on said bump pad side metal layer 324 .
  • FIG. 3T shows the stripping of the photo plating resist 325 , applying photo etching resist 327 .
  • Ni/Au or Sn/Pb combined with etching resist mask 327 , is used to form a layer of Ni/Au or Sn/Pb on passive component pads 328 , fiducial marks 329 , and flexible adjust bump pads 330 to match wafer side bump size on said dielectric layer 319 and ball pads 331 in the etching process.
  • FIG. 3V shows the step of applying eutectic solder paste, or the environmentally friendly lead-free solder onto said enlarged bump pads, and flattening said bump pads 332 .
  • the step of using plating filled vias solves the problem of insufficient bonding strength due to the under-sized bump pads.
  • the final surface finishing e.g., electro-plating Ni/Au, Sn/Pb Paste, lead-free material or organic solderability coating
  • the final surface finishing can provide more IC connecting methods, such as, IC Gold Stub/Tin Stub connection, and gold wiring. If solder paste, or lead-free solder paste, is applied to make the Sn/Pb solder bump, and the bumps are flattened, the flip chip packaging methods can also be used.
  • the present invention can also be used to improve the routing density in conventional flip chip packaging methods.
  • conventional methods require at least the bump pads with the size of 150 um in diameter.
  • the size of the bump pads can be reduced to below 80 um.
  • the saved 70 um can be used to increase the routing density, and further reduce the substrate's 6- to 10-layer structure to a 4- to 8-layer structure. This will further reduce the manufacturing cost.

Abstract

A method for a manufacturing process of micro bump pitch IC substrates uses a dielectric layer to replace the conventional solder resist, then uses CCD high precision alignment laser drill to open up the defined bump pad lands, and fills them with via plating filled metal accompanied by etching to enlarge the bump pads, and finally plates the bum pads with Sn/Pb. This can simultaneously solve the problems of insufficient strength of bump pads, limitation of printing technology and being unable to apply the solder in the conventional technologies. The method can provide a higher packaging density, higher yield rate, and provides a total solution to the next generation high density IC design.

Description

FIELD OF THE INVENTION
The invention relates to a method used in Translation Pad Flip Chip (TPFC) IC substrate manufacturing process, and more particularly to a method used in manufacturing micro bump pitch IC substrates.
BACKGROUND OF THE INVENTION
Recent product developments within the electronic industry are able to integrate more functions in a single substrate, which has led to a rapid increase in the number of I/Os used in a substrate, and a higher demand on packaging technology. With the Flip Chip (FC) technology currently used in the high level products, a higher packaging density is achieved, for example, the bump pitch between IC bumps can be reduced from 300 um to 200 um with the improvement of the alignment precision during the manufacturing process. However, with the next generation products that demand a packaging technology to reduce the bump pitch below 150 um, the conventional substrate structure and manufacturing methods can no longer meet such a demand. Therefore, the development of new substrate structure and manufacturing methods is imperative.
The conventional structure of IC substrates is a 4 to 10 layers of multi-layer printed circuit board, which is made of ceramics or organic materials. The conductive circuits between the layers are micro vias, mechanical or laser drilled, and wired to form bump pads for connecting IC bumps. Solder resist is used to define bump pad lands, and solders are applied by stencil printing. Conventionally, there are two ways to define the bump pad lands. The first is use solder resist to define the lands, as shown in FIG. 1, and the other is called metal defined lands, as shown in FIG. 2. When the bump pitch between IC bumps is reduced to below 150 um, the line between the bump pads will decrease the area of bump pad lands, which may cause solder paste unable to enter and fill solder mask opening where the grain size of the solder 102 is too large to be applied into the bump pad 101. This is problematic as the bonding strength is not sufficient to hold the IC chips, due to the lack of sufficient solder applied, as shown in FIG. 1. On the other hand, when when the solder resist 201, 202 covers less than 75 um in width, the solder resist 202 usually will not stick and is prone to peel off, as shown in FIG. 2. Hence, conventional methods are unable to manufacture micro bump pitch substrates.
SUMMARY OF THE INVENTION
The present invention provides a method to improve micro bump pitch IC substrates manufacturing process. It uses a dielectric layer to replace the conventional solder resist, then uses CCD high precision alignment laser drill to open up the defined bump pad lands, fills them with via plating filled metal accompanied by etching to enlarge the bump pads, and finally surface finishing the bump pads with various materials, such as solder, Ni/Au, or organic coating. This can simultaneously solve the problems of insufficient strength of bump pads, limitation of printing technology and being unable to apply the solder in the conventional technologies. Furthermore, the present invention can also translate the bump pads, passive component pads (e.g., capacitor pads), fiducial marks to the surface level, and avoid burying the pads in the solder resist that occurs in the conventional methods. The substrate structure also improves the underfilling step following the IC connection in the packaging process, and solves the micro bump pitch IC packaging problem. The present invention applies small bump pad at original design bump layer, and provides more circuit routability and higher packaging density. Further more, it can reduce layer count, get higher yield rate, and provide a total solution to the next generation high density IC design.
The present invention will become more obvious from the following description when taken in connection with the accompanying drawings which show, for purposes of illustration only, a preferred embodiment in accordance with the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the conventional method of solder resist defined bump pad lands;
FIG. 2 shows the conventional method of metal defined bump pad lands;
FIGS. 3A to 3V show a method of manufacturing micro bump pitch IC substrates, where the present invention is applicable.
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 3A to 3V show the complete method of manufacturing Translation Pad for Micro bump pad pitch IC substrates, with feature steps of the present invention in FIGS. 3P to 3V.
FIGS. 3A to 3C show a process of providing a substrate. FIG. 3A shows a core 301 which may be a laminate made of Bismaleimide Triazine (BT), other organic material, or even ceramics. A first metal layer 302, which may be made of copper (Cu), is made on said substrate 301. FIG. 3B shows a plurality of through holes 303 drilled on said substrate 301. FIG. 3C shows that a first metal plated layer 304, which may be made of copper (Cu), is formed on said first metal layer 302 and said through holes 303.
FIGS. 3D to 3E show a step of forming an inner layer circuit. FIG. 3D uses a dry film 305 by image transfer pattern as the inner layer circuit. A part of said first metal plated layer 304 and a part of said first metal layer 302 are etched to form traces 306. As shown in FIG. 3E, the remained portions of said first metal plated layer 304 and said first metal layer 302 are left as the inner layer circuit 306.
FIG. 3F shows a step of black-oxidizing the inner layer circuit. A black oxide inner layer circuit 307 is formed in said inner layer circuit 306 by oxidizing the inner layer circuit 306.
FIGS. 3G to 3H show a step of forming a dielectric layer and a second metal layer. FIG. 3G shows using the dielectric material in the traces and the through holes of the substrate to form a dielectric layer 308. The dielectric layer 308 is made of Bismaleimide Triazing (BT) or other dielectric material. A metal foil 309, which may be made of copper (Cu), is laminated on said dielectric layer 308. FIG. 3G shows the metal foil thickness of said foil 309 is reduced, by chemical micro etching, to form the second metal layer 309 a.
FIGS. 3I to 3L show a step of forming vias in the dielectric layer. FIG. 3I shows the dry film 310 used to form laser conformal mask 311, as shown in FIG. 3J. A plurality of micro vias 312 are drilled as shown in FIG. 3K. A second metal plated layer 313 is formed in said micro vias 312 and said second metal plated layer 313, as shown in FIG. 3L.
FIGS. 3M to 3O show a step of forming a circuit layer. FIG. 3M shows an image of photo resist 315 is used as a mask. Plating filled copper 314 is applied in said dielectric circuit second metal plated layer 313 and said vias 312 according to the area exposed by said photo resist mask 315. Then, a Ni/Au or Sn/Pb 316 is plated to act as an etching resist as FIG. 3N shows. FIG. 3O shows the stripping of said photo resist mask 315, using said Ni/Au or Sn/Pb 316 as an etching resist to etch on said second metal layer 309 a wherein the remained portion is the circuit layer 317, including bump pads 318 a, 318 b, and 318 c.
The aforementioned steps up to this point are steps used in related arts. The following are the steps proposed in the present invention. FIG. 3P shows a step of forming a layer of dielectric. A layer of dielectric 319 is formed on the bump pad side of the substrate to replace the solder resist used in conventional methods. A solder resist layer 320 is formed on the ball pad side of the substrate.
FIGS. 3Q to 3R show a step of forming a plurality of micro vias drilled by CCD alignment then laser ablation. Use CCD alignment laser to ablate a plurality of micro vias 321 on said dielectric layer 319, so that the bump pads, passive component pads and fiducial marks are open to the surface level. Then, use the conventional exposure printing method to form solder resist ball pads 322 on said solder resist 320, and electro-plate a thin metal conductive layer, as shown in FIG. 3Q. FIG. 3R shows the plating filled vias step. Use plating resist 323 to protect said ball pads from electro-plating, and the exposed bump pads are applied with a layer of plating filled metal 324 to fill up said micro vias.
FIGS. 3S-3U shows a step enlarging the bump pads. Remove the electro-plating resist 323 protecting said ball pads to expose the ball pads. Apply photo plating resist 325 on bump pad side, and use the image as a mask. The exposed areas (such as passive component pads, fiducial marks) and exposed ball pads are applied with a layer of Ni/Au or Sn/Pb 326, as shown in FIG. 3S. FIG. 3T shows the stripping of the photo plating resist 325, applying photo etching resist 327. Use the image as a mask to cover the areas of the enlarged bump pads on said bump pad side metal layer 324. In FIG. 3U, Ni/Au or Sn/Pb, combined with etching resist mask 327, is used to form a layer of Ni/Au or Sn/Pb on passive component pads 328, fiducial marks 329, and flexible adjust bump pads 330 to match wafer side bump size on said dielectric layer 319 and ball pads 331 in the etching process.
FIG. 3V shows the step of applying eutectic solder paste, or the environmentally friendly lead-free solder onto said enlarged bump pads, and flattening said bump pads 332.
The present invention has the following advantages in comparison with the current technologies:
1. The use of a dielectric layer to replace solder resist. Because said dielectric layer has the same coefficient of thermal expansion as the substrate, it solves the problem of substrate warpage or twist due to the heat expansion during the process. Furthermore, the failure rate of the packaging reliability testing is reduced because of the homogeneity of material, and said material has better physical characteristics, such as water absorption, than solder resist. Therefore, the packaging reliability is improved.
2. The step of using plating filled vias solves the problem of insufficient bonding strength due to the under-sized bump pads.
3. By using etching on the dielectric layer, it does not only expose a larger area of said bump pad, but also raise the passive component pads and fiducial marks to the surface level of said dielectric layer. This solves the problems of bump pads being buried in the solder resist, or solder grain size too large for stencil print soldering that are associated with conventional methods.
4. By enlarging bump pads and providing higher flexibility, the final surface finishing (e.g., electro-plating Ni/Au, Sn/Pb Paste, lead-free material or organic solderability coating) can provide more IC connecting methods, such as, IC Gold Stub/Tin Stub connection, and gold wiring. If solder paste, or lead-free solder paste, is applied to make the Sn/Pb solder bump, and the bumps are flattened, the flip chip packaging methods can also be used.
5. The present invention can also be used to improve the routing density in conventional flip chip packaging methods. For example, when said conventional flip chip substrate uses a 250 um IC design, conventional methods require at least the bump pads with the size of 150 um in diameter. With present invention, the size of the bump pads can be reduced to below 80 um. The saved 70 um can be used to increase the routing density, and further reduce the substrate's 6- to 10-layer structure to a 4- to 8-layer structure. This will further reduce the manufacturing cost.
While we have shown and described the embodiment in accordance with the present invention, it should be clear to those skilled in the art that further embodiments may be made without departing from the scope of the present invention.

Claims (4)

What is claimed is:
1. A method for improving an IC substrate manufacturing process with bump pitch less than 180 um, comprising the steps of:
(a) providing a substrate formed with a first metal layer and a plurality of through holes, said first metal layer and said plurality of through holes being plated with a first metal plated layer;
(b) forming an inner layer circuit by patterning and etching said first metal layer and said first metal plated layer;
(c) black-oxiding said inner layer circuit;
(d) covering and filling said inner layer circuit and said plurality of through holes with a first dielectric layer;
(e) covering said first dielectric layer with a second metal layer;
(f) forming a plurality of first micro vias through said second metal layer and said first dielectric layer;
(g) plating said second metal layer and said plurality of first micro vias with a second metal plated layer;
(h) filling said plurality of first micro vias with plating filled copper, etching and forming a circuit layer above said plurality of first micro vias and said second metal plated layer, said circuit layer including a plurality of bump pads on a bump-pad side of said substrate and a plurality of ball pads on a ball-pad side of said substrate;
(i) forming a second dielectric layer on said bump-pad side for covering said plurality of bump pads, and a solder resist layer on said ball-pad side for covering said plurality of ball pads;
(j) forming a plurality of second micro vias by CCD alignment laser drilling on said second dielectric layer for exposing said plurality of bump pads;
(k) filling up said plurality of second micro vias with plating filled metal to a surface level for providing enlarged bump pads and translating passive components and fiducial marks to said surface level;
(l) providing flexible and adjustable bump pads to meet wafer side bump size; and
(m) providing flexible final finishing.
2. The method as claimed in claim 1, wherein said bump pads are enlarged by using photo etching resist as a mask and electro-plating Ni/Au or Sn/Pb on said second dielectric layer, and said enlarged bump pads are applied with solder paste or electro-plating Sn/Pb reflow and then flattened for wafer side bump connection.
3. The method as claimed in claim 1, wherein said bump pads have a bump pitch less than 150 um.
4. The method as claimed in claim 1, wherein said solder resist layer includes solder resist with a width less than 75 um.
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WO2011023556A1 (en) * 2009-08-24 2011-03-03 Epcos Ag Carrier device, arrangement comprising such a carrier device, and method for patterning a layer stack comprising at least one ceramic layer
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USRE49045E1 (en) * 2011-10-31 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US20130200509A1 (en) * 2012-02-02 2013-08-08 Samsung Electronics Co., Ltd. Semiconductor package
CN103871907A (en) * 2014-03-26 2014-06-18 华进半导体封装先导技术研发中心有限公司 Manufacturing technology of ultra-thin substrate
CN103871907B (en) * 2014-03-26 2017-04-12 华进半导体封装先导技术研发中心有限公司 Manufacturing technology of ultra-thin substrate
CN112492755A (en) * 2020-11-02 2021-03-12 江西旭昇电子有限公司 Method for manufacturing micro solder mask definition bonding pad of lead-free tin-spraying plate
CN112492755B (en) * 2020-11-02 2022-09-27 江西旭昇电子有限公司 Method for manufacturing micro solder mask definition bonding pad of lead-free tin-spraying plate

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