US6713687B2 - Printed wiring board and method for manufacturing printed wiring board - Google Patents

Printed wiring board and method for manufacturing printed wiring board Download PDF

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Publication number
US6713687B2
US6713687B2 US10/022,222 US2222201A US6713687B2 US 6713687 B2 US6713687 B2 US 6713687B2 US 2222201 A US2222201 A US 2222201A US 6713687 B2 US6713687 B2 US 6713687B2
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United States
Prior art keywords
metal
conductive compound
hole
printed wiring
wiring board
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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US10/022,222
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US20020079135A1 (en
Inventor
Yoshitarou Yazaki
Tomohiro Yokochi
Koji Kondo
Toshikazu Harada
Yoshihiko Shiraishi
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Murata Manufacturing Co Ltd
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Denso Corp
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Assigned to DENSO CORPORATION reassignment DENSO CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIRAISHI, YOSHIHIKO, HARADA, TOSHIKAZU, KONDO, KOJI, YAZAKI, YOSHITAROU, YOKOCHI, TOMOHIRO
Publication of US20020079135A1 publication Critical patent/US20020079135A1/en
Priority to US10/662,368 priority Critical patent/US7188412B2/en
Application granted granted Critical
Publication of US6713687B2 publication Critical patent/US6713687B2/en
Assigned to MURATA MANUFACTURING CO., LTD. reassignment MURATA MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DENSO CORPORATION
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4632Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0129Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0263Details about a collection of particles
    • H05K2201/0272Mixed conductive particles, i.e. using different conductive particles, e.g. differing in shape
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0302Properties and characteristics in general
    • H05K2201/0305Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0355Metal foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0388Other aspects of conductors
    • H05K2201/0394Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827Tapered, e.g. tapered hole, via or groove
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09863Concave hole or via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/0425Solder powder or solder coated metal powder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Definitions

  • the present invention relates to a printed wiring board and a manufacturing method thereof, specifically relates to a double-sided printed wiring board and a multilayer printed wiring board with a plurality of electrically-interconnected conductor pattern layers formed thereon and to a manufacturing method thereof.
  • an insulator board includes a plurality of conductor patterns and the conductor patterns are interconnected by a conductive compound in a via-hole formed in the insulator board.
  • a method shown in FIG. 12A is proposed.
  • a substantially cylindrical via-hole 124 is formed in an insulator board 123 , which is made of prepreg in B stage status prepared by impregnating a core material such as glass cloth with unset thermosetting resin.
  • a conductive paste 150 which is an interlayer connecting material consisting of metal particles and binder resin made of unset thermosetting resin, is packed in the via-hole 124 .
  • the board and conductive foils 122 forming a conductor pattern are laminated.
  • the conductive paste 150 becomes a unified conductive compound 151 with the setting of the binder resin, and conductive foils 122 forming conductor patterns are interconnected by the substantially cylindrical conductive compound 151 formed in the substantially cylindrical via-hole 124 .
  • interconnection between the conductive foils 122 forming conductor patterns is achieved with the substantially cylindrical conductive compound 151 . Therefore, in a case that the printed wiring board incurs a stress due to deformation such as bending, the conductive compound 151 is likely to incur stress concentration in the vicinity of a junction part 151 b that is a junction part with the conductor pattern (the conductive foil 122 ). If repeated or large stress concentration is generated in the vicinity of the junction part 151 b , reliability of the interconnection is lowered.
  • the present invention has been made in view of the above-mentioned aspects with an object to provide a printed wiring board having reliable interlayer connection and a fabrication method thereof.
  • a printed wiring board has a unified conductive compound in a via-hole.
  • the compound has a side wall adjacent to an area contacting the conductor pattern.
  • the wall has an inclination against the conductor pattern in such a manner that the farther from the conductor patterns on the side wall, the closer to the center axis of the via-hole.
  • the conductive compound is formed such that the cross section thereof on the cross-sectional plane that passes the center axis of the via-hole provides an arch shape.
  • the film is made of thermoplastic resin. Therefore, when the conductive compound with the inclination of the side wall is formed, the insulator film is readily deformed plastically and the via-hole is readily formed in a shape conforming to the shape of the conductive compound.
  • the conductive compound is readily formed with the inclination of the side wall.
  • the conductor pattern is made of metal.
  • the interlayer connecting material includes first and second metal particles.
  • the first metal particles can form first alloy with the metal making up the conductor pattern.
  • the second metal particles have higher melting point than the heating temperature for interconnecting layers and can form second alloy with the metal making up the first metal particle.
  • the unified conductive compound is formed by hot-pressing the interlayer connecting material in the via-hole between a plurality of conductor patterns. Therefore, the conductor patterns are electrically interconnected with the conductive compound and the interposing solid phase diffusion layer that is formed by the mutual solid phase diffusion between the metal making up the conductor pattern and the first metal in the conductive compound.
  • the electrical interconnection between the conductor patterns is not made by mechanical contact so that the interlayer contact resistance hardly changes.
  • the reliability of the interconnection is certainly enabled to avoid becoming worse.
  • FIGS. 1A to 1 E are process-by-process cross-sectional views showing production processes of a printed wiring board in the first embodiment of the present invention
  • FIGS. 2A and 2B are partially-enlarged schematic views of printed wiring boards respectively after packing a conductive paste in a via-hole and after interconnecting layers in the first embodiment of the present invention
  • FIG. 3 is a partially-enlarged view showing schematically the shape of a conductive compound in the first embodiment of the present invention
  • FIG. 4 is a graph showing the evaluation result on the adhesion between a copper foil forming the conductor pattern and the conductive compound
  • FIG. 5 is a graph showing the change ratio in the via serial resistance of the printed wiring board after reflow-soldering process of the printed wiring board;
  • FIGS. 6A and 6B are partially-enlarged schematic views showing respectively the states after packing the conductive paste in the via-hole and after interconnecting layers in the second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing an element piling configuration for a multilayer printed wiring board
  • FIG. 8 is a cross-sectional view showing another element piling configuration for a multilayer printed wiring board
  • FIG. 9 is a cross-sectional view showing other element piling configuration for a multilayer printed wiring board.
  • FIG. 10 is a cross-sectional view showing other element piling configuration for a multilayer printed wiring board
  • FIG. 11 is a cross-sectional view showing other element piling configuration for a multilayer printed wiring board.
  • FIGS. 12A and 12B are partially-enlarged schematic views of printed wiring boards respectively after packing a conductive paste in a via-hole and after interconnecting layers in the related art.
  • a single-sided conductor pattern film 21 is shown as having a plurality of conductor patterns 22 that are defined by means of etching a conductive foil (a copper foil with 18 ⁇ m thickness in this embodiment) adhered onto one side of a resin film 23 .
  • a thermoplastic film with 25-75 ⁇ m thickness which is made of a mixture of 65-35% polyetheretherketone resin and 35-65% polyetherimide resin, is used as the resin film 23 .
  • a substantially cylindrical via-hole 24 bottomed with the conductor pattern 22 is formed by exposing the resin film 23 to carbon dioxide laser, as shown in FIG. 1 B.
  • the conductor pattern 22 escapes being dug by the laser by adjusting the power and the exposure period of the carbon dioxide laser and such.
  • via-hole 24 Other than the carbon dioxide laser, excimer laser or the like may be utilized for formation of the via-hole 24 .
  • excimer laser or the like may be utilized for formation of the via-hole 24 .
  • other via-hole formation means such as drilling is applicable.
  • hole machining by laser beam is preferable because of capability thereof in fine hole machining with the least damage to the conductor pattern 22 .
  • conductive paste 50 that is a material for interlayer connection is packed in the via-hole 24 as shown in FIG. 1 C.
  • the paste is prepared by the steps mentioned below. 60 g of terpineol, which is organic solvent, is added to 300 g of tin particles 61 (first metal particles and shown in FIG. 2A) with 5 ⁇ m mean particle size and 0.5 m 2 /g specific surface and 300 g of silver particles 62 (second metal particles and shown in FIG. 2A) with 1 ⁇ m mean particle size and 1.2 m 2 /g specific surface. The mixture is compounded by a mixer to make it pasty.
  • the terpineol is evaporated at 140-160° C. for 30 minutes.
  • the screen printing machine is used for packing the conductive paste 50 into the via-hole 24 .
  • other methods using a dispenser or the like are usable as long as the methods enable reliable packing.
  • Organic solvents other than terpineol are applicable as a solvent to make a paste.
  • organic solvents with 150-300° C. boiling point are preferably used.
  • Organic solvents having the boiling point of 150° C. or lower is likely to increase time-dependent variation of the viscosity of the conductive paste 50 .
  • organic solvent having boiling point higher than 300° C. is unfavorable because evaporation time thereof becomes longer.
  • the tin particles with 5 ⁇ m mean particle size and 0.5 m 2 /g specific surface and the silver particles with 1 ⁇ m mean particle size and 1.2 m 2 /g specific surface are used for the conductive paste 50 .
  • the metal particles preferably have 0.5-20 ⁇ m mean particle size and 0.1-1.5 m 2 /g specific surface.
  • the metal particles have mean particle size smaller than 0.5 ⁇ m or specific surface larger than 1.5 m 2 /g, a lot of organic solvent is required for adjusting the paste to suitable viscosity for via-hole packing.
  • Conductive paste containing a lot of organic solvent requires long time for evaporation, and a lot of gas is generated by the heating during interconnecting time period if the evaporation is insufficient. Therefore, voids are likely to be generated in the via-hole 24 , and reliability of the interconnection is lowered.
  • the metal particles have mean particle size larger than 20 ⁇ m or specific surface smaller than 0.1 m 2 /g, it becomes difficult to pack the paste into the via-hole 24 .
  • the metal particles are likely to be unevenly distributed so that it also becomes difficult to provide the conductive compound 51 made of homogeneous alloy after heating.
  • the surface of the conductor pattern 22 facing the via-hole 24 may be slightly etched or reduced. Thereby, solid phase diffusion described later is preferably done.
  • a plurality of single-sided conductor pattern films 21 are piled, as shown in FIG. 1 D.
  • One pair of single-sided conductor pattern films 21 of the lower side are piled such that the side including the conductor pattern 22 faces downward.
  • the other pair of single-sided conductor pattern films 21 of the upper side are piled such that the side including the conductor pattern 22 faces upward.
  • one pair of single-sided conductor pattern films 21 placed inside are piled together such that the side including no conductor pattern 22 faces each other.
  • the other pair of single-sided conductor pattern films 21 are piled such that the side including conductor pattern 22 of one film faces the side including no conductor pattern 22 of the other film.
  • a cover layer 36 a that is a resist film covering the conductor pattern 22 on the top layer is piled on the piled single-sided conductor pattern films 21 having a plurality of layers, and so is a cover layer 36 b that is another resist film covering the conductor pattern 22 on the bottom layer.
  • the cover layer 36 a is machined to provide a hole 39 a through which an electrode 32 is exposed in a predetermined position of the conductor pattern 22 on the top layer, and so is the cover layer 36 b to provide another hole 39 b through which an electrode 37 is exposed in a predetermined position of the conductor pattern 22 on the bottom layer.
  • the same resin film as for the resin film 23 which is a thermoplastic film with 25-75 ⁇ m thickness, made of a mixture of 65-35% polyetheretherketone resin and 35-65% polyetherimide resin, is used for the cover layers 36 a and 36 b.
  • the piled unit After piling the single-sided conductor pattern films 21 and the cover layer 36 a , 36 b as shown in FIG. 1D, the piled unit is hot-pressed from the top and bottom surfaces thereof by a vacuum hot-press machine. In this embodiment, the piled unit is pressed for 10-20 minutes under 2-10 MP pressure with heating temperature of 240-350° C.
  • each single-sided conductor pattern film 21 and the cover layer 36 a , 36 b are bonded together. While the resin films 23 and the cover layer 36 a , 36 b thermally fuse together to be unified, the conductor patterns 22 adjacent to the conductive paste 50 in the via-hole 24 are interconnected and a multilayer printed wiring board 100 with the electrode 32 on one side and the electrode 37 on the other side is provided.
  • the resin film 23 and the cover layer 36 a , 36 b are made of the same thermoplastic resin so that both are firmly unified by being thermally softened and pressed.
  • the mechanism of the interconnection is explained with reference to FIGS. 2A and 2B.
  • the tin particles 61 melt and stick to the surface of the silver particles 62 because the melting point of the tin particles 61 and that of the silver particles 62 are 232° C. and 961° C., respectively.
  • fused tin begins defusing from the surface of the silver particles and an alloy (melting point 480° C.) is made between tin and silver.
  • the conductive paste is under 2-10 MP pressure. Therefore, as shown in FIG. 2B, the conductive compound 51 is formed in the via-hole 24 with the tin-silver alloy formation.
  • the solid phase diffusion layer is formed similarly at the interface between the conductor pattern 22 at the lower side of the via-hole 24 and the conductive compound 51 . Therefore, both conductor patterns 22 at the top and bottom of the via-hole 24 are electrically interconnected by the unified conductive compound 51 and the solid phase diffusion layer 52 . In this way, while the conductor patterns 22 are interconnected by the hot-press with the vacuum hot-press machine, the conductive compound 51 continues to be sintered even after the solid phase diffusion layer 52 is formed, and the conductive compound 51 shrinks. In this embodiment, the conductive compound 51 is smaller in volume by 10-20% than the conductive paste 50 .
  • the resin film 23 is hot-pressed by the vacuum hot-press machine, the resin film 23 is deformed in an extendable direction and the resin film 23 adjacent to the via-hole 24 is deformed to protrude out into the via-hole 24 .
  • the modulus of elasticity of the resin film 23 is reduced to about 5-40 MPa while being hot-pressed by the vacuum hot-press machine. If the resin film 23 with reduced modulus of elasticity is pressed in this way, substantially homogeneous pressure (hydrostatic pressure) is generated in the insulator resin film 23 .
  • the pressing is continued with substantially homogeneous pressure provided in the resin film 23 , and the resin film 23 adjacent to the via-hole 24 is deformed plastically to protrude out into the via-hole 24 .
  • the protrusion amount of the resin film 23 into the via-hole becomes larger at the central part (the central part of the via-hole 24 in the direction of the center) of the via-hole 24 than at the end part (the end part of the via-hole 24 in the direction of the center axis) connected to the conductor pattern 22 .
  • the side wall of the via-hole 24 which is substantially cylindrical before hot-pressing, is deformed such that the shape of the side wall on the cross-section that passes the center axis of the via-hole 24 provides an arch shape by letting the resin film 23 protrude into the via-hole 24 as described above.
  • the apparent volume of the compound 51 decreases as the sintering proceeds. While shrinking, the compound 51 is pushed by the resin film 23 that protrudes such that the cross-section shape thereof provides an arch shape. Therefore, the deformation of the resin film 23 in the direction of the protrusion into the via-hole 24 proceeds synchronously with the shrinkage of the conductive compound 51 such that the side wall of the via-hole 24 is always in contact with the conductive compound 51 . As a result, as shown in FIG. 3, the side wall of the conductive compound 51 is formed to provide an arch shape on the cross-section that passes the center axis of the via-hole 24 .
  • a side wall 51 a of the conductive compound 51 is formed with the inclination against the conductor pattern 22 in such a manner that the farther from the conductor patterns 22 , the closer to the center axis of the via-hole 24 .
  • the modulus of elasticity of the resin film 23 during the hot-pressing process is preferably 1-1000 MPa. If the modulus of elasticity is larger than 1000 MPa, it is difficult to provide homogeneous internal pressure in the resin film 23 and difficult to bond the resin films 23 together by fusing thermally. On the other hand, if the modulus of elasticity is smaller than 1 MPa, the resin film flows thermally too readily to hold a shape of the printed board 100 .
  • the volume reduction ratio of the conductive compound 51 to the conductor paste 50 is preferably 5% or more. If the reduction ratio is smaller than 5%, it is difficult to form the side wall 51 a of the conductive compound 51 with an inclination large enough against the conductor pattern 22 .
  • the configuration and fabrication method in the first embodiment even in the case that a stress due to a deformation such as bending is applied to the printed wiring board 100 , it is possible to prevent the stress concentration in the junction part 51 b shown in FIG. 3, because the side wall 51 a of the conductive compound 51 is formed with an inclination. Moreover, any other part of the conductive compound 51 is likely to incur less stress concentration because the side wall of the conductive compound 51 is formed to provide an arch shape on the cross-section that passes the center axis of the via-hole 24 . Therefore, the reliability of the interconnection is enabled to avoid becoming worse.
  • a plurality of conductor patterns 22 of the printed wiring board 100 are electrically interconnected with both conductive compound 51 including the tin-silver alloy formed by sintering and the solid phase diffusion layer 52 made between tin in the conductive compound 51 and copper making up the conductor pattern 22 . Therefore, the electrical connection of the conductor patterns 22 is not achieved by mechanical contact so that the interlayer contact resistance hardly changes. Thus, the reliability of the interconnection is further prevented from becoming worse.
  • the metal components of the conductive paste 50 are 50 weight % tin and 50 weight % silver. Tin content in the metal components is preferably 20-80%.
  • FIG. 4 shows variation of the adhesion between the copper foil forming the conductor pattern 22 and the conductive compound when the ratio of tin to silver in the conductive paste 50 is varied.
  • the adhesion evaluation has been conducted as follows.
  • the same tin particles and silver particles as used for the conductive paste 50 in this embodiment are used as metal components.
  • Terpineol is added to the metal components by the amount equivalent to 10 weight % of the metal components and the mixture is treated to provide a paste.
  • the paste is printed on the shiny side of a copper foil and evaporated on the conditions described above.
  • another copper foil is piled on the evaporated paste such that the mat side thereof contacts the paste.
  • the two copper foils interposed by a conductive compound therebetween are bonded by the hot-press on the conditions described above.
  • the shiny side of one copper foil and the mat side of the other copper foil are bonded, because a via packed with the conductive compound in the via-hole thereof is formed between those sides when the single-sided conductor pattern films are piled in the fabrication of the printed wiring board such that each film faces the same direction.
  • the bonded two copper foils are peeled at the speed of 10 mm/min and the peeling strength is defined as the adhesion therebetween.
  • tin content between 20-80% provides preferable adhesion more than 1.0 N/mm, which is an adhesion between the insulator and the copper foil.
  • the fracture mode in the peeling in 20-80% tin content range is not the boundary peeling between the copper foil and the conductive compound, but the internal fracture of the conductive compound. This means that a solid phase diffusion layer more robust than the conductive compound is formed between the copper foil and the conductive compound.
  • FIG. 5 shows the change ratio of the serial via resistance to the via initial serial resistance after reflow-soldering process of the printed wiring board 100 when the ratio of tin to silver in the conductive paste 50 packed in the via-hole 24 are varied.
  • the evaluation has been conducted as follows.
  • the same tin particles and silver particles as used for the conductive paste 50 described above in this embodiment are used as metal components.
  • Terpineol is added to the metal components by the amount equivalent to 10 weight % of the metal components and the mixture is treated to provide a paste.
  • the paste 50 is packed in the via-hole 24 of a single-sided conductor pattern film and evaporated on the conditions described above.
  • a copper foil is piled on the insulator side of the single-sided conductor pattern film. The piled unit is hot-pressed on the conditions described above.
  • a double-sided board having conductor patterns for measuring the serial resistance of the via is prepared in this way.
  • the via serial resistances of the double-sided board are measured as prepared and after the board is passed through a reflowing process with the temperature of 250° C. and time period of 5 minutes.
  • the resistance change ratio therebetween is calculated from the measured values.
  • the tin content between 20-80% ensures that the resistance change ratio by the reflowing is 20% or smaller, which is generally the maximum value to provide preferable reliability. Therefore, it is possible to provide a printed wiring board with excellent connecting reliability if the printed wiring board is manufactured by using, as an interlayer connecting material, the conductive paste 50 with 20-80% tin content in the metal components, as described above.
  • the conductive paste 50 contains the tin particles 61 and the silver particles 62 , and the conductive compound 51 is formed by alloying and sintering both metals.
  • the conductive paste 50 need not necessarily be a material whose metal particles are sintered.
  • the conductive paste 50 may be a material that contains metal particles and unset thermosetting resin as binder resin and becomes a conductive compound whose metal particles are supported by set thermosetting resin.
  • the interconnection is based on contact conduction so that the embodiment described above is more preferable from the standpoint of reliability.
  • silver particles are used as the second metal particles.
  • any other metal particles may be used as long as the particles do not fuse during the interconnecting period and form an alloy with tin that is the first metal particles.
  • Applicable metals are copper (mp 1083° C.), gold (mp 1063° C.), platinum (mp 1769° C.), palladium (mp 1552° C.), nickel (mp 1453° C.), zinc (mp 419° C.) or the like.
  • the second metal particles these may be used either separately or in combination on a case-by-case basis.
  • metal particles contained in the conductive paste 50 are only the tin particles 61 and the silver particles 62 .
  • metal particles with low melting point e.g., iridium particles
  • with about 1-100 nm particle particle size e.g., silver
  • metal particles that do not form an alloy with tin may be added for the sake of adjusting the thermal expansion coefficient of the conductive compound 51 close to that of the insulator resin film 23 .
  • metal particles nonconductive inorganic filler or the like may be added. However, it is unfavorable to add too much to unify the conductive compound 51 .
  • the conductive paste 50 consists of the metal particles 61 and 62 and organic solvent.
  • a dispersing agent may be added to the conductive paste 50 by an amount equivalent to 0.01-1.5 weight % of the total solid components of the conductive paste 50 . This makes it easier to disperse homogeneously the metal particles in the conductive paste 50 . Dispersing agent content less than 0.01 weight % provides scarcely dispersion effect, and dispersing agent content more than 1.5 weight % hinders the unification of the conductive compound 51 by sintering. It is possible to use phosphoric ester and stearic ester or the like as the dispersing agent.
  • grainy material is applicable as long as it is possible to pack the material in the via-hole 24 .
  • conductive paste 150 which consists of organic solvent and alloy particles 162 including 50 weight % tin and 50 weight % silver, is packed in the via-hole 24 of the single-sided conductor pattern film 21 and evaporated. Afterward, the single-sided conductor pattern films 21 are preferably piled and the piled unit is hot-pressed from both sides thereof for forming the unified conductive compound 51 by sintering the alloy particles in the via-hole 24 .
  • the conductive compound 51 is pressurized while being pressed in the via-hole 24 so that the compound 51 is pressed toward the surface of the conductor pattern 22 , which makes up the bottom of the via-hole 24 .
  • tin contained in the conductive compound 51 and copper of the copper foil forming the conductor pattern 22 diffuse mutually in solid phase to form the solid phase diffusion layer 52 at the boundary between the conductive compound 51 and the conductor pattern 22 .
  • the resin film 23 is deformed such that the film 23 protrudes into the via-hole 24 as the volume of the conductive compound 51 decreases. Therefore, the same effect as in the first embodiment is provided.
  • the second metal is not limited to silver. Copper, gold, platinum, palladium, nickel, zinc or the like are applicable as the second metal particles either separately or in combination.
  • the metal components of the conductive paste 150 are 50 weight % tin and 50 weight % silver. As well as in the first embodiment, tin content of the metal components is preferably 20-80%.
  • the single-sided conductor pattern films 21 are piled, as shown in FIG. 1D, in the fabrication processes of the printed wiring board 100 .
  • piling configuration is not limited to this one, but any other configurations may be used as long as the configurations are for providing multilayer or double-sided printed wiring board requiring interlayer connection.
  • a configuration shown in FIG. 7 is possible.
  • a multilayer printed wiring board is made with steps of piling together a single-sided conductor pattern film 71 having a copper foil conductor pattern covering a whole side thereof, single-sided conductor pattern films 21 and a copper foil 81 , then hot-pressing the piled unit, and afterward defining the copper foils on both sides.
  • FIG. 8 Another configuration shown in FIG. 8 is possible as well.
  • a multilayer printed wiring board is made with steps of piling together single-sided conductor pattern films 21 and a double-sided film 91 , and afterward hot-pressing the piled unit.
  • FIG. 9 other configuration shown in FIG. 9 is possible as well.
  • a multilayer printed wiring board is made with steps of piling the resin film 23 on both sides of the double-sided film 91 , then piling the copper foils 81 to the piled unit, and afterward hot-pressing the finally piled body.
  • FIG. 10 Other configuration shown in FIG. 10 is possible as well.
  • a multilayer printed wiring board is made with steps of piling the copper foils 81 on the resin film 23 , then hot-pressing the piled unit, and afterward defining the copper foils on both sides.
  • FIG. 11 Other configuration shown in FIG. 11 is possible as well.
  • a multilayer printed wiring board is made with steps of piling together the single-sided conductor pattern film 71 and the copper foil 81 , then hot-pressing the piled unit, and afterward defining the copper foils on both sides.
  • a resin film made of a mixture of 65-35% polyetheretherketone resin and 35-65% polyetherimide resin is used for the resin film 23 and the cover layer 36 a , 36 b .
  • this film it is possible to use a film made by adding nonconductive filler to polyetheretherketone resin and polyetherimide resin. It is also possible to use only one of polyetheretherketone (PEEK) and polyetherimide (PEI).
  • thermoplastic polyimide or liquid crystal polymer is applicable as well. It is preferable to use a resin film having 1-1000 MPa modulus of elasticity at the heating temperature during the hot-pressing and having thermal resistance needed for soldering in later processes.
  • copper is used as metal making up the conductor pattern 22 .
  • the conductor pattern 22 does not have to be entirely made of the metal that diffuses mutually with tin (the first metal) contained in the conductive compound 51 .
  • a conductor pattern having a plated layer thereon which is made of a metal such as silver and gold and diffuses mutually with tin (the first metal) contained in the conductive compound 51 .
  • Any conductor patterns are applicable as long as the patterns have metal that can diffuse mutually with tin (the first metal) contained in the conductive compound 51 at the position thereof correspondent to the via-hole 24 .
  • the printed wiring board 100 consists of four layers. However, as a matter of course, as long as the board 100 consists of a plurality of conductor pattern layers, the number thereof is not limited.

Abstract

Conductive paste containing tin particles and silver particles is packed in a substantially cylindrical via hole formed in a thermoplastic resin film that interposes between conductor patterns and is hot-pressed from both sides. When the metal particles contained in the conductive paste are sintered to form a unified conductive compound, the volume of the conductive paste shrinks. Synchronously, the resin film around the via-hole protrudes into the via-hole. Therefore, the shape of the side wall on the cross-section of the conductive compound provides an arch shape, and a side wall adjacent to a junction part of the conductive compound, which contacts the conductor pattern, is formed with an inclination. Therefore, it is possible to prevent the stress concentration due to deformation of the board.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based on and incorporates herein by reference Japanese Patent Applications NO. 2000-395601 filed Dec. 26, 2000, No. 2001-94176 filed Mar. 28, 2001, and No. 2001-204024 filed Jul. 4, 2001.
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a printed wiring board and a manufacturing method thereof, specifically relates to a double-sided printed wiring board and a multilayer printed wiring board with a plurality of electrically-interconnected conductor pattern layers formed thereon and to a manufacturing method thereof.
It is proposed that, in a printed wiring board, an insulator board includes a plurality of conductor patterns and the conductor patterns are interconnected by a conductive compound in a via-hole formed in the insulator board. As a manufacturing method for such a printed wiring board, a method shown in FIG. 12A is proposed. In this method, a substantially cylindrical via-hole 124 is formed in an insulator board 123, which is made of prepreg in B stage status prepared by impregnating a core material such as glass cloth with unset thermosetting resin. A conductive paste 150, which is an interlayer connecting material consisting of metal particles and binder resin made of unset thermosetting resin, is packed in the via-hole 124. Subsequently, the board and conductive foils 122 forming a conductor pattern are laminated.
By hot-pressing this piled body, as shown in FIG. 12B, the conductive paste 150 becomes a unified conductive compound 151 with the setting of the binder resin, and conductive foils 122 forming conductor patterns are interconnected by the substantially cylindrical conductive compound 151 formed in the substantially cylindrical via-hole 124.
In this proposed art, interconnection between the conductive foils 122 forming conductor patterns is achieved with the substantially cylindrical conductive compound 151. Therefore, in a case that the printed wiring board incurs a stress due to deformation such as bending, the conductive compound 151 is likely to incur stress concentration in the vicinity of a junction part 151 b that is a junction part with the conductor pattern (the conductive foil 122). If repeated or large stress concentration is generated in the vicinity of the junction part 151 b, reliability of the interconnection is lowered.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above-mentioned aspects with an object to provide a printed wiring board having reliable interlayer connection and a fabrication method thereof.
To achieve the above object, a printed wiring board has a unified conductive compound in a via-hole. The compound has a side wall adjacent to an area contacting the conductor pattern. The wall has an inclination against the conductor pattern in such a manner that the farther from the conductor patterns on the side wall, the closer to the center axis of the via-hole.
Preferably, the conductive compound is formed such that the cross section thereof on the cross-sectional plane that passes the center axis of the via-hole provides an arch shape.
According to the invention, even in the case that a stress due to deformation such as bending is applied to the printed wiring board, it is possible to prevent the stress from concentrating in the vicinity of a junction part of the conductive compound. Therefore, the reliability of the interconnection avoids becoming worse. The film is made of thermoplastic resin. Therefore, when the conductive compound with the inclination of the side wall is formed, the insulator film is readily deformed plastically and the via-hole is readily formed in a shape conforming to the shape of the conductive compound.
Moreover, when the compound is formed by sintering metal particles, apparent volume is reduced. Therefore, the conductive compound is readily formed with the inclination of the side wall.
The conductor pattern is made of metal. The interlayer connecting material includes first and second metal particles. The first metal particles can form first alloy with the metal making up the conductor pattern. The second metal particles have higher melting point than the heating temperature for interconnecting layers and can form second alloy with the metal making up the first metal particle. The unified conductive compound is formed by hot-pressing the interlayer connecting material in the via-hole between a plurality of conductor patterns. Therefore, the conductor patterns are electrically interconnected with the conductive compound and the interposing solid phase diffusion layer that is formed by the mutual solid phase diffusion between the metal making up the conductor pattern and the first metal in the conductive compound.
Namely, the electrical interconnection between the conductor patterns is not made by mechanical contact so that the interlayer contact resistance hardly changes. Thus, the reliability of the interconnection is certainly enabled to avoid becoming worse.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
FIGS. 1A to 1E are process-by-process cross-sectional views showing production processes of a printed wiring board in the first embodiment of the present invention;
FIGS. 2A and 2B are partially-enlarged schematic views of printed wiring boards respectively after packing a conductive paste in a via-hole and after interconnecting layers in the first embodiment of the present invention;
FIG. 3 is a partially-enlarged view showing schematically the shape of a conductive compound in the first embodiment of the present invention;
FIG. 4 is a graph showing the evaluation result on the adhesion between a copper foil forming the conductor pattern and the conductive compound;
FIG. 5 is a graph showing the change ratio in the via serial resistance of the printed wiring board after reflow-soldering process of the printed wiring board;
FIGS. 6A and 6B are partially-enlarged schematic views showing respectively the states after packing the conductive paste in the via-hole and after interconnecting layers in the second embodiment of the present invention;
FIG. 7 is a cross-sectional view showing an element piling configuration for a multilayer printed wiring board;
FIG. 8 is a cross-sectional view showing another element piling configuration for a multilayer printed wiring board;
FIG. 9 is a cross-sectional view showing other element piling configuration for a multilayer printed wiring board;
FIG. 10 is a cross-sectional view showing other element piling configuration for a multilayer printed wiring board;
FIG. 11 is a cross-sectional view showing other element piling configuration for a multilayer printed wiring board; and
FIGS. 12A and 12B are partially-enlarged schematic views of printed wiring boards respectively after packing a conductive paste in a via-hole and after interconnecting layers in the related art.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, embodiments of the present invention are explained with reference to the drawings.
First Embodiment
In FIG. 1A, a single-sided conductor pattern film 21 is shown as having a plurality of conductor patterns 22 that are defined by means of etching a conductive foil (a copper foil with 18 μm thickness in this embodiment) adhered onto one side of a resin film 23. In this embodiment, a thermoplastic film with 25-75 μm thickness, which is made of a mixture of 65-35% polyetheretherketone resin and 35-65% polyetherimide resin, is used as the resin film 23.
After the conductor pattern 22 is formed, a substantially cylindrical via-hole 24 bottomed with the conductor pattern 22 is formed by exposing the resin film 23 to carbon dioxide laser, as shown in FIG. 1B. During the formation of the via-hole 24, the conductor pattern 22 escapes being dug by the laser by adjusting the power and the exposure period of the carbon dioxide laser and such.
Other than the carbon dioxide laser, excimer laser or the like may be utilized for formation of the via-hole 24. In place of laser, other via-hole formation means such as drilling is applicable. However, hole machining by laser beam is preferable because of capability thereof in fine hole machining with the least damage to the conductor pattern 22.
After the via-hole 24 is formed as shown in FIG. 1B, conductive paste 50 that is a material for interlayer connection is packed in the via-hole 24 as shown in FIG. 1C. The paste is prepared by the steps mentioned below. 60 g of terpineol, which is organic solvent, is added to 300 g of tin particles 61 (first metal particles and shown in FIG. 2A) with 5 μm mean particle size and 0.5 m2/g specific surface and 300 g of silver particles 62 (second metal particles and shown in FIG. 2A) with 1 μm mean particle size and 1.2 m2/g specific surface. The mixture is compounded by a mixer to make it pasty.
After the conductive paste 50 is printed and packed in the via-hole 24 of the single-sided conductor pattern film 21 by a screen printing machine with a metal mask, the terpineol is evaporated at 140-160° C. for 30 minutes. In this embodiment, the screen printing machine is used for packing the conductive paste 50 into the via-hole 24. However, other methods using a dispenser or the like are usable as long as the methods enable reliable packing.
Organic solvents other than terpineol are applicable as a solvent to make a paste. However, organic solvents with 150-300° C. boiling point are preferably used. Organic solvents having the boiling point of 150° C. or lower is likely to increase time-dependent variation of the viscosity of the conductive paste 50. On the other hand, organic solvent having boiling point higher than 300° C. is unfavorable because evaporation time thereof becomes longer.
In this embodiment, the tin particles with 5 μm mean particle size and 0.5 m2/g specific surface and the silver particles with 1 μm mean particle size and 1.2 m2/g specific surface are used for the conductive paste 50. The metal particles preferably have 0.5-20 μm mean particle size and 0.1-1.5 m2/g specific surface.
In the case that the metal particles have mean particle size smaller than 0.5 μm or specific surface larger than 1.5 m2/g, a lot of organic solvent is required for adjusting the paste to suitable viscosity for via-hole packing. Conductive paste containing a lot of organic solvent requires long time for evaporation, and a lot of gas is generated by the heating during interconnecting time period if the evaporation is insufficient. Therefore, voids are likely to be generated in the via-hole 24, and reliability of the interconnection is lowered.
On the other hand, in the case that the metal particles have mean particle size larger than 20 μm or specific surface smaller than 0.1 m2/g, it becomes difficult to pack the paste into the via-hole 24. In addition, the metal particles are likely to be unevenly distributed so that it also becomes difficult to provide the conductive compound 51 made of homogeneous alloy after heating.
Before the conductive paste 50 is packed into the via-hole 24, the surface of the conductor pattern 22 facing the via-hole 24 may be slightly etched or reduced. Thereby, solid phase diffusion described later is preferably done.
On the completion of the packing of the conductive paste 50 into the via-hole 24 and the evaporation thereof, a plurality of single-sided conductor pattern films 21 (four films, for instance) are piled, as shown in FIG. 1D. One pair of single-sided conductor pattern films 21 of the lower side are piled such that the side including the conductor pattern 22 faces downward. The other pair of single-sided conductor pattern films 21 of the upper side are piled such that the side including the conductor pattern 22 faces upward.
Namely, one pair of single-sided conductor pattern films 21 placed inside are piled together such that the side including no conductor pattern 22 faces each other. The other pair of single-sided conductor pattern films 21 are piled such that the side including conductor pattern 22 of one film faces the side including no conductor pattern 22 of the other film.
A cover layer 36 a that is a resist film covering the conductor pattern 22 on the top layer is piled on the piled single-sided conductor pattern films 21 having a plurality of layers, and so is a cover layer 36 b that is another resist film covering the conductor pattern 22 on the bottom layer.
The cover layer 36 a is machined to provide a hole 39 a through which an electrode 32 is exposed in a predetermined position of the conductor pattern 22 on the top layer, and so is the cover layer 36 b to provide another hole 39 b through which an electrode 37 is exposed in a predetermined position of the conductor pattern 22 on the bottom layer. In this embodiment, the same resin film as for the resin film 23, which is a thermoplastic film with 25-75 μm thickness, made of a mixture of 65-35% polyetheretherketone resin and 35-65% polyetherimide resin, is used for the cover layers 36 a and 36 b.
After piling the single-sided conductor pattern films 21 and the cover layer 36 a, 36 b as shown in FIG. 1D, the piled unit is hot-pressed from the top and bottom surfaces thereof by a vacuum hot-press machine. In this embodiment, the piled unit is pressed for 10-20 minutes under 2-10 MP pressure with heating temperature of 240-350° C.
Thereby, as shown in FIG. 1E, each single-sided conductor pattern film 21 and the cover layer 36 a, 36 b are bonded together. While the resin films 23 and the cover layer 36 a, 36 b thermally fuse together to be unified, the conductor patterns 22 adjacent to the conductive paste 50 in the via-hole 24 are interconnected and a multilayer printed wiring board 100 with the electrode 32 on one side and the electrode 37 on the other side is provided. The resin film 23 and the cover layer 36 a, 36 b are made of the same thermoplastic resin so that both are firmly unified by being thermally softened and pressed.
Hereinafter, the mechanism of the interconnection is explained with reference to FIGS. 2A and 2B. When the paste 50 is heated at 240-350° C., the tin particles 61 melt and stick to the surface of the silver particles 62 because the melting point of the tin particles 61 and that of the silver particles 62 are 232° C. and 961° C., respectively. As the heating is continued in this condition, fused tin begins defusing from the surface of the silver particles and an alloy (melting point 480° C.) is made between tin and silver. In this case, the conductive paste is under 2-10 MP pressure. Therefore, as shown in FIG. 2B, the conductive compound 51 is formed in the via-hole 24 with the tin-silver alloy formation.
In addition, while the conductive compound 51 is formed in the via-hole 24, this pressurized conductive compound 51 is pressed toward the bottom of the via-hole 24. Thereby, tin contained in the conductive compound 51 and copper contained in the copper foil forming the conductor pattern 22 diffuse mutually, and a solid phase diffusion layer 52 is formed at the interface between the conductive compound 51 and the conductor pattern 22.
Although not shown in FIGS. 2A and 2B, the solid phase diffusion layer is formed similarly at the interface between the conductor pattern 22 at the lower side of the via-hole 24 and the conductive compound 51. Therefore, both conductor patterns 22 at the top and bottom of the via-hole 24 are electrically interconnected by the unified conductive compound 51 and the solid phase diffusion layer 52. In this way, while the conductor patterns 22 are interconnected by the hot-press with the vacuum hot-press machine, the conductive compound 51 continues to be sintered even after the solid phase diffusion layer 52 is formed, and the conductive compound 51 shrinks. In this embodiment, the conductive compound 51 is smaller in volume by 10-20% than the conductive paste 50.
Because the insulator resin film 23 is hot-pressed by the vacuum hot-press machine, the resin film 23 is deformed in an extendable direction and the resin film 23 adjacent to the via-hole 24 is deformed to protrude out into the via-hole 24. The modulus of elasticity of the resin film 23 is reduced to about 5-40 MPa while being hot-pressed by the vacuum hot-press machine. If the resin film 23 with reduced modulus of elasticity is pressed in this way, substantially homogeneous pressure (hydrostatic pressure) is generated in the insulator resin film 23.
The pressing is continued with substantially homogeneous pressure provided in the resin film 23, and the resin film 23 adjacent to the via-hole 24 is deformed plastically to protrude out into the via-hole 24. The protrusion amount of the resin film 23 into the via-hole becomes larger at the central part (the central part of the via-hole 24 in the direction of the center) of the via-hole 24 than at the end part (the end part of the via-hole 24 in the direction of the center axis) connected to the conductor pattern 22.
Namely, as shown in FIG. 3, the side wall of the via-hole 24, which is substantially cylindrical before hot-pressing, is deformed such that the shape of the side wall on the cross-section that passes the center axis of the via-hole 24 provides an arch shape by letting the resin film 23 protrude into the via-hole 24 as described above.
At that time, the apparent volume of the compound 51 decreases as the sintering proceeds. While shrinking, the compound 51 is pushed by the resin film 23 that protrudes such that the cross-section shape thereof provides an arch shape. Therefore, the deformation of the resin film 23 in the direction of the protrusion into the via-hole 24 proceeds synchronously with the shrinkage of the conductive compound 51 such that the side wall of the via-hole 24 is always in contact with the conductive compound 51. As a result, as shown in FIG. 3, the side wall of the conductive compound 51 is formed to provide an arch shape on the cross-section that passes the center axis of the via-hole 24.
Namely, a side wall 51 a of the conductive compound 51 is formed with the inclination against the conductor pattern 22 in such a manner that the farther from the conductor patterns 22, the closer to the center axis of the via-hole 24.
The modulus of elasticity of the resin film 23 during the hot-pressing process is preferably 1-1000 MPa. If the modulus of elasticity is larger than 1000 MPa, it is difficult to provide homogeneous internal pressure in the resin film 23 and difficult to bond the resin films 23 together by fusing thermally. On the other hand, if the modulus of elasticity is smaller than 1 MPa, the resin film flows thermally too readily to hold a shape of the printed board 100.
The volume reduction ratio of the conductive compound 51 to the conductor paste 50 is preferably 5% or more. If the reduction ratio is smaller than 5%, it is difficult to form the side wall 51 a of the conductive compound 51 with an inclination large enough against the conductor pattern 22.
According to the configuration and fabrication method in the first embodiment, even in the case that a stress due to a deformation such as bending is applied to the printed wiring board 100, it is possible to prevent the stress concentration in the junction part 51 b shown in FIG. 3, because the side wall 51 a of the conductive compound 51 is formed with an inclination. Moreover, any other part of the conductive compound 51 is likely to incur less stress concentration because the side wall of the conductive compound 51 is formed to provide an arch shape on the cross-section that passes the center axis of the via-hole 24. Therefore, the reliability of the interconnection is enabled to avoid becoming worse.
A plurality of conductor patterns 22 of the printed wiring board 100 are electrically interconnected with both conductive compound 51 including the tin-silver alloy formed by sintering and the solid phase diffusion layer 52 made between tin in the conductive compound 51 and copper making up the conductor pattern 22. Therefore, the electrical connection of the conductor patterns 22 is not achieved by mechanical contact so that the interlayer contact resistance hardly changes. Thus, the reliability of the interconnection is further prevented from becoming worse.
In addition, piled unification of the single-sided conductor pattern films 21 and the cover layer 36 a, 36 b and interconnection of the conductor patterns 22 are conducted simultaneously by the hot-press. Therefore, the number of fabrication processes for the printed wiring board 100 can be reduced and so can the fabrication costs of the board.
In this embodiment, the metal components of the conductive paste 50 are 50 weight % tin and 50 weight % silver. Tin content in the metal components is preferably 20-80%.
FIG. 4 shows variation of the adhesion between the copper foil forming the conductor pattern 22 and the conductive compound when the ratio of tin to silver in the conductive paste 50 is varied. The adhesion evaluation has been conducted as follows. The same tin particles and silver particles as used for the conductive paste 50 in this embodiment are used as metal components. Terpineol is added to the metal components by the amount equivalent to 10 weight % of the metal components and the mixture is treated to provide a paste. The paste is printed on the shiny side of a copper foil and evaporated on the conditions described above. Subsequently, another copper foil is piled on the evaporated paste such that the mat side thereof contacts the paste. The two copper foils interposed by a conductive compound therebetween are bonded by the hot-press on the conditions described above.
The shiny side of one copper foil and the mat side of the other copper foil are bonded, because a via packed with the conductive compound in the via-hole thereof is formed between those sides when the single-sided conductor pattern films are piled in the fabrication of the printed wiring board such that each film faces the same direction. The bonded two copper foils are peeled at the speed of 10 mm/min and the peeling strength is defined as the adhesion therebetween.
It turns out that tin content between 20-80% provides preferable adhesion more than 1.0 N/mm, which is an adhesion between the insulator and the copper foil. The fracture mode in the peeling in 20-80% tin content range is not the boundary peeling between the copper foil and the conductive compound, but the internal fracture of the conductive compound. This means that a solid phase diffusion layer more robust than the conductive compound is formed between the copper foil and the conductive compound.
FIG. 5 shows the change ratio of the serial via resistance to the via initial serial resistance after reflow-soldering process of the printed wiring board 100 when the ratio of tin to silver in the conductive paste 50 packed in the via-hole 24 are varied.
The evaluation has been conducted as follows. The same tin particles and silver particles as used for the conductive paste 50 described above in this embodiment are used as metal components. Terpineol is added to the metal components by the amount equivalent to 10 weight % of the metal components and the mixture is treated to provide a paste. The paste 50 is packed in the via-hole 24 of a single-sided conductor pattern film and evaporated on the conditions described above. A copper foil is piled on the insulator side of the single-sided conductor pattern film. The piled unit is hot-pressed on the conditions described above. A double-sided board having conductor patterns for measuring the serial resistance of the via is prepared in this way.
Afterward, the via serial resistances of the double-sided board are measured as prepared and after the board is passed through a reflowing process with the temperature of 250° C. and time period of 5 minutes. The resistance change ratio therebetween is calculated from the measured values.
It turns out that the tin content between 20-80% ensures that the resistance change ratio by the reflowing is 20% or smaller, which is generally the maximum value to provide preferable reliability. Therefore, it is possible to provide a printed wiring board with excellent connecting reliability if the printed wiring board is manufactured by using, as an interlayer connecting material, the conductive paste 50 with 20-80% tin content in the metal components, as described above.
In this embodiment, the conductive paste 50 contains the tin particles 61 and the silver particles 62, and the conductive compound 51 is formed by alloying and sintering both metals. However, the conductive paste 50 need not necessarily be a material whose metal particles are sintered. For example, the conductive paste 50 may be a material that contains metal particles and unset thermosetting resin as binder resin and becomes a conductive compound whose metal particles are supported by set thermosetting resin.
As long as the volume of a conductive compound is reduced (preferably reduced by more than 5%) due to the shrinkage of a thermosetting resin in comparison with that of a conductive paste, it is possible to form a side wall of the conductive compound with the inclination against the conductor pattern in such a manner that the farther from the conductor patterns, the closer to the center axis of the via-hole. In this case as well, it is possible to prevent a stress from concentrating in the vicinity of a junction part between the conductive compound and the conductor pattern. However, in this case, the interconnection is based on contact conduction so that the embodiment described above is more preferable from the standpoint of reliability.
In this embodiment, silver particles are used as the second metal particles. However, any other metal particles may be used as long as the particles do not fuse during the interconnecting period and form an alloy with tin that is the first metal particles. Applicable metals are copper (mp 1083° C.), gold (mp 1063° C.), platinum (mp 1769° C.), palladium (mp 1552° C.), nickel (mp 1453° C.), zinc (mp 419° C.) or the like. As the second metal particles, these may be used either separately or in combination on a case-by-case basis.
In this embodiment, metal particles contained in the conductive paste 50 are only the tin particles 61 and the silver particles 62. However, for the purpose of improving shape-holding capability of the conductive paste 50, metal particles with low melting point (e.g., iridium particles) or with about 1-100 nm particle particle size (e.g., silver) may be added to the paste 50. Thereby, it is possible to keep the shape-holding capability of the conductive paste 50 better until the interlayer connecting process.
Moreover, other metal particles that do not form an alloy with tin may be added for the sake of adjusting the thermal expansion coefficient of the conductive compound 51 close to that of the insulator resin film 23. Other than metal particles, nonconductive inorganic filler or the like may be added. However, it is unfavorable to add too much to unify the conductive compound 51.
In this embodiment, the conductive paste 50 consists of the metal particles 61 and 62 and organic solvent. A dispersing agent may be added to the conductive paste 50 by an amount equivalent to 0.01-1.5 weight % of the total solid components of the conductive paste 50. This makes it easier to disperse homogeneously the metal particles in the conductive paste 50. Dispersing agent content less than 0.01 weight % provides scarcely dispersion effect, and dispersing agent content more than 1.5 weight % hinders the unification of the conductive compound 51 by sintering. It is possible to use phosphoric ester and stearic ester or the like as the dispersing agent.
In this embodiment, instead of pasty material for the conductive paste 50, grainy material is applicable as long as it is possible to pack the material in the via-hole 24.
Second Embodiment
It is possible to use conductive paste including alloy particles that consist of first metal making up the first metal particles and second metal making up the second metal particles. For example, as shown in FIG. 6A, conductive paste 150, which consists of organic solvent and alloy particles 162 including 50 weight % tin and 50 weight % silver, is packed in the via-hole 24 of the single-sided conductor pattern film 21 and evaporated. Afterward, the single-sided conductor pattern films 21 are preferably piled and the piled unit is hot-pressed from both sides thereof for forming the unified conductive compound 51 by sintering the alloy particles in the via-hole 24.
The conductive compound 51 is pressurized while being pressed in the via-hole 24 so that the compound 51 is pressed toward the surface of the conductor pattern 22, which makes up the bottom of the via-hole 24. Thereby, tin contained in the conductive compound 51 and copper of the copper foil forming the conductor pattern 22 diffuse mutually in solid phase to form the solid phase diffusion layer 52 at the boundary between the conductive compound 51 and the conductor pattern 22.
When the sintering of the alloy 162 proceeds as described above, the resin film 23 is deformed such that the film 23 protrudes into the via-hole 24 as the volume of the conductive compound 51 decreases. Therefore, the same effect as in the first embodiment is provided.
At that time, as described above, the second metal is not limited to silver. Copper, gold, platinum, palladium, nickel, zinc or the like are applicable as the second metal particles either separately or in combination. In this embodiment, the metal components of the conductive paste 150 are 50 weight % tin and 50 weight % silver. As well as in the first embodiment, tin content of the metal components is preferably 20-80%.
Furthermore, in the embodiments described above, the single-sided conductor pattern films 21 are piled, as shown in FIG. 1D, in the fabrication processes of the printed wiring board 100. However, piling configuration is not limited to this one, but any other configurations may be used as long as the configurations are for providing multilayer or double-sided printed wiring board requiring interlayer connection.
For example, a configuration shown in FIG. 7 is possible. In this configuration, a multilayer printed wiring board is made with steps of piling together a single-sided conductor pattern film 71 having a copper foil conductor pattern covering a whole side thereof, single-sided conductor pattern films 21 and a copper foil 81, then hot-pressing the piled unit, and afterward defining the copper foils on both sides.
Another configuration shown in FIG. 8 is possible as well. In this configuration, a multilayer printed wiring board is made with steps of piling together single-sided conductor pattern films 21 and a double-sided film 91, and afterward hot-pressing the piled unit.
Moreover, other configuration shown in FIG. 9 is possible as well. In this configuration, a multilayer printed wiring board is made with steps of piling the resin film 23 on both sides of the double-sided film 91, then piling the copper foils 81 to the piled unit, and afterward hot-pressing the finally piled body.
Other configuration shown in FIG. 10 is possible as well. In this configuration, a multilayer printed wiring board is made with steps of piling the copper foils 81 on the resin film 23, then hot-pressing the piled unit, and afterward defining the copper foils on both sides.
Other configuration shown in FIG. 11 is possible as well. In this configuration, a multilayer printed wiring board is made with steps of piling together the single-sided conductor pattern film 71 and the copper foil 81, then hot-pressing the piled unit, and afterward defining the copper foils on both sides.
In the embodiments described above, a resin film made of a mixture of 65-35% polyetheretherketone resin and 35-65% polyetherimide resin is used for the resin film 23 and the cover layer 36 a, 36 b. Instead of this film, it is possible to use a film made by adding nonconductive filler to polyetheretherketone resin and polyetherimide resin. It is also possible to use only one of polyetheretherketone (PEEK) and polyetherimide (PEI).
In addition, thermoplastic polyimide or liquid crystal polymer is applicable as well. It is preferable to use a resin film having 1-1000 MPa modulus of elasticity at the heating temperature during the hot-pressing and having thermal resistance needed for soldering in later processes.
In the embodiments described above, copper is used as metal making up the conductor pattern 22. However, other than copper, it is possible to use other metals that diffuse mutually in the solid phase with tin contained in the conductive compound 51. In addition, the conductor pattern 22 does not have to be entirely made of the metal that diffuses mutually with tin (the first metal) contained in the conductive compound 51. It is possible to use a conductor pattern having a plated layer thereon, which is made of a metal such as silver and gold and diffuses mutually with tin (the first metal) contained in the conductive compound 51. Any conductor patterns are applicable as long as the patterns have metal that can diffuse mutually with tin (the first metal) contained in the conductive compound 51 at the position thereof correspondent to the via-hole 24.
In the embodiments described above, the printed wiring board 100 consists of four layers. However, as a matter of course, as long as the board 100 consists of a plurality of conductor pattern layers, the number thereof is not limited.

Claims (12)

What is claimed is:
1. A printed wiring board comprising:
an insulator board having a via-hole, a first surface and a second surface that is opposite the first surface;
first and second conductor patterns that are respectively located on the first surface and the second surface to cover the via-hole, and that include a metal;
a unified conductive compound provided in the via-hole and including a first metal and a second metal having a higher melting point than a heating temperature required for interconnecting the first and second conductor patterns; and
first and second solid phase diffusion layers formed from the metal in the first and second conductor patterns and the first metal in the unified conductive compound diffused into the metal in the first and second conductor patterns, the first and second solid diffusion layers located between the unified conductive compound and the first and second conductor patterns;
wherein a sidewall of the unified conductive compound in the via-hole is concave in shape and approaches a center axis of the via-hole approximately halfway between the first surface and the second surface of the insulator board; and
the first and second conductor patterns are electrically interconnected by the unified conductive compound and the first and second solid phase diffusion layers.
2. The printed wiring board as in claim 1, wherein the side wall of the unified conductive compound has an arch shape between the first and second solid phase diffusion layers on a cross-sectional plane passing through a center axis of the via-hole.
3. The printed wiring board as in claim 1, wherein the unified conductive compound is a sintered metal made from metal particles.
4. The printed wiring board as in claim 1, wherein the first metal is tin and the second metal is silver.
5. A printed wiring board comprising:
an insulator board having a via-hole, a first surface and a second surface that is opposite to the first surface;
first and second conductor patterns, that include a metal and that are respectively located on the first surface and the second surface to cover the via-hole;
a unified conductive compound, that is located in the via-hole that includes a first metal and a second metal that has a higher melting point than a heating temperature required for interconnecting the first and second conductor patterns; and
first and second solid phase diffusion layers, that are made of the metal included in the first and second conductor patterns and the first metal, wherein each of the first and second solid phase diffusion layers is located between the unified conductive compound and one of the conductor patterns, and wherein the first and second conductor patterns are electrically interconnected by the unified conductive compound and the first and second solid phase diffusion layers.
6. The printed wiring board as in claim 5, wherein the unified conductive compound is an alloy that includes sintered metals.
7. The printed wiring board as in claim 5, wherein the first metal is tin and the second metal is silver.
8. A printed wiring board comprising:
an insulator board having a via-hole, a first surface and a second surface that is opposite to the first surface;
first and second conductor patterns, that include a metal and that are respectively located on the first surface and the second surface to cover the via-hole; and
a unified conductive compound that is located in the via-hole and that includes a first metal and a second metal that has a higher melting point than a heating temperature required for interconnecting the conductor pattern, wherein:
the unified conductive compound is an alloy that includes sintered metals including the first metal, and other metal particles including the second metal; and
the first and second conductor patterns are electrically interconnected by the unified conductive compound.
9. The printed wiring board as in claim 8, wherein the first metal is tin and the second metal is silver.
10. The printed wiring board as in claim 8, wherein the unified conductive compound further comprises first and second solid phase diffusion layers between and electrically connecting the unified conductive compound and the first and second conductor patterns; and
wherein a sidewall of the unified conductive compound in the via-hole between the first and second solid phase diffusion layers is concave and approaches a center axis of the via-hole approximately halfway between the first surface and the second surface has a shape such that the farther from the conductor patterns on the sidewall, the closer the sidewall is to a center axis of the via hole.
11. The printed wiring board of claim 1, wherein the sidewall of the unified conductive compound between the first and second solid phase diffusion layers follows a convex protrusion of the insulator board that is farthest from the center axis of the via-hole near the first surface and the second surface and closest to the center axis of the via-hole approximately halfway between the first surface and the second surface.
12. The printed wiring board of claim 1, wherein the sidewall of the unified conductive compound is inclined with respect to the first and second conductor patterns, wherein stress concentrations are avoided at an area of an electrical contact between the first and second conductor patterns and the unified conductive compound.
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030039811A1 (en) * 2001-01-15 2003-02-27 Toshio Sugawa Circuit board and production method thereof
US20040066633A1 (en) * 2000-12-26 2004-04-08 Yoshitarou Yazaki Method for manufacturing printed wiring board
US20050230667A1 (en) * 2002-09-04 2005-10-20 Michinori Komagata Conductive adhesive and circuit using the same
US20060042832A1 (en) * 2004-08-27 2006-03-02 Kiyoshi Sato Multilayer circuit board and method of producing the same
US20060046394A1 (en) * 2004-09-01 2006-03-02 Nirmal Ramaswamy Forming a vertical transistor
US20060274510A1 (en) * 2004-11-09 2006-12-07 Masakazu Nakada Multilayer wiring board and fabricating method of the same
US20070062723A1 (en) * 2005-09-02 2007-03-22 Samsung Electro-Mechanics Co., Ltd. Method of forming circuit pattern on printed circuit board
US20070170593A1 (en) * 2006-01-26 2007-07-26 Fujitsu Limited Product including conductor made of zinc or zinc aluminum alloy
US20080017409A1 (en) * 2006-06-05 2008-01-24 Denso Corporation Multilayer board
US20110253431A1 (en) * 2010-04-20 2011-10-20 Snu R&Db Foundation Printed circuit substrate and method of manufacturing the same
US20140003111A1 (en) * 2012-07-02 2014-01-02 Denso Corporation Electric power converter
US20180213643A1 (en) * 2015-11-10 2018-07-26 Murata Manufacturing Co., Ltd. Resin multilayer substrate and method of manufacturing the same
US20220087033A1 (en) * 2020-09-17 2022-03-17 Unimicron Technology Corp. Circuit board and manufacturing method thereof
CN114205989A (en) * 2020-09-17 2022-03-18 欣兴电子股份有限公司 Circuit board and method for manufacturing the same

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3473601B2 (en) * 2000-12-26 2003-12-08 株式会社デンソー Printed circuit board and method of manufacturing the same
EP1571680B1 (en) * 2002-12-09 2012-09-12 Panasonic Corporation Electronic part with external electrode
US6992001B1 (en) * 2003-05-08 2006-01-31 Kulicke And Soffa Industries, Inc. Screen print under-bump metalization (UBM) to produce low cost flip chip substrate
DE10350568A1 (en) * 2003-10-30 2005-02-10 Ticona Gmbh Production of foil cables or multi-layered circuit boards for printed circuits comprises using a thermoplastic plastic support film absorbing a prescribed wavelength with strip conductors or a thermoplastic circuit board
JP3997991B2 (en) 2004-01-14 2007-10-24 セイコーエプソン株式会社 Electronic equipment
US8257795B2 (en) 2004-02-18 2012-09-04 Virginia Tech Intellectual Properties, Inc. Nanoscale metal paste for interconnect and method of use
US20070183920A1 (en) * 2005-02-14 2007-08-09 Guo-Quan Lu Nanoscale metal paste for interconnect and method of use
KR100687394B1 (en) * 2004-09-24 2007-02-27 산에이카가쿠 가부시키가이샤 Multilayer circuit substrate and method of producing the same
JP2006128519A (en) * 2004-10-29 2006-05-18 Tdk Corp Method of manufacturing multilayer substrate
US7334323B2 (en) * 2005-07-11 2008-02-26 Endicott Interconnect Technologies, Inc. Method of making mutilayered circuitized substrate assembly having sintered paste connections
US7510323B2 (en) * 2006-03-14 2009-03-31 International Business Machines Corporation Multi-layered thermal sensor for integrated circuits and other layered structures
US8344523B2 (en) * 2006-05-08 2013-01-01 Diemat, Inc. Conductive composition
JP2010062339A (en) * 2008-09-04 2010-03-18 Dainippon Printing Co Ltd Component built-in wiring board, and method of manufacturing component built-in wiring board
US8161637B2 (en) * 2009-07-24 2012-04-24 Ibiden Co., Ltd. Manufacturing method for printed wiring board
JP5828203B2 (en) * 2009-09-03 2015-12-02 大日本印刷株式会社 Printed wiring board and method for manufacturing printed wiring board
JP5307669B2 (en) 2009-09-09 2013-10-02 東京エレクトロン株式会社 Method for manufacturing semiconductor device and method for obtaining electrical connection
KR101153675B1 (en) * 2009-09-14 2012-06-18 삼성전기주식회사 Printed Circuit Board and Manufacturing Method Thereof
US10544483B2 (en) 2010-03-04 2020-01-28 Lockheed Martin Corporation Scalable processes for forming tin nanoparticles, compositions containing tin nanoparticles, and applications utilizing same
KR101141385B1 (en) 2010-08-13 2012-05-03 삼성전기주식회사 Repairing method of probe board and probe board using thereof
US8572840B2 (en) * 2010-09-30 2013-11-05 International Business Machines Corporation Method of attaching an electronic module power supply
WO2012084291A1 (en) * 2010-12-21 2012-06-28 Microconnections Sas Method of manufacturing a surface mounted device and corresponding surface mounted device
US8785790B2 (en) * 2011-11-10 2014-07-22 Invensas Corporation High strength through-substrate vias
JP5874697B2 (en) 2013-08-28 2016-03-02 株式会社デンソー Multilayer printed circuit board and manufacturing method thereof
WO2015170539A1 (en) 2014-05-08 2015-11-12 株式会社村田製作所 Resin multilayer substrate and method for producing same
KR101823194B1 (en) 2014-10-16 2018-01-29 삼성전기주식회사 Chip electronic component and manufacturing method thereof
DE102015226607A1 (en) * 2015-12-23 2017-06-29 Robert Bosch Gmbh Method for producing a line section of a hydraulic line
KR101832607B1 (en) 2016-05-13 2018-02-26 삼성전기주식회사 Coil component and manufacturing method for the same
US10349520B2 (en) * 2017-06-28 2019-07-09 Catlam, Llc Multi-layer circuit board using interposer layer and conductive paste
JP2019067994A (en) * 2017-10-04 2019-04-25 トヨタ自動車株式会社 Multilayer substrate and manufacturing method thereof
US10645808B2 (en) * 2018-02-22 2020-05-05 Apple Inc. Devices with radio-frequency printed circuits
US10827624B2 (en) * 2018-03-05 2020-11-03 Catlam, Llc Catalytic laminate with conductive traces formed during lamination
JP7075785B2 (en) * 2018-03-08 2022-05-26 スタンレー電気株式会社 Circuit boards, electronic circuit devices, and methods for manufacturing circuit boards

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4221925A (en) * 1978-09-18 1980-09-09 Western Electric Company, Incorporated Printed circuit board
US4303715A (en) * 1977-04-07 1981-12-01 Western Electric Company, Incorporated Printed wiring board
US5227588A (en) * 1991-03-25 1993-07-13 Hughes Aircraft Company Interconnection of opposite sides of a circuit board
JPH07176846A (en) 1993-10-29 1995-07-14 Matsushita Electric Ind Co Ltd Composition of conductor paste for filling via hole, both-sided and multilayered printed board using it, and its manufacture
US5473120A (en) * 1992-04-27 1995-12-05 Tokuyama Corporation Multilayer board and fabrication method thereof
US5744758A (en) * 1995-08-11 1998-04-28 Shinko Electric Industries Co., Ltd. Multilayer circuit board and process of production thereof
US5977490A (en) 1993-10-29 1999-11-02 Matsushita Electric Industrial Co., Ltd. Conductive paste compound for via hole filling, printed circuit board which uses the conductive paste, and method of manufacturing the same
US6087597A (en) * 1994-07-22 2000-07-11 Nec Corporation Connecting member and a connecting method with ball and tapered via
US6329610B1 (en) * 1997-06-03 2001-12-11 Kabushiki Kaisha Toshiba Hybrid wiring board, semiconductor apparatus, flexible substrate, and fabrication method of hybrid wiring board

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5314788A (en) * 1986-01-24 1994-05-24 Canon Kabushiki Kaisha Matrix printed board and process of forming the same
US5031308A (en) * 1988-12-29 1991-07-16 Japan Radio Co., Ltd. Method of manufacturing multilayered printed-wiring-board
US5078372A (en) * 1989-10-12 1992-01-07 Fitzpatrick John P Quick change vise jaw
JPH0567869A (en) * 1991-09-05 1993-03-19 Matsushita Electric Ind Co Ltd Method of bonding electric part, module and multilayer board
JP2601128B2 (en) * 1992-05-06 1997-04-16 松下電器産業株式会社 Method of manufacturing circuit forming substrate and circuit forming substrate
US5439164A (en) * 1992-06-05 1995-08-08 Matsushita Electric Industrial Co., Ltd. Methods for joining copper or its alloys
JP3428070B2 (en) * 1993-06-07 2003-07-22 株式会社東芝 Manufacturing method of printed wiring board
US5359767A (en) * 1993-08-26 1994-11-01 International Business Machines Corporation Method of making multilayered circuit board
JP2783751B2 (en) * 1993-12-21 1998-08-06 富士通株式会社 Method for manufacturing multilayer ceramic substrate
JP3512225B2 (en) * 1994-02-28 2004-03-29 株式会社日立製作所 Method for manufacturing multilayer wiring board
FR2722639B1 (en) * 1994-07-18 1996-08-30 Solaic Sa METHOD FOR ESTABLISHING AN ELEXTRIC LINK BETWEEN TWO PRINTED CIRCUITS LOCATED ON THE OPPOSITE FACES OF A WAFER, AND ELECTRONIC CARD COMPRISING SUCH A LINK
JPH08148828A (en) 1994-11-18 1996-06-07 Hitachi Ltd Thin film multilayered circuit board and its manufacture
DE69634597T2 (en) * 1995-11-17 2006-02-09 Kabushiki Kaisha Toshiba, Kawasaki MULTILAYERED PCB, PRE-PRODUCED MATERIAL FOR THIS PCB, METHOD FOR PRODUCING A MULTILAYER PCB, PACKAGING OF ELECTRONIC COMPONENTS AND METHOD FOR PRODUCING VERTICAL, ELECTRICALLY CONDUCTIVE CONNECTIONS
CA2196024A1 (en) * 1996-02-28 1997-08-28 Craig N. Ernsberger Multilayer electronic assembly utilizing a sinterable composition and related method of forming
JPH1081857A (en) 1996-09-05 1998-03-31 Hitachi Cable Ltd Double-sided adhesive tape, lead frame and integrated circuit
US5997490A (en) * 1997-02-12 1999-12-07 Exogen, Inc. Method and system for therapeutically treating bone fractures and osteoporosis
US5829762A (en) * 1997-04-21 1998-11-03 Power Tool Holders Incorporated Chuck with locking unit
JPH11204943A (en) 1998-01-08 1999-07-30 Hitachi Ltd Electronic circuit board and manufacture thereof
JP3187373B2 (en) * 1998-07-31 2001-07-11 京セラ株式会社 Wiring board
JP2000138457A (en) * 1998-11-02 2000-05-16 Kyocera Corp Multilayer interconnection board and its manufacture
US6207259B1 (en) * 1998-11-02 2001-03-27 Kyocera Corporation Wiring board
US6196536B1 (en) * 1999-03-09 2001-03-06 Paul H. Hintze Grip set for an adjustable vice
JP2001077533A (en) 1999-09-07 2001-03-23 Nitto Denko Corp Multilayer wiring substrate
JP3867523B2 (en) * 2000-12-26 2007-01-10 株式会社デンソー Printed circuit board and manufacturing method thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4303715A (en) * 1977-04-07 1981-12-01 Western Electric Company, Incorporated Printed wiring board
US4221925A (en) * 1978-09-18 1980-09-09 Western Electric Company, Incorporated Printed circuit board
US5227588A (en) * 1991-03-25 1993-07-13 Hughes Aircraft Company Interconnection of opposite sides of a circuit board
US5473120A (en) * 1992-04-27 1995-12-05 Tokuyama Corporation Multilayer board and fabrication method thereof
JPH07176846A (en) 1993-10-29 1995-07-14 Matsushita Electric Ind Co Ltd Composition of conductor paste for filling via hole, both-sided and multilayered printed board using it, and its manufacture
US5977490A (en) 1993-10-29 1999-11-02 Matsushita Electric Industrial Co., Ltd. Conductive paste compound for via hole filling, printed circuit board which uses the conductive paste, and method of manufacturing the same
US6087597A (en) * 1994-07-22 2000-07-11 Nec Corporation Connecting member and a connecting method with ball and tapered via
US5744758A (en) * 1995-08-11 1998-04-28 Shinko Electric Industries Co., Ltd. Multilayer circuit board and process of production thereof
US6329610B1 (en) * 1997-06-03 2001-12-11 Kabushiki Kaisha Toshiba Hybrid wiring board, semiconductor apparatus, flexible substrate, and fabrication method of hybrid wiring board

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040066633A1 (en) * 2000-12-26 2004-04-08 Yoshitarou Yazaki Method for manufacturing printed wiring board
US7188412B2 (en) * 2000-12-26 2007-03-13 Denso Corporation Method for manufacturing printed wiring board
US20030039811A1 (en) * 2001-01-15 2003-02-27 Toshio Sugawa Circuit board and production method thereof
US20040221449A1 (en) * 2001-01-15 2004-11-11 Matsushita Elec. Ind. Co. Ltd. Circuit board and method of manufacturing the same
US20100025099A1 (en) * 2001-01-15 2010-02-04 Panasonic Corporation Circuit board and method of manufacturing the same
US7423222B2 (en) * 2001-01-15 2008-09-09 Matsushita Electric Industrial Co., Ltd. Circuit board and method of manufacturing the same
US20050230667A1 (en) * 2002-09-04 2005-10-20 Michinori Komagata Conductive adhesive and circuit using the same
US20060042832A1 (en) * 2004-08-27 2006-03-02 Kiyoshi Sato Multilayer circuit board and method of producing the same
US20060046394A1 (en) * 2004-09-01 2006-03-02 Nirmal Ramaswamy Forming a vertical transistor
US20060274510A1 (en) * 2004-11-09 2006-12-07 Masakazu Nakada Multilayer wiring board and fabricating method of the same
US7642468B2 (en) * 2004-11-09 2010-01-05 Sony Corporation Multilayer wiring board and fabricating method of the same
US20070062723A1 (en) * 2005-09-02 2007-03-22 Samsung Electro-Mechanics Co., Ltd. Method of forming circuit pattern on printed circuit board
US20070170593A1 (en) * 2006-01-26 2007-07-26 Fujitsu Limited Product including conductor made of zinc or zinc aluminum alloy
US7565739B2 (en) 2006-01-26 2009-07-28 Fujitsu Limited Method of making zinc-aluminum alloy connection
US20080017409A1 (en) * 2006-06-05 2008-01-24 Denso Corporation Multilayer board
US20110253431A1 (en) * 2010-04-20 2011-10-20 Snu R&Db Foundation Printed circuit substrate and method of manufacturing the same
US8410373B2 (en) * 2010-04-20 2013-04-02 Samsung Electro-Mechanics Co., Ltd. Printed circuit substrate and method of manufacturing the same
US20140003111A1 (en) * 2012-07-02 2014-01-02 Denso Corporation Electric power converter
US8958225B2 (en) * 2012-07-02 2015-02-17 Denso Corporation Electric power converter
US20180213643A1 (en) * 2015-11-10 2018-07-26 Murata Manufacturing Co., Ltd. Resin multilayer substrate and method of manufacturing the same
US10743414B2 (en) * 2015-11-10 2020-08-11 Murata Manufacturing Co., Ltd. Resin multilayer substrate and method of manufacturing the same
US20220087033A1 (en) * 2020-09-17 2022-03-17 Unimicron Technology Corp. Circuit board and manufacturing method thereof
CN114205989A (en) * 2020-09-17 2022-03-18 欣兴电子股份有限公司 Circuit board and method for manufacturing the same

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CN1180666C (en) 2004-12-15
US20040066633A1 (en) 2004-04-08
MXPA01013268A (en) 2004-05-21
EP1220589A3 (en) 2004-07-21
KR100529405B1 (en) 2005-11-17
KR20020053002A (en) 2002-07-04
US7188412B2 (en) 2007-03-13
SG108830A1 (en) 2005-02-28
CN1361656A (en) 2002-07-31
US20020079135A1 (en) 2002-06-27
DE60135082D1 (en) 2008-09-11
JP2002359470A (en) 2002-12-13
JP3867523B2 (en) 2007-01-10
TWI290013B (en) 2007-11-11
EP1220589A2 (en) 2002-07-03

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