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Publication numberUS6686212 B1
Publication typeGrant
Application numberUS 10/286,100
Publication date3 Feb 2004
Filing date31 Oct 2002
Priority date31 Oct 2002
Fee statusPaid
Publication number10286100, 286100, US 6686212 B1, US 6686212B1, US-B1-6686212, US6686212 B1, US6686212B1
InventorsJohn F. Conley, Jr., Yoshi Ono, Rajendra Solanki
Original AssigneeSharp Laboratories Of America, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method to deposit a stacked high-κ gate dielectric for CMOS applications
US 6686212 B1
Abstract
A method of forming a layer of high-κ dielectric material in an integrated circuit includes preparing a silicon substrate; depositing a first layer of metal oxide using ALD with a metal nitrate precursor; depositing another layer of metal oxide using ALD with a metal chloride precursor; and completing the integrated circuit.
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Claims(16)
We claim:
1. A method of forming a layer of high-κ dielectric material in an integrated circuit comprising:
preparing a silicon substrate, including forming an H-terminated surface on the silicon substrate;
depositing a first layer of metal oxide using ALD with a metal nitrate precursor;
depositing another layer of metal oxide using ALD with a metal chloride precursor; and
completing the integrated circuit.
2. The method of claim 1 wherein said forming includes exposing the silicon surface to HF.
3. The method of claim 1 wherein said depositing a first layer of metal oxide includes depositing a layer of metal oxide using from one to five ALD cycles.
4. The method of claim 1 wherein said depositing another layer of metal oxide includes depositing a layer of metal oxide using multiple ALD cycles to achieve a desired metal oxide layer thickness.
5. The method of claim 1 which includes selecting a metal oxide taken from the group of metal oxides consisting of HfO2, ZrO2, Gd2O3, La2O3, CeO2, TiO2, Y2O3, Ta2O5 and Al2O3 to be deposited on the silicon substrate.
6. The method of claim 1 wherein said depositing a first layer of metal oxide includes depositing an initial layer of metal oxide having a thickness of between about 0.1 nm to 1.5 nm.
7. The method of claim 1 wherein said depositing another layer of metal oxide includes depositing a layer of metal oxide having a thickness of between about 3 nm to 10 nm.
8. A method of forming a layer of high-κ dielectric gate oxide in an integrated circuit comprising:
preparing a silicon substrate, including forming an H-terminated surface on the silicon substrate;
depositing a first layer of metal oxide using from one to five ALD cycles with a metal nitrate precursor to achieve a desired metal oxide layer thickness;
depositing another layer of metal oxide using multiple ALD cycles with a metal chloride precursor; and
completing the integrated circuit.
9. The method of claim 8 wherein said forming includes exposing the silicon surface to HF.
10. The method of claim 8 which includes selecting a metal oxide taken from the group of metal oxides consisting of HfO2, ZrO2, Gd2O3, La2O3, CeO2, TiO2, Y2O3, Ta2O5 and Al2O3 to be deposited on the silicon substrate.
11. The method of claim 8 wherein said depositing a first layer of metal oxide includes depositing an initial layer of metal oxide having a thickness of between about 0.1 nm to 1.5 nm.
12. The method of claim 8 wherein said depositing another layer of metal oxide includes depositing a layer of metal oxide having a thickness of between about 3 nm to 10 nm.
13. A method of forming a layer of HfO2 high-κ dielectric gate oxide in an integrated circuit comprising:
preparing a silicon substrate, including forming an H-terminated surface on the silicon substrate;
depositing a first layer of HfO2 metal oxide using from one to five ALD cycles with a Hf(NO3)4 precursor to achieve a desired metal oxide layer thickness;
depositing another layer of HfO2 using multiple ALD cycles with a HfCl4 precursor; and
completing the integrated circuit.
14. The method of claim 13 wherein said forming includes exposing the silicon surface to HF.
15. The method of claim 13 wherein said depositing a first layer of metal oxide includes depositing an initial layer of metal oxide having a thickness of between about 0.1 nm to 1.5 nm.
16. The method of claim 13 wherein said depositing another layer of metal oxide includes depositing a layer of metal oxide having a thickness of between about 3 nm to 10 nm.
Description
RELATED APPLICATIONS

This application is related to Ser. No. 09/894,941, filed Jun. 28, 2001, for Method to Initiate the Atomic Layer Deposition of a High Dielelctric Constant Material Directly on a Silicon Substrate.

FIELD OF THE INVENTION

This invention relates to integrated circuit fabrication, and specifically to a method of fabricating a MOS gate dielectric for separating a transistor gate from the channel between the source and drain regions.

BACKGROUND OF THE INVENTION

Thermally grown SiO2 on silicon has been called the “heart and soul” of MOS technology. The Si/SiO2 interface has excellent semiconductor properties including low interface and bulk trapping, thermal stability, high breakdown, etc. With each successive generation of microelectronic technology, however, the thickness of the gate dielectric is scaled. e.g., becomes smaller. As the thickness is scaled below 1.5 nm, problems arise, such as excessive power consumption due to leakage from direct tunneling, boron penetration, reliability concerns, etc. Because of these problems, in the near future, possibly as early as the 80 nm node in 2005, the reign of SiO2 as a gate dielectric may dwindle, eventually coming to an end. SiO2 will likely be replaced by a higher dielectric constant (κ) material, which will have a greater thickness for any given capacitance.

Despite this compelling near term need for an SiO2 substitute, a suitable replacement still has not been discovered. Requirements for this replacement material include lower leakage, low interface traps, low trapped charge, good reliability, good thermal stability, conformal deposition, etc. Promising candidate materials include metal oxides such as HfO2, ZrO2, etc., and other metal oxides.

It is crucial to avoid a low-κ interfacial layer when depositing a high-κ film, as even a very thin low-κ layer can negate most of the benefits of the overlying high-κ material. It is therefore essential to deposit a high-κ material directly on H-terminated silicon layer.

Because of the requirements for conformality and thickness control, atomic layer deposition (ALD) has emerged as one of the most promising deposition techniques for high-κ material. In this technique, dielectric material is built up layer-by-layer in a self-limiting fashion, i.e., the deposition phenominnon where only one monolayer of a chemical species will adsorb onto a given surface. Currently, the leading ALD precursors for depositing metal oxides are metal halides and metal organics. There has also been some experimentation using anhydrous metal nitrates as high-κ dielectric precursors.

A film of ZrO2, deposited using a metal chloride precursor, such as ZrCl4 have shown good insulating properties, including a high-κ dielectric constant and low leakage. A major drawback of ZrCl4, however, is that it does not provide for smooth deposition directly on H-terminated silicon, requires several “incubation” cycles, and requires a thin layer of SiO2 for uniform initiation. These problems must be solved before metal-chloride precursors can be used in production.

A drawback of the metal organic precursors is the potential for organic contamination. Hf(NO3)4 has been demonstrated as a viable ALD precursor, as identified in the above-identified related Application, and in Conley, Jr., et al., Atomic Layer Deposition of Hafnium Oxide Using Anhydrous Hafnium Nitrate, Electrochem. and Sol. State Lett. 5 (5) May, 2002. The primary benefit of Hf(NO3)4 is that it allows deposition initiation directly on H-terminated silicon, resulting in a uniform thin layer. This method has the potential to avoid a low-κ interfacial layer, however, experimental work has shown that HfO2 films deposited via ALD of Hf(NO3)4 have a dielectric constant which is lower than expected, possibly because of the oxygen-rich nature of the films. The “bulk” dielectric properties of the resulting films must be improved before metal-nitrate precursors can find widespread use.

SUMMARY OF THE INVENTION

A method of forming a layer of high-κ dielectric material in an integrated circuit includes preparing a silicon substrate; depositing a first layer of metal oxide using ALD with a metal nitrate precursor; depositing another layer of metal oxide using ALD with a metal chloride precursor; and completing the integrated circuit.

It is an object of the invention to deposit a metal oxide high-κ layer on a silicon substrate.

Another object of the invention is to deposit a metal oxide high-κ layer on a silicon substrate without the requirement of forming a low-κ interfacial layer on the silicon substrate.

A further object of the invention is to provide a high-κ layer having low leakage properties.

This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a silicon substrate having a H-terminated silicon surface.

FIG. 2 depicts the substrate after deposition of an initial HfO2 layer.

FIG. 3 depicts the structure after deposition of the second, or final, HfO2 layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The state-of-the-art technique for gate formation requires oxidation of silicon at high temperatures. It is likely that SiO2 will be replaced by a metal-oxide, such as HfO2, ZrO2, etc. Although a high-κ deposition method has not been established yet, a leading technique is atomic layer deposition (ALD). ALD is typically performed using a single precursor, such as a metal tetrachloride, metal organic, or anhydrous metal nitrate. As described above, these precursors all have significant disadvantages.

Because the leading precursors currently available for ALD of metal oxides have serious drawbacks, the method of the invention incorporates a combination of precursors to improve the quality of the resulting metal-oxide films. The combination of precursors draws on the advantages of each precursor, while minimizing the disadvantages associated with using the precursors. The method of the invention initiates ALD deposition on H-terminated silicon with a single, or up to five, Hf(NO3)4 cycles, followed by ALD deposition of the remaining film to desired thickness using another precursor such as HfCl4. The method of the invention eliminates the need for an initial low-κ interfacial layer, while still achieving a “bulk” film with a high dielectric constant.

The method of the invention incorporates the strengths of individual precursors, in combination, to achieve deposition of a high-κ film directly on H-terminated silicon. A Hf(NO3)4 precursor provides initiation directly on H-terminated silicon and provides a base layer for further ALD using a precursor of HfCl4.

The use of alternate precursors has been previously described, however, use of such alternate precursors has meant using different precursors to interleave different metal oxides, such as HfO2—ZrO2, Ta2O5—HfO2, etc., to create a nano-laminate, as described in H. Zhang, et al., High Permittivity Thin Film Nanolaminates, J. Appl. Phys. 87, 1921 (2000). The combination of different precursors to deposit the same metal oxide using multiple deposition cycles is not known to have been reported.

The method of the invention describes a method of gate oxide deposition using ALD. The first, or up to five, ALD deposition cycle(s) use anhydrous hafnium nitrate (Hf(NO3)4) as the precursor, while the remaining cycles use hafnium tetra-chloride (HfCl4) as the precursor. One ALD deposition cycle includes a pulse of the precursor, either hafnium nitrate or hafnium tetra-chloride, followed by a nitrogen purge, and then a pulse of water vapor, and finally, another nitrogen purge.

Referring now to FIG. 1, the structure prior to depositing the gate oxide is formed by any state-of-the-art method, which includes preparing a silicon substrate 10 and field oxide regions 12, 14. The example shown in the figures below is for a replacement gate process. The last step prior to forming the gate oxide is to expose the silicon surface to HF to prepare a H-terminated silicon surface 16.

FIG. 2 depicts the initial, or first layer, 18 of HfO2, which is deposited via ALD using a Hf(NO3)4 precursor. The purpose of this step is to initiate deposition directly on H-terminated silicon without the need for an “incubation” period or a thin SiO2 layer. The initial layer may be form between about 0.1 nm to 1.5 nm thick.

FIG. 3 depicts the another HfO2 “bulk” layer 20 as deposited to a desired thickness, which, in the preferred embodiment, is between about 3 nm to 10 nm thick, using a HfCl4 precursor. This purpose of this step is to create a “bulk” HfO2 film with the expected high dielectric constant.

The fabrication process of the method of the invention then proceeds with the deposition of the gate material, such as a metal gate followed by either and etching process or by CMP. The remaining steps are conventional fabrication processes, well known to those of ordinary skill in the art. The method of the invention eliminates the need for an initial low-κ interfacial layer while still achieving a film with a high dielectric constant.

EXAMPLE

HfO2 film A was deposited via a single cycle of ALD using a Hf(NO3)4 precursor, followed by 40 cycles of ALD using a HfCl4 precursor. As a comparison, a HfO2 film B was deposited without the single cycle ALD nitrate step, using only 40 cycles of HfCl4 precursor-based ALD. Spectroscopic ellipsometry measurements revealed that HfO2 film A, deposited using the initial ALD nitrate cycle, had an average thickness of 8.0 nm and a standard deviation of 0.5 nm. Film B, deposited without the nitrate cycle, had a average thickness of 4.2 nm and a standard deviation of 1.8 nm. The fact that film A is smoother and thicker than film B demonstrates the utility of the method of the invention: initial deposition by a single ALD cycle of Hf(NO3)4 produces an effective initiation layer for subsequent ALD using HfCl4. The fact that film A is thicker indicates that the “incubation” cycles typical of HfCl4 ALD are not required.

The layer deposited with one, or up to five, ALD cycle(s) using a Hf(NO3)4 precursor may be used as an initiation layer for ALD using other precursors, such as other metal halides, such as MI4, MBr4, etc., or metallorganics, such as alkoxide, acetylacetonates, t-butoxide, ethoxide, etc. In addition to the HfO2 process described herein, other metal oxides, such as ZrO2, Gd2O3, La2O3, CeO2, TiO2, Y2O3, Ta2O5, Al2O3, etc. may also be deposited.

Thus, a method to deposit a stacked high-κ gate dielectric for CMOS applications has been disclosed. It will be appreciated that further variations and modifications thereof may be made within the scope of the invention as defined in the appended claims.

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Non-Patent Citations
Reference
1H. Zhang et al., High permittivity thin film nanolaminates, J. Appl. Phys. 87, 1921 (2000).
2John F. Conley, Jr., et al., Atomic Layer Deposition of Hafnium Oxide Using Anhydrous Hafnium Nitrate, Electrochem. and Sol. State Lett. 5 (5) May, 2002.
Referenced by
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US713536931 Mar 200314 Nov 2006Micron Technology, Inc.Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US718318622 Apr 200327 Feb 2007Micro Technology, Inc.Atomic layer deposited ZrTiO4 films
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US7192892 *4 Mar 200320 Mar 2007Micron Technology, Inc.Atomic layer deposited dielectric layers
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Classifications
U.S. Classification438/3, 257/310, 257/E21.29, 257/E21.639, 257/E21.444, 257/295, 257/E21.274, 257/E21.01, 438/240
International ClassificationH01L21/02, H01L29/78, C23C16/40, H01L21/28, H01L29/51, H01L21/8238, H01L21/336, C23C16/455, C23C16/44, H01L21/283, H01L21/316, H01L21/31
Cooperative ClassificationH01L21/823857, H01L21/3141, C23C16/45529, H01L29/513, C23C16/405, H01L21/31683, H01L21/31604, H01L28/56, H01L29/66545, H01L21/28194, H01L29/518, H01L29/517
European ClassificationH01L29/66M6T6F8, H01L21/28E2C2D, C23C16/40H, H01L29/51B2, H01L21/8238J, H01L21/314A, C23C16/455F2B2
Legal Events
DateCodeEventDescription
1 Aug 2011FPAYFee payment
Year of fee payment: 8
24 Apr 2007FPAYFee payment
Year of fee payment: 4
31 Oct 2002ASAssignment
Owner name: SHARP LABORATORIES OF AMERICA, INC., WASHINGTON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CONLEY, JOHN F. JR.;ONO, YOSHI;SOLANKI, RAJENDRA;REEL/FRAME:013483/0556;SIGNING DATES FROM 20021030 TO 20021031