US6584596B2 - Method of designing a voltage partitioned solder-bump package - Google Patents
Method of designing a voltage partitioned solder-bump package Download PDFInfo
- Publication number
- US6584596B2 US6584596B2 US09/682,584 US68258401A US6584596B2 US 6584596 B2 US6584596 B2 US 6584596B2 US 68258401 A US68258401 A US 68258401A US 6584596 B2 US6584596 B2 US 6584596B2
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- Prior art keywords
- voltage island
- package
- chip
- island
- power
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2113/00—Details relating to the application field
- G06F2113/18—Chip packaging
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (36)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/682,584 US6584596B2 (en) | 2001-09-24 | 2001-09-24 | Method of designing a voltage partitioned solder-bump package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/682,584 US6584596B2 (en) | 2001-09-24 | 2001-09-24 | Method of designing a voltage partitioned solder-bump package |
Publications (2)
Publication Number | Publication Date |
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US20030061571A1 US20030061571A1 (en) | 2003-03-27 |
US6584596B2 true US6584596B2 (en) | 2003-06-24 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/682,584 Expired - Lifetime US6584596B2 (en) | 2001-09-24 | 2001-09-24 | Method of designing a voltage partitioned solder-bump package |
Country Status (1)
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Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040060023A1 (en) * | 2002-09-25 | 2004-03-25 | International Business Machines Corporation | Voltage island chip implementation |
US6823501B1 (en) * | 2001-11-28 | 2004-11-23 | Reshape, Inc. | Method of generating the padring layout design using automation |
US20050010887A1 (en) * | 2003-07-08 | 2005-01-13 | International Business Machines Corporation | Nested voltage island architecture |
US20050091629A1 (en) * | 2003-09-09 | 2005-04-28 | Robert Eisenstadt | Apparatus and method for integrated circuit power management |
US20060047490A1 (en) * | 2004-08-30 | 2006-03-02 | International Business Machines Corporation | Hierarchical method of power supply noise and signal integrity analysis |
US7055122B1 (en) * | 2002-04-05 | 2006-05-30 | Cisco Technology, Inc. | Method for automatically connecting top side conductors with bottom side conductors of an integrated circuit package |
US7243327B1 (en) | 2002-04-05 | 2007-07-10 | Cisco Technology, Inc. | Method for automatically routing connections between top side conductors and bottom side conductors of an integrated circuit package |
US7303941B1 (en) | 2004-03-12 | 2007-12-04 | Cisco Technology, Inc. | Methods and apparatus for providing a power signal to an area array package |
US20080030254A1 (en) * | 2006-08-02 | 2008-02-07 | Igor Arsovski | Design structure to eliminate step response power supply perturbation |
US20080030223A1 (en) * | 2006-08-02 | 2008-02-07 | Igor Arsovski | Device and method to eliminate step response power supply perturbation |
US20090172613A1 (en) * | 2003-10-21 | 2009-07-02 | Roberto Suaya | Mutual Inductance extraction using dipole approximations |
US20120204139A1 (en) * | 2003-10-21 | 2012-08-09 | Mentor Graphics Corporation | Determining mutual inductance between intentional inductors |
US20120229190A1 (en) * | 2011-03-10 | 2012-09-13 | Kabushiki Kaisha Toshiba | Power source controller and semiconductor integrated circuit |
US8732648B2 (en) | 2008-03-08 | 2014-05-20 | Mentor Graphics Corporation | High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate |
US8826203B2 (en) | 2012-06-18 | 2014-09-02 | International Business Machines Corporation | Automating current-aware integrated circuit and package design and optimization |
US8863068B2 (en) * | 2012-06-18 | 2014-10-14 | International Business Machines Corporation | Current-aware floorplanning to overcome current delivery limitations in integrated circuits |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7281227B2 (en) * | 2004-09-30 | 2007-10-09 | Infineon Technologies Ag | Method and device for the computer-aided design of a supply network |
US7882464B1 (en) * | 2005-02-14 | 2011-02-01 | Cadence Design Systems, Inc. | Method and system for power distribution analysis |
JP2009251755A (en) * | 2008-04-02 | 2009-10-29 | Nec Electronics Corp | Method, program, and apparatus for generating power supply noise model |
US8225258B2 (en) * | 2009-06-11 | 2012-07-17 | Qualcomm Incorporated | Statistical integrated circuit package modeling for analysis at the early design age |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4503386A (en) | 1982-04-20 | 1985-03-05 | International Business Machines Corporation | Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks |
US4890238A (en) | 1986-12-17 | 1989-12-26 | International Business Machines Corporation | Method for physical VLSI-chip design |
US5081602A (en) * | 1989-11-07 | 1992-01-14 | Amp Incorporated | Computer simulator for electrical connectors |
US5160997A (en) | 1988-08-12 | 1992-11-03 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit with shield electrodes for protecting the interconnection lines from undesirable radiation |
US5216278A (en) | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5243547A (en) * | 1992-04-01 | 1993-09-07 | Motorola, Inc. | Limiting parasitic signal coupling between conductors |
US5694344A (en) * | 1995-06-15 | 1997-12-02 | Motorola, Inc. | Method for electrically modeling a semiconductor package |
JPH09321142A (en) | 1996-05-28 | 1997-12-12 | Fujitsu Ltd | Apparatus for designing semiconductor integrated circuit device |
JPH10124560A (en) | 1996-10-17 | 1998-05-15 | Nec Eng Ltd | Cad system |
US5838021A (en) | 1995-12-26 | 1998-11-17 | Ancona; Mario G. | Single electron digital circuits |
US5943486A (en) | 1995-11-21 | 1999-08-24 | Matsushita Electric Industrial Co.,Ltd. | Compaction method, compaction apparatus, routing method and routing apparatus |
US5977606A (en) | 1992-11-06 | 1999-11-02 | Hitachi, Ltd. | Dielectric isolated high voltage semiconductor device |
US6025616A (en) | 1997-06-25 | 2000-02-15 | Honeywell Inc. | Power distribution system for semiconductor die |
-
2001
- 2001-09-24 US US09/682,584 patent/US6584596B2/en not_active Expired - Lifetime
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4503386A (en) | 1982-04-20 | 1985-03-05 | International Business Machines Corporation | Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks |
US4890238A (en) | 1986-12-17 | 1989-12-26 | International Business Machines Corporation | Method for physical VLSI-chip design |
US5160997A (en) | 1988-08-12 | 1992-11-03 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit with shield electrodes for protecting the interconnection lines from undesirable radiation |
US5081602A (en) * | 1989-11-07 | 1992-01-14 | Amp Incorporated | Computer simulator for electrical connectors |
US5216278A (en) | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5243547A (en) * | 1992-04-01 | 1993-09-07 | Motorola, Inc. | Limiting parasitic signal coupling between conductors |
US5977606A (en) | 1992-11-06 | 1999-11-02 | Hitachi, Ltd. | Dielectric isolated high voltage semiconductor device |
US5694344A (en) * | 1995-06-15 | 1997-12-02 | Motorola, Inc. | Method for electrically modeling a semiconductor package |
US5943486A (en) | 1995-11-21 | 1999-08-24 | Matsushita Electric Industrial Co.,Ltd. | Compaction method, compaction apparatus, routing method and routing apparatus |
US5838021A (en) | 1995-12-26 | 1998-11-17 | Ancona; Mario G. | Single electron digital circuits |
JPH09321142A (en) | 1996-05-28 | 1997-12-12 | Fujitsu Ltd | Apparatus for designing semiconductor integrated circuit device |
JPH10124560A (en) | 1996-10-17 | 1998-05-15 | Nec Eng Ltd | Cad system |
US6025616A (en) | 1997-06-25 | 2000-02-15 | Honeywell Inc. | Power distribution system for semiconductor die |
Non-Patent Citations (1)
Title |
---|
Buffet et al., "Methodology for I/O Cell Placement and Checking in ASIC Designs Using Area-Array Power Grid," IEEE 2000 Custom Ics Conference, pp. 125-128. * |
Cited By (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6823501B1 (en) * | 2001-11-28 | 2004-11-23 | Reshape, Inc. | Method of generating the padring layout design using automation |
US7055122B1 (en) * | 2002-04-05 | 2006-05-30 | Cisco Technology, Inc. | Method for automatically connecting top side conductors with bottom side conductors of an integrated circuit package |
US7243327B1 (en) | 2002-04-05 | 2007-07-10 | Cisco Technology, Inc. | Method for automatically routing connections between top side conductors and bottom side conductors of an integrated circuit package |
US6820240B2 (en) * | 2002-09-25 | 2004-11-16 | International Business Machines Corporation | Voltage island chip implementation |
US20040243958A1 (en) * | 2002-09-25 | 2004-12-02 | Bednar Thomas R. | Voltage island chip implementation |
US6883152B2 (en) | 2002-09-25 | 2005-04-19 | International Business Machines Corporation | Voltage island chip implementation |
US20040060023A1 (en) * | 2002-09-25 | 2004-03-25 | International Business Machines Corporation | Voltage island chip implementation |
WO2005008725A3 (en) * | 2003-07-08 | 2006-11-23 | Ibm | Nested voltage island architecture |
US20050010887A1 (en) * | 2003-07-08 | 2005-01-13 | International Business Machines Corporation | Nested voltage island architecture |
KR100827056B1 (en) | 2003-07-08 | 2008-05-02 | 인터내셔널 비지네스 머신즈 코포레이션 | Nested voltage island architecture |
US7131074B2 (en) * | 2003-07-08 | 2006-10-31 | International Business Machines Corporation | Nested voltage island architecture |
USRE44025E1 (en) | 2003-09-09 | 2013-02-19 | Jr. Shadt Electronics, Llc | Apparatus and method for integrated circuit power management |
US20050091629A1 (en) * | 2003-09-09 | 2005-04-28 | Robert Eisenstadt | Apparatus and method for integrated circuit power management |
US7080341B2 (en) * | 2003-09-09 | 2006-07-18 | Robert Eisenstadt | Apparatus and method for integrated circuit power management |
US8650522B2 (en) * | 2003-10-21 | 2014-02-11 | Mentor Graphics Corporation | Determining mutual inductance between intentional inductors |
US20120204139A1 (en) * | 2003-10-21 | 2012-08-09 | Mentor Graphics Corporation | Determining mutual inductance between intentional inductors |
US8826204B2 (en) | 2003-10-21 | 2014-09-02 | Mentor Graphics Corporation | Mutual inductance extraction using dipole approximations |
US8549449B2 (en) | 2003-10-21 | 2013-10-01 | Mentor Graphics Corporation | Mutual inductance extraction using dipole approximations |
US20090172613A1 (en) * | 2003-10-21 | 2009-07-02 | Roberto Suaya | Mutual Inductance extraction using dipole approximations |
US7303941B1 (en) | 2004-03-12 | 2007-12-04 | Cisco Technology, Inc. | Methods and apparatus for providing a power signal to an area array package |
US7675147B1 (en) | 2004-03-12 | 2010-03-09 | Cisco Technology, Inc. | Methods and apparatus for providing a power signal to an area array package |
US7197446B2 (en) * | 2004-08-30 | 2007-03-27 | International Business Machines Corporation | Hierarchical method of power supply noise and signal integrity analysis |
US20060047490A1 (en) * | 2004-08-30 | 2006-03-02 | International Business Machines Corporation | Hierarchical method of power supply noise and signal integrity analysis |
US7705626B2 (en) * | 2006-08-02 | 2010-04-27 | International Business Machines Corporation | Design structure to eliminate step response power supply perturbation |
US7511528B2 (en) * | 2006-08-02 | 2009-03-31 | International Business Machines Corporation | Device and method to eliminate step response power supply perturbation |
US20080030254A1 (en) * | 2006-08-02 | 2008-02-07 | Igor Arsovski | Design structure to eliminate step response power supply perturbation |
US20080030223A1 (en) * | 2006-08-02 | 2008-02-07 | Igor Arsovski | Device and method to eliminate step response power supply perturbation |
US8732648B2 (en) | 2008-03-08 | 2014-05-20 | Mentor Graphics Corporation | High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate |
US8910108B2 (en) | 2008-03-08 | 2014-12-09 | Mentor Graphics Corporation | High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate |
US9230054B2 (en) | 2008-03-08 | 2016-01-05 | Mentor Graphics Corporation | High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate |
US20120229190A1 (en) * | 2011-03-10 | 2012-09-13 | Kabushiki Kaisha Toshiba | Power source controller and semiconductor integrated circuit |
US8536936B2 (en) * | 2011-03-10 | 2013-09-17 | Kabushiki Kaisha Toshiba | Power source controller and semiconductor integrated circuit |
US8826203B2 (en) | 2012-06-18 | 2014-09-02 | International Business Machines Corporation | Automating current-aware integrated circuit and package design and optimization |
US8863068B2 (en) * | 2012-06-18 | 2014-10-14 | International Business Machines Corporation | Current-aware floorplanning to overcome current delivery limitations in integrated circuits |
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US20030061571A1 (en) | 2003-03-27 |
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