US6576553B2 - Chemical mechanical planarization of conductive material - Google Patents
Chemical mechanical planarization of conductive material Download PDFInfo
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- US6576553B2 US6576553B2 US10/012,808 US1280801A US6576553B2 US 6576553 B2 US6576553 B2 US 6576553B2 US 1280801 A US1280801 A US 1280801A US 6576553 B2 US6576553 B2 US 6576553B2
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- 239000004020 conductor Substances 0.000 title claims abstract description 97
- 239000000126 substance Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 115
- 239000000463 material Substances 0.000 claims abstract description 44
- 238000000151 deposition Methods 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims description 38
- 238000005498 polishing Methods 0.000 claims description 37
- 239000002002 slurry Substances 0.000 claims description 16
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 238000012544 monitoring process Methods 0.000 claims description 8
- 102100022717 Atypical chemokine receptor 1 Human genes 0.000 claims description 6
- 101000678879 Homo sapiens Atypical chemokine receptor 1 Proteins 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- -1 Tungsten Nitride Chemical class 0.000 claims description 5
- 239000006117 anti-reflective coating Substances 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000003667 anti-reflective effect Effects 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910001260 Pt alloy Inorganic materials 0.000 claims description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- ROZSPJBPUVWBHW-UHFFFAOYSA-N [Ru]=O Chemical class [Ru]=O ROZSPJBPUVWBHW-UHFFFAOYSA-N 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 230000001939 inductive effect Effects 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000002310 reflectometry Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 59
- 239000003989 dielectric material Substances 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 description 14
- 239000000758 substrate Substances 0.000 description 11
- 238000005530 etching Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000007517 polishing process Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000012876 topography Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000010431 corundum Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
Definitions
- the present invention relates to semiconductor processing technology and, in particular, concerns a method of planarizing the surface of a wafer using chemical mechanical polishing.
- Integrated circuits are typically comprised of a plurality of semiconductor devices formed in or on a semiconductor substrate.
- integrated circuits can consist of literally thousands or millions of individual semiconductor devices formed in or on the substrate.
- large number of integrated circuits are formed on a single wafer by selectively exposing regions of the wafer so as to allow for deposition or implantation of impurities into the semiconductor wafer to thereby alter the characteristics of the semiconductor wafer to produce the desired different semiconductor devices.
- the semiconductor devices can be formed in the exposed regions of the wafer using well-known masking techniques in conjunction with well-known diffusion, implantation or deposition techniques.
- CMP chemical mechanical polishing or planarization
- CMP is a technique whereby the upper surface of a wafer is globally planarized by simultaneously abrasively polishing and etching the upper surface of the wafer.
- the wafer is positioned adjacent a pad that is rotated with respect to the wafer and the pad also contains a slurry which typically is comprised of an etchant liquid and an abrasive encapsulated within a suspension material.
- the rotating pad is then applied to the wafer so that protrusions in the surface topography of the integrated circuits on the wafer can be removed by a combination of abrasive polishing and etching.
- dielectric layers such as BPSG Oxide (Boro-Phospho-Silicate Glass) is formed on the upper surface of a wafer so as to provide isolation or a dielectric between conductive layers and semiconductor devices formed in the wafer.
- cavities such as trenches or vias, are often formed in the intermediate dielectric layer so that conductors can be deposited within the trenches or vias to allow for selective interconnection to the semiconductor devices within the semiconductor substrate or to circuit nodes positioned under the dielectric layer.
- the conductive layers are formed by depositing conductive material such as Polysilicon, Tungsten, or Aluminum, on top of the intermediate dielectric layer using well-known deposition techniques, such as vacuum chamber deposition, spluttering and the like. While the deposition techniques will result in conductive material being deposited within the trenches and vias formed in the intermediate dielectric layer, a substantial portion of the conductive material will extend upward from the intermediate dielectric layer thereby resulting in less planarization of the upper surface of the integrated circuit.
- conductive material such as Polysilicon, Tungsten, or Aluminum
- CMP is often used to remove the excess portion of the conductive material that is positioned on top of the intermediate dielectric layer as a result of the deposition techniques. While CMP is well adapted for removing the excess conductive material, it is often difficult to control the rate of removal of the conductive material which can result in portions of the intermediate dielectric layer being inadvertently removed during the CMP process.
- planarization technique such as CMP, which is capable of planarizing a dielectric or Oxide layer to remove excess conductive material, but does not result in significant thinning of the underlying region or layer.
- one aspect of the present invention is a method of forming a circuit element on a semiconductor wafer comprising forming a dielectric layer on a semiconductor wafer, forming a shield layer on the dielectric layer, forming a first cavity in the dielectric layer, and then depositing conductive material on the wafer so that the conductive material coats the exposed surfaces of the first cavity and so that the conductive material does not completely fill the cavity so as to define a second cavity within the first cavity.
- the method further comprises removing excess conductive material by chemical mechanical planarization (CMP), wherein the shield layer inhibits thinning of the dielectric layer during the chemical mechanical planarization. In this way, substantially all of the excess conductive material can be removed while reducing the degree of thinning of the underlying dielectric layer.
- CMP chemical mechanical planarization
- the step of removing the excess conductive material includes detecting an end point which corresponds to the chemical mechanical polishing of the shield layer. In this way, chemical mechanical polishing of the excess conductive material and can be continued until an indication that the chemical mechanical polishing is now occurring at the shield layer.
- a method of forming a conductive element in a dielectric layer on a semiconductor wafer includes positioning a shield layer on the dielectric layer, positioning a sacrificial layer on the shield layer, forming a cavity in the dielectric layer, and depositing conductive material on the sacrificial layer so that the conductive layer is positioned within the cavity.
- the method further includes using chemical mechanical polishing (CMP) to remove the excess conductive material and the sacrificial layer, wherein the CMP is performed using an etchant selected to remove the sacrificial layer and wherein the shield layer is resistant to the selected etchant.
- CMP chemical mechanical polishing
- a method of forming a dielectric layer of a first thickness on a semiconductor wafer comprises forming the dielectric layer of the first thickness on the wafer, positioning a shield layer on the dielectric layer, positioning a sacrificial layer on the shield layer, depositing conductive material on the sacrificial layer, and removing the conductive material and the sacrificial layer using a chemical mechanical polishing process adapted to remove the conductive material and the sacrificial layer wherein the shield layer is more resistant to planarization by the chemical mechanical polishing process than the sacrificial layer.
- the method further comprises detecting when the chemical mechanical polishing process has removed the sacrificial layer.
- an electrical structure formed using semiconductor processing techniques comprises a circuit node, a layer of dielectric material formed over the circuit node to a desired thickness and having an opening formed therein, a shield layer formed on an outer surface of the dielectric layer, and a sacrificial layer formed on an outer surface of the shield layer.
- the electrical structure further comprises a conductive plug formed of a conductive material positioned within the opening so as to contact the circuit node, wherein the shield layer provides a shield against thinning of the dielectric layer from the desired thickness and wherein the sacrificial layer facilitates CMP removal of excess conductive material during formation of the conductive plug.
- a capacitor structure formed using semiconductor processing techniques comprises a layer of dielectric material formed to a desired thickness and having an opening formed therein, a shield layer formed on an outer surface of the dielectric layer, and a bottom electrode formed of a conductive material positioned within the opening so as to be adjacent the dielectric layer, wherein the shield layer provides a shield against thinning of the dielectric layer from the desired thickness during formation of the bottom electrode.
- the capacitor structure further comprises a capacitor dielectric formed on an outer surface of the bottom electrode within the opening, and an upper electrode formed of a conductive material on an outer surface of the capacitor dielectric.
- FIGS. 1A-1F are sectional views illustrating the process by which a cavity is formed in a dielectric layer and conductive material is deposited on the surface of the device so as to fill the cavity with the excess conductive material being removed through one embodiment of a CMP process.
- FIG. 2A is a schematic illustration of an exemplary CMP device which is used to remove extra conductive material formed on the upper surface of the dielectric layer so as to planarize the structure;
- FIG. 2B is a schematic illustration of another exemplary CMP device which is used to remove extra conductive material formed on the upper surface of the dielectric layer so as to planarize the structure;
- FIG. 3 is a flow chart illustrating the basic operation of the chemical mechanical polishing device of FIG. 2 as excess conductive material is removed from the upper surface of the structure shown in FIGS. 1A-1F;
- FIG. 4 is a sectional view illustrating a contact plug having a shield layer to reduce thinning of a dielectric layer during chemical mechanical planarization of the upper surface of the dielectric layer;
- FIGS. 5A-5D are sectional views illustrating various embodiments of a method of forming a capacitor structure which utilizes a shield layer to reduce thinning of a dielectric layer during chemical mechanical planarization of the upper surface of the dielectric layer.
- FIGS. 1A-1F illustrate the process by which a cavity, such as a trench, via or other opening, is formed in a dielectric layer, such as an intermediate dielectric layer.
- a conductive material such as Polysilicon or a metal, is deposited on the upper surface of the dielectric layer so as to fill the cavity in the dielectric layer.
- the dielectric layer includes a sacrificial layer and a shield layer that will allow for better removal of the excess conductive material from the upper surface of the dielectric layer while reducing the degree of thinning of the dielectric layer during the removal and planarization process.
- a dielectric layer 100 is provided.
- the dielectric layer 100 can be comprised of a dielectric layer that is positioned on top of a semiconductor substrate 102 so as to isolate conductors from semiconductor devices formed in the underlying substrate 102 .
- the dielectric layer 100 can also be formed to separate devices and conductors formed on top of the substrate 102 .
- the exact configuration of the dielectric layer 100 can, of course, vary depending upon the design and configuration of the semiconductor device.
- the intermediate dielectric layer 100 is comprised of a layer of BPSG Oxide that is grown to a desired thickness using well-known techniques on top of the semiconductor substrate 102 .
- any of a number of well-known dielectric layers or spacer layers, such as TEOS layers etc. can be used in conjunction with this process as will be described in greater detail below.
- a shield layer 104 is then positioned on an upper surface 103 of the dielectric layer 100 .
- the shield layer 104 in one embodiment, is selected to be resistant to a subsequent chemical mechanical planarization (CMP) process.
- the shield layer 104 is comprised of a layer of material that has a relatively high hardness when compared to other Oxide layers or is comprised of other hard Oxide layers, such as TEOS Oxide, and the like.
- the shield layer 104 is selected so that it is relatively impervious to the etchant that will be used in a subsequent chemical mechanical planarization (CMP) process.
- the shield layer 104 is formed by depositing Silicon Nitride (Si 3 N 4 ) in a well known manner on the upper surface 103 of the dielectric 102 .
- the Silicon Nitride shield layer 104 is less susceptible to removal in certain CMP processes depending upon the etchant used in the process.
- the shield layer 104 may comprise material that reflects a relatively small amount of light from its surface.
- the shield layer 104 may comprise an antireflective coating, such as dielectric antireflective coating (commonly known as DARC Oxide) having the chemical composition of SiO x N y , wherein x and y are integer values.
- the DARC shield layer 104 may be deposited using a Chemical Vapor Deposition (CVD) process, such as plasma enhanced CVD.
- CVD Chemical Vapor Deposition
- a sacrificial layer 106 is deposited on an upper surface 105 of the shield layer 104 .
- the sacrificial layer 106 is comprised of a sacrificial Oxide, such as BPSG Oxide, which is grown to a thickness of 200-1000 angstroms.
- the sacrificial layer is selected so as to be more easily removed during planarization than the shield layer 104 .
- a cavity 110 is formed so as to extend through the sacrificial layer 106 , the shield layer 104 and into the dielectric layer 100 .
- the cavity 110 is preferably formed using well known patterning and etching processes.
- the cavity 110 can comprise an opening, via or trench that is adapted to receive conductive material in a manner that will be described in greater detail below.
- the cavity 110 may extend entirely through the dielectric layer 100 to the underlying devices or it may simply extend only partially into the dielectric layer 100 so that any conductive material positioned within the cavity 110 is insulated from any semiconductor devices or other conductors positioned on the other side of the dielectric layer 100 .
- the cavity 110 may take the form of a trench, whereby a conductive trace can be deposited in the dielectric layer 100 and extend across the surface of the integrated circuit while still allowing the upper surface of the circuit to be generally planar as will be described in greater detail below.
- a conductive material 112 such as Polysilicon, Aluminum, Tungsten, Tungsten Nitride, or Copper, can be deposited on the upper surface 107 of the sacrificial layer so that the conductive material 112 fills the cavity 110 .
- the conductive material 112 is generally deposited on the upper surface 107 of the sacrificial layer 106 and within the cavity 110 using well-known deposition techniques, such as vacuum deposition, spluttering and the like. As is shown in FIG. 1E, the deposition usually results in the conductive material 112 extending an irregular thickness T from the upper surface 107 of the sacrificial layer 106 .
- CMP chemical mechanical polishing or planarization
- the shield layer 104 is selected to be less easily removed through the CMP process than either the conductive material 112 or the sacrificial layer 106 .
- the shield layer 104 is of significantly greater hardness than the sacrificial layer 106 .
- the etchant used in the CMP process is selected to remove the conductive material 112 and the sacrificial layer 106 , but the shield layer 104 is selected to be relatively impervious to the etchant.
- the current that is drawn by the motor to turn the polisher will increase as the polisher comes in contact with the shield layer 104 .
- it will ensure that substantially all of the sacrificial layer 106 has been removed. If substantially all of the sacrificial layer 106 has been removed, the likelihood of excess conductive material 112 positioned on the upper surface 105 of the shield layer 104 remaining after the CMP process step is reduced. In this way, the conductive material 112 can be removed from the upper surface of the dielectric layer 100 without contributing to excess thinning of the dielectric layer 100 .
- the shield layer 104 can be used to define an end point to the CMP process.
- FIG. 2A schematically illustrates a manner in which CMP is often performed on a semiconductor wafer.
- a typical CMP system 200 includes a rotating polishing pad or surface 201 that is rotated by a shaft 202 attached to a motor (not shown).
- the polishing pad 201 may comprise a relatively soft material, such as a plastic like polyurethane, and a slurry 205 is provided by a supply tube 204 to the pad while the pad is rotated.
- the slurry 205 provided by the tube 204 is typically comprised of an abrasive material, such as alumina or silica particles, that is encapsulated within an etchant liquid and also, possibly, a suspension fluid.
- the exact compensation of the slurry 205 will, of course, vary depending upon the material that is to be removed from the wafer via the CMP process.
- the etchant in the slurry 205 is selected to be a Corundum-type etchant available from Rodel, Newark, Del., that is specifically adapted for etching BPSG Oxide and Polysilicon conductive material.
- the shield layer 104 is comprised of a Silicon Nitride (Si,N 4 ) material that is relatively impervious to the corundum etching. The slurry can therefore be selected for selective etching action against the conductive material 110 and the sacrificial material 106 but is relatively ineffective at etching the underlying shield layer 104 to facilitate end point definition as will be described in greater detail hereinbelow.
- the CMP system 200 also includes a rotatable wafer carrier 206 that is rotatable about a shaft 208 by a motor (not shown).
- the wafer 210 is attached to the carrier 206 so that the wafer 210 can be positioned against the polishing pad 201 in the manner shown in FIG. 2 .
- the wafer carrier 206 and the polishing pad 201 are moveable with respect to each other so that the plane of the polishing pad 201 can be positioned against the plane of the wafer 210 that is positioned within the carrier 206 .
- the surface of the wafer 210 adjacent the polishing pad 201 is preferably planarized by the combination of the abrasive polishing the surface of the wafer 210 and the etchant of the slurry 205 chemically interacting with the materials on the exposed surface of the wafer 210 .
- various detectable end points are used which can be used to control the CMP process.
- the slurry 205 is selected for removal of the excess conductive material 110 and the sacrificial layer 106 but does not etch the shield layer 104 as effectively, various detectable end points also occur.
- the pad 201 removes the excess conductive material 110 and the sacrificial layer 106 , the pad then comes in contact with the shield layer 104 .
- the shield layer 104 is not removed as easily as the sacrificial layer 106 or the conductive material 110 , either as a result of different hardness or different etchant rates between the materials, the frictional engagement between the polishing pad 201 and the shield layer 104 increases during the CMP process.
- the amount of current drawn by the motor that is causing either the carrier 206 or the pad 201 or both to rotate increases.
- an end point can be detected which is indicative of the CMP process having removed all of the excess conductive material 110 and the sacrificial layer 106 .
- the use of the current drawn by a rotating motor of a chemical mechanical polishing system provides a well-known end point suitable for use for halting a chemical mechanical polishing process.
- any of a number of end point determinations can be used to assess when the CMP process has removed the excess conductive layer 110 and the sacrificial layer 106 and is in contact with the shield layer 104 to halt the CMP process in a manner that reduces the thinning of the dielectric layer 100 .
- another way of detecting end points is by exposing the surface of the wafer that is subject to the CMP process to a light source, such as a LASER, and then analyzing the intensity of the reflected light.
- the light source can be tuned so that the intensity of the reflected light changes, e.g., decreases, when the CMP process has exposed the shield layer.
- any of a number of CMP end point detection schemes can be used with the shield layer of the present invention without departing from the spirit of the present invention.
- FIG. 2B is a schematic illustration of one embodiment of the CMP system 200 that monitors reflected light to perform end point determination.
- the CMP system 200 further comprises a processor or processing system 220 that is adapted to control the CMP process performed by the system 200 .
- the processor 220 is capable of translating the pad 201 and the carriage 206 with respect to each other and then positioning the pad 201 and the carriage 206 in proximity to each other to begin the planarization process.
- the processor 220 also receives end point data from an end point detection system 221 and decides, based upon the end point data, when the end of the planarization process has occurred.
- the end point detection system 221 is comprised of one or more light sources 222 , such as a laser, that shine a beam 226 through the pad 201 onto the surface of the wafer 210 and a detector 224 that receives a reflective beam 228 from the surface of the wafer and provides a signal indicative thereof to the processor 220 .
- light sources 222 such as a laser
- the light source 222 is adapted to produce the beam 226 that is selected so that the reflective beam 228 is modulated in a detectable manner upon the planarization of the wafer 210 occurring such that a particular layer of the wafer is exposed.
- the light source 222 is comprised of a laser that produces the beam 226 of a particular wavelength that is selected so that the intensity of the reflected beam 228 decreases upon the planarization of the wafer 210 occurring such that a particular layer of the wafer is exposed. The occurrence of a relatively large decrease in intensity of the reflected beam 228 is indicative of the end point of the CMP process.
- the processor 220 Upon receiving such a signal from the detector 224 , the processor 220 is adapted to halt the CMP process.
- the system illustrated in FIG. 2B is an exemplary CMP system of a type that is well known in the art. Examples of such a system include the MIRRA Chemical Mechanical Planarization System available from Applied Materials of Santa Clara, Calif.
- FIG. 3 is a flow chart which illustrates the general operation of the CMP systems 200 as the excess conductive material 110 and the sacrificial layer 106 is removed from the wafer 210 .
- the CMP system 200 from a start state 300 , initially rotates the polishing pad 201 and the wafer carriage 206 , in a state 302 .
- the CMP system 200 is adapted to rotate the pad 201 and the carriage 206 simultaneously in opposite directions.
- only the carriage or the pad may be rotated in order to achieve the planarization effect and that the CMP process of the present invention can be used with these types of CMP systems without departing from the spirit of the present invention.
- relative movement between the carriage and the pad could occur in either a continuous or reciprocal manner.
- relative movement could occur in a translational manner.
- slurry 205 is applied to the pad 201 in state 304 via the slurry supply tube 204 .
- the pad 201 is frictionally engaged with the wafer 210 .
- the wafer carriage 206 and the pad 201 are moved with respect to each other such that the plane of the exposed surface of the wafer 210 is brought into physical contact with the pad 201 .
- the rotational movement between the pad 201 and the wafer 210 provides the frictional engagement which results in the abrasive captured within the slurry 205 removing portions of the exposed surface of the wafer 210 and also allowing the etchant within the slurry 205 to chemically react with the exposed surface of the wafer to further enhance the removal and planarization process.
- the CMP system 200 is monitoring end point data in a state 310 which are indicative of the frictional forces applied between the pad and the wafer.
- the end point data in one embodiment is the current that is being drawn by the motors that is establishing the rotational movement between the pad 201 and the exposed surface of the wafer 210 .
- the CMP system 200 includes a processor that can be adapted to receive an end point signal indicative of the current being drawn by the motor so that when the current has increased to thereby indicate that the pad 201 is now in contact with the shield layer 104 , the processor can halt the chemical mechanical polishing step.
- the CMP system 200 is monitoring end point data in the state 310 which are indicative of the light 228 reflected from the surface of the wafer 210 .
- the end point data in this embodiment are the output signals of the light sensors 224 which are indicative of the light energy entering the active regions of the sensors 224 .
- the CMP system 200 includes the processor 220 that is adapted to receive the output signals from the light sensors 224 so that when the output signals change to thereby indicate that the pad 201 is now in contact with the shield layer 104 , the processor 220 can halt the chemical mechanical polishing step.
- the CMP system 200 determines, in decision state 312 , whether the shield layer end point has been detected. If the shield layer end point has not been detected in decision state 312 , the process returns to state 302 where the rotational motion between the pad 201 and the wafer 210 is maintained. If, however, the end point is detected in decision state 312 , the process is then terminated in an end state 314 .
- the method of removing conductive material from an exposed surface of a dielectric layer can result in more complete removal of the conductive material while reducing the degree of thinning of the underlying dielectric layer as a result of the chemical mechanical polishing. This allows the dielectric layer to be grown to a final thickness of a more exact tolerance.
- the use of a CMP resistant shield layer 104 immediately underneath the sacrificial layer results in the establishment of a readily identifiable end point for the CMP system 200 .
- the use of an antireflective shield layer 104 immediately underneath the sacrificial layer results in the establishment of a readily identifiable end point for the CMP system 200 .
- the CMP resistant shield layer 104 is also more resistant to chemical mechanical planarization such that the inadvertent removal of the shield layer 104 is reduced as compared to removal of the material forming the dielectric layer 100 in a similar prior art CMP process.
- FIG. 4 illustrates an exemplary structure that can be formed using the process described above in conjunction with FIGS. 1A through 1F.
- FIG. 4 shows a contact plug 260 that is formed in an opening 258 in a dielectric layer 250 that has been grown to a desired thickness on top of a circuit node 262 , which in one embodiment, can be a semiconductor substrate.
- the contact plug 260 is preferably formed of a conductive material such as Polysilicon, Tungsten and the like so that electrical connection can be made to the circuit node 262 positioned underneath.
- the dielectric layer 250 is formed of a dielectric isolating material, such as BPSG Silicon to a desired thickness.
- a shield layer 254 is positioned on top of the dielectric layer 250 .
- the shield layer 254 can be any material that provides reliable end point determination to a CMP process that is being used to remove excess material positioned on top of the shield layer 254 during the formation of the contact plug 260 in the manner described above, such as Nitride material or DARC Oxide material.
- FIGS. 5A-5D illustrate methods of forming a bottom electrode 510 of a capacitor structure 501 , wherein the methods are similar to those described above in conjunction with FIGS. 1A-1F.
- a contact plug 520 such as the plug described above, is formed so as to electrically interconnect the bottom electrode 510 to a substrate 522 .
- a barrier layer 519 is interposed between the plug 520 and the bottom electrode 510 in a well known manner so as to reduce oxidation of the plug 520 and so as to reduce Silicon diffusion of the bottom electrode 510 .
- transistor gate structures 526 which allows for selective activation of the bottom electrode 510 of the capacitor structure 510 in a well known manner.
- a dielectric layer 500 of a material such as BPSG Oxide is grown to a desired thickness using well-known techniques above the substrate 522 .
- a shield layer 504 such as DARC Oxide or Nitride is then positioned on the upper surface of the dielectric layer 500 .
- a first opening 508 is formed in the shield layer 504 and the dielectric layer 500 using well known techniques so that the capacitor structure 501 can be subsequently formed within the opening 508 .
- the bottom electrode layer 510 is then formed within the opening 508 so as to cover the interior walls of the opening 508 .
- the bottom electrode layer 510 does not completely fill the opening 508 so as to define a second opening 509 within the first opening 508 and so as to enable subsequent deposition of a dielectric layer 512 and an upper electrode layer 514 within the opening 509 as will be described in greater detail below in connection with FIG. 5 D.
- the bottom electrode layer 510 is formed by depositing a conductive material, preferably of a barrier metal to prevent diffusion of subsequently deposited material into the dielectric isolation layer 500 .
- the layer 510 is formed using well known techniques using materials such as Tungsten, Tungsten Nitride, Platinum, Platinum alloys, Tantalum, Ruthenium, Ruthenium Oxides such as RuO 2 and Ru 2 O 3 , and the like.
- the bottom electrode layer 510 may be formed with a hemispherical grained surface (HSG) so as to enhance the capacitance of the capacitor structure 501 by increasing the surface area of the layer 510 .
- HSG hemispherical grained surface
- excess material is often deposited on top of the shield layer 504 and is removed using CMP.
- the shield layer 504 enhances end point determination which allows for removal of the excess material while decreasing the likelihood of thinning of the underlying dielectric layer 500 .
- a sacrificial layer 511 is deposited over the shield layer 504 before forming the opening 508 .
- the sacrificial layer 506 is comprised of sacrificial Oxide, such as BPSG Oxide, which is grown to a thickness of 200-1000 Angstroms so as to be more easily removed during planarization than the shield layer 504 .
- the sacrificial layer 506 reduces the likelihood that overlying conductive material will remain following the CMP process.
- a temporary fill layer 513 is preferably deposited over the bottom electrode layer 510 so as to temporarily fill the second opening 509 .
- the fill layer 513 helps to maintain the integrity of the bottom electrode layer 510 during the subsequent CMP process.
- the fill layer 513 preferably comprises any material that can be removed during the previously mentioned CMP process and that can be further removed during a conventional etching process.
- the fill layer 513 comprises photoresist.
- either of the CMP processes described previously can be used to remove excess material from the fill layer 513 and excess material from the bottom electrode layer 510 so as to define the bottom electrode 510 of the capacitor structure 501 of FIG. 5 C.
- the sacrificial layer 506 is also removed during the CMP process so as to reduce the likelihood that material from the bottom electrode layer 510 remains on the upper surface of the shield layer 504 following the completion of the CMP process.
- FIG. 5C illustrates an intermediate form of the capacitor structure 501 of FIG. 5D subsequent to the completion of the CMP process.
- the remaining material from the fill layer 513 extends into the opening 509 so as to form a planarized upper surface that aligns with the planarized upper surface of the shield layer 504 .
- the bottom electrode 510 and the fill layer 513 substantially fill the opening 508 , the likelihood that the upper vertical portions of the bottom electrode 510 are dislodged from the shield layer 504 and the dielectric layer 500 during the CMP process is reduced. Consequently, the integrity of the bottom electrode 510 is substantially maintained during the CMP process.
- the remaining fill layer 513 of FIG. 5C is substantially removed so as to substantially expose the bottom electrode 510 and, thus, redefine the opening 509 .
- an etching process is used to remove the remaining fill layer 513 .
- the fill layer 513 comprising known photoresist material is exposed to a known etchant comprising an oxidizing agent.
- a dielectric layer 512 is then deposited in the opening 509 using well known techniques so as to eventually form an insulating medium between the bottom electrode 510 and a top electrode 514 of the capacitor structure 501 .
- the dielectric layer 512 is deposited so as to cover the exposed outer surface of the bottom electrode 510 .
- the dielectric layer 510 is formed of a dielectric material such as Tantalum Oxide, Aluminum Oxide and Barium Strontium Titanate or other High-K dielectric materials.
- the upper electrode 514 is then formed on the exposed outer surface of the capacitor dielectric 512 .
- the upper electrode 514 is typically formed of a material such as Polysilicon, Platinum, Platinum alloys, Tungsten, Tungsten Nitride, Ruthenium, Ruthenium Oxide (RuO 2 ), Iridium and Iridium Oxide (IrO 2 ).
- FIGS. 4 and 5D simply illustrate two types of structures that can be formed so as to have a shield layer that improves endpoint determination during CMP removal of excess material. These structures can be formed so as to have material layers of closer tolerances which enhances the ability to form higher density structures. While FIGS. 4 and 5D illustrate two different possible structures, it will be appreciated that any of a number of different structures formed in semiconductor processing can be formed having a shield layer which protects a particular region of the device from thinning during CMP without departing from the spirit of the present invention.
Abstract
Description
Claims (28)
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US10/012,808 US6576553B2 (en) | 1999-05-11 | 2001-11-13 | Chemical mechanical planarization of conductive material |
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US30946099A | 1999-05-11 | 1999-05-11 | |
US09/552,383 US7045454B1 (en) | 1999-05-11 | 2000-04-19 | Chemical mechanical planarization of conductive material |
US10/012,808 US6576553B2 (en) | 1999-05-11 | 2001-11-13 | Chemical mechanical planarization of conductive material |
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US09/552,383 Division US7045454B1 (en) | 1999-05-11 | 2000-04-19 | Chemical mechanical planarization of conductive material |
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US6576553B2 true US6576553B2 (en) | 2003-06-10 |
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US09/552,383 Expired - Fee Related US7045454B1 (en) | 1999-05-11 | 2000-04-19 | Chemical mechanical planarization of conductive material |
US10/012,637 Abandoned US20020053712A1 (en) | 1999-05-11 | 2001-11-13 | Chemical mechanical planarization of conductive material |
US10/012,808 Expired - Lifetime US6576553B2 (en) | 1999-05-11 | 2001-11-13 | Chemical mechanical planarization of conductive material |
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US10/012,637 Abandoned US20020053712A1 (en) | 1999-05-11 | 2001-11-13 | Chemical mechanical planarization of conductive material |
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Cited By (2)
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KR20030059407A (en) * | 2001-12-29 | 2003-07-10 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
US7045454B1 (en) * | 1999-05-11 | 2006-05-16 | Micron Technology, Inc. | Chemical mechanical planarization of conductive material |
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US8242006B2 (en) | 2007-12-21 | 2012-08-14 | General Electric Company | Smooth electrode and method of fabricating same |
DE102007063271B4 (en) * | 2007-12-31 | 2009-11-26 | Advanced Micro Devices, Inc., Sunnyvale | A method of making a dielectric interlayer material having different removal rates during a CMP process |
US8610280B2 (en) * | 2011-09-16 | 2013-12-17 | Micron Technology, Inc. | Platinum-containing constructions, and methods of forming platinum-containing constructions |
KR102251775B1 (en) * | 2014-07-18 | 2021-05-12 | 삼성전자주식회사 | Electrode structure and touch detecting sensor using the same |
CN109994394B (en) * | 2017-12-29 | 2021-05-28 | 中电海康集团有限公司 | Method for flattening MTJ (magnetic tunnel junction) unit in MRAM (magnetic random Access memory) device and MRAM device |
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Also Published As
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US7045454B1 (en) | 2006-05-16 |
US20020053712A1 (en) | 2002-05-09 |
US20020042201A1 (en) | 2002-04-11 |
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