US6538486B1 - Latch chain having improved sensitivity - Google Patents
Latch chain having improved sensitivity Download PDFInfo
- Publication number
- US6538486B1 US6538486B1 US09/686,236 US68623600A US6538486B1 US 6538486 B1 US6538486 B1 US 6538486B1 US 68623600 A US68623600 A US 68623600A US 6538486 B1 US6538486 B1 US 6538486B1
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- latch
- output
- input
- amplifier
- sample
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/287—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the feedback circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
- H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration
Definitions
- the present invention relates to digital latches and latch chains having improved sensitivity.
- FIG. 1 shows a conventional digital latch 1 that includes a sample stage 2 with complementary voltage inputs 3 , 4 , a hold stage 5 , and matched transistors 6 , 7 having complementary voltage outputs 8 , 9 .
- the transistors 6 , 7 are biased by complementary currents through matched resistors R.
- sample stage 2 During a sample period, sample stage 2 generates a current through resistors R to produce a voltage difference Vab between nodes A and B responsive to the voltage difference Vin ⁇ overscore (V) ⁇ in between input terminals 3 and 4 .
- the values of the voltage difference Vab correspond logical values +1 and 0.
- hold stage 5 maintains the current through resistors R so that the voltage difference Vab remains unchanged.
- the voltages at nodes A and B cause output voltages Vout and ⁇ overscore (V) ⁇ out at output terminals 8 and 9 , respectively.
- the difference between output voltages Vout and ⁇ overscore (V) ⁇ out is indicative of the logic value stored during the previous sample period.
- external digital devices may sample the voltages at terminals 8 , 9 to determine the logic value stored in the latch 1 .
- the sensitivity of a latch to input voltages sets performance limitations on several mixed-signal integrated circuit (IC) applications of the latch. These applications include digital phase detection in clock-data recovery circuits and fiber receivers. Improved circuit performance in such applications may be realized by improving the sensitivity of the latch.
- IC integrated circuit
- the chain includes a first latch, an amplifier, and a second latch connected in series.
- the second latch is a conventional latch.
- the first latch is modified to have a higher sensitivity and lower output voltage swing than conventional latches.
- the modified latch includes a pair of matched output transistors that generate output voltages and a pair of matched biasing circuits to bias the bases of the output transistors with bias voltages.
- a sample stage is connected so as to apply first biasing currents to one of the biasing circuits in response to input voltages applied to the first latch during the sample period.
- a hold stage is connected so as to apply second biasing currents to the biasing circuits during a hold period.
- the sample and hold stages are configured to apply different voltage differences between the bases of the output transistors.
- FIG. 1 shows a conventional digital latch
- FIG. 2 is an exemplary latch chain with improved sensitivity to input voltages in accordance with the present invention
- FIG. 3 is an embodiment of the amplifier in the latch chain of FIG. 2;
- FIG. 4 is an embodiment of the modified latch of FIG. 2, which has improved sensitivity to input voltages
- FIG. 5 is one embodiment of the modified latch in FIG. 4.
- FIGS. 6 a - 6 c are timing diagrams for the modified latch in FIG. 4 .
- FIG. 2 is an exemplary latch chain 10 with improved sensitivity to input voltages Vin.
- Latch chain 10 includes a modified latch 14 , an amplifier 16 , and conventional latches 18 , 20 , which are serially connected to the output of the amplifier 16 .
- Two conventional latches 18 , 20 are shown in FIG. 2, however, any number of one or more conventional latches may be serially connected in the chain, as desired.
- Each latch 14 , 18 , 20 has a sample period and a hold period triggered by signals from an external clock 22 .
- the amplifier 16 is not controlled by the clock 22 .
- Modified latch 14 has an input terminal 12 that also serves as the input terminal for the latch chain 10 . At its input terminal 12 , the modified latch 14 has a higher input voltage sensitivity than conventional latches 18 , 20 of the chain 10 . As a result of the higher input voltage sensitivity of modified latch 14 , the entire latch chain 10 is more sensitive to input voltage Vin swings.
- conventional latch 1 prior to storing a new logic value Vab, conventional latch 1 must discharge the previously stored voltage Vab between nodes A and B.
- the time needed to discharge the previously stored voltage difference Vab is dependent on the internal parasitic capacitances of the latch 1 . If the time for discharge is greater than one sample period, the latch 1 is unable to store the new logic voltage Vab during the next sample period. Thus, proper operation of the latch 1 requires that the sample period be longer than the time needed to discharge the previous voltage Vab between nodes A and B. Thus, sampling rates are limited by internal parasitic capacitances of the latch 1 .
- the length of the sample period limits the input sensitivity of latch 1 , because the rate of discharge of a previously stored voltage Vab depends on the absolute value of Vin ⁇ overscore (V) ⁇ in. If the input voltages are too low in amplitude, the latch 1 will not completely discharge the previously stored voltage Vab thereby prohibiting setup of a new voltage difference Vab associated with a new logic value during the next sample period.
- modified latch 14 has a higher input voltage sensitivity than conventional latches 18 , 20 , because it performs smaller internal voltage swings than those latches 18 , 20 .
- the smaller voltage swings change the internal logic state.
- the modified latch 14 has to discharge less internally stored charge than conventional latches 18 , 20 , during the next sample period to change its logic state.
- the modified latch 14 is able to switch its stored logic state in response to a smaller absolute value of the input voltage Vin ⁇ overscore (V) ⁇ in than conventional latches 18 , 20 .
- the higher sensitivity of the modified latch 14 produces a latch chain 10 having a higher sensitivity at a given clock rate than a conventional latch chain comprising sequentially coupled latches with identical sensitivities.
- the modified latch 14 in FIG. 2 generates smaller output voltage swings, i.e., a smaller swings of the amplitude of output voltage difference (Vout ⁇ overscore (V) ⁇ out), as a result of its smaller internal voltage swings, e.g., voltage swings between nodes A and B in the embodiment of FIG. 4 .
- the smaller output voltage swing of the modified latch 14 is below the input voltage sensitivity of next latch 18 .
- Amplifier 16 boosts the output voltage swing from the modified latch 14 to exceed the minimum switching threshold for latch 18 .
- the switching threshold for latch 18 is dependent on the frequency of external clock 22 .
- the overall sensitivity of the latch chain is dependent on the clock frequency.
- Amplifier 16 in FIG. 2 is not controlled by external clock 22 and therefore, can have a higher gain bandwidth product than modified latch 14 . Since amplifier 16 is unclocked, the transmission delay introduced by the device is intrinsic and associated with setup and transmission times of the amplifier's internal components. Nevertheless, the intrinsic transmission delays produced by the amplifier 16 should substantially match those delays caused by conventional latches, e.g., latches 18 , 20 , that are controlled by the external clock 22 . Amplifier 16 provides the gain necessary to produce an output voltage that properly operates the next latch 18 in response to lower input voltages than needed by clock-controlled latches 18 , 20 for proper operation.
- amplifier 16 receives an output voltage during a hold period of modified latch 14 and transmits an amplified voltage to the next latch 18 during that latch's sample period.
- amplifier 16 exhibits approximately a one half clock cycle delay between receipt of the output voltage from the modified latch 14 and transmission of the amplified output voltage to the next latch 18 so as to ensure that the new voltage arrives at the next latch 18 during that latch's sample period.
- FIG. 3 is an alternative embodiment of the latch chain of FIG. 2, wherein amplifier 16 comprises a cascaded sequence of N amplifier stages 27 1 , . . . , 27 N , wherein N ⁇ 1 .
- Each amplifier stage 27 1 , . . . , 27 N may be a Cherry-Hooper amplifier stage or any other differential amplifier which produces a characteristic delay between receipt of an input voltage and transmission of an amplified output voltage signal.
- the sequence of “N” cascaded amplifier stages is selected to produce a total delay of approximately one half of the clock cycle of external clock 22 .
- FIG. 4 is an exemplary modified latch 14 in FIG. 2 .
- Modified latch 14 includes matched output transistors 32 , 34 .
- the base of output transistors 32 , 34 are biased by voltages across matched resistors 36 , 38 .
- Resistors 36 , 38 are connected to a voltage source Vc and receive complementary current pairs from either sample stage 40 or hold stage 42 so that output transistors 32 , 34 produce complementary or opposite output voltages Vout and ⁇ overscore (V) ⁇ out.
- Sample and hold stages 40 , 42 are similar in construction, each including paired inputs 44 , 45 and paired outputs 46 , 47 . In response to complementary voltages being applied at inputs 44 , 45 , sample and hold stages 40 , 42 generate complementary current values on the paired outputs 46 , 47 of the same stage 40 , 42 , respectively.
- sample stage 40 In response to receiving input voltages Vin and ⁇ overscore (V) ⁇ in, sample stage 40 generates a voltage differential Vab between nodes A and B that corresponds to the logic value associated with Vin ⁇ overscore (V) ⁇ in.
- Hold stage 42 maintains a previously established voltage differential Vab at a value indicative of the stored logic value during the hold period. During the hold period, the output voltages Vout and ⁇ overscore (V) ⁇ out may be sampled by other digital devices to determine the logic value stored in latch 14 .
- FIG. 5 is an embodiment of the modified latch in FIG. 4 .
- Sample stage 40 comprises a pair of transistors 50 , 51 whose emitters are connected to the collector of a third transistor 52 .
- Hold stage 42 is similar in construction to that of sample stage 40 but, input voltages for the sample stage 40 are ⁇ overscore (V) ⁇ out and Vout, instead of Vin and ⁇ overscore (V) ⁇ in. Also, the transistors 52 of the sample stage 40 and the hold stage 42 turn on in response to high and low clock voltages, respectively.
- Sample and hold stages 40 , 42 are connected to external current sources 53 , 54 that produce different current values. Because each stage 40 , 42 has a different current source 53 , 54 , different currents are applied to resistors 36 , 38 , and thus, output transistors 32 , 34 produce different output voltages Vout at the end of sample and hold periods, respectively.
- the different currents in resistors 32 , 34 during the sample and hold periods imply that the absolute amplitude of the voltage difference Vab between nodes A and B changes between sample and hold periods unlike in conventional latch 1 of FIG. 1 .
- FIGS. 6 a - 6 c are timing diagrams that illustrate the operation of the sample and hold stages 40 , 42 of the modified latch 14 during a clock period T and subsequent or next clock period T′.
- either the sample stage 40 or the hold stage 42 is activated and applies a current to one of nodes A and B.
- the sample stage 40 of the modified latch 14 is active and applies a current to one of nodes A and B and the hold stage 42 is disconnected.
- the hold stage 42 becomes active and applies a current to one of nodes A and B and the sample stage 40 is disconnected.
- FIG. 6 b An exemplary timing diagram of the differential current in resistors 36 , 38 is represented by the curve shown in FIG. 6 b.
- the differential current in the resistors 36 , 38 increases until a final value of I 1 , at the end of the sample period, wherein I 1 is proportional to the input voltage to the latch 14 .
- the clock signal transitions low and the modified latch 14 switches to the hold period during which the differential current in resistors 36 , 38 changes from I 1 , at the beginning of the hold period, to I 2 , at the end of the hold period. If input voltages applied to the latch 14 did not change between the sampling portion of clock period T and the sampling portion of the previous clock period, then I 1 >I 2 as shown in FIG. 6 b.
- the curve representative of the voltage differential Vab between nodes A and B, as shown in FIG. 6 c, mirrors that of the current differential curve shown in FIG. 6 b merely being scaled by the resistance of matched resistor 36 or 38 .
- the current I 2 at the end of the hold portion of clock period T, is smaller than the current I 1 , at the end of the sample portion of the same clock period.
- the differential voltage Vab between nodes A and B is also smaller at the end of the hold portion of clock period T than at the end of the sample portion of the same clock period.
- less time is required to dissipate the stored charge Vab when transitioning to a new logic state during the next clock cycle T′ than in a conventional latch 1 of FIG. 1 where the same current is applied to nodes A and B during sample and hold periods.
- current sources 53 , 54 are set so that
- the stored voltage difference Vab is however associated with 12 , which has a smaller absolute value than I 1 . If a new logic value is to be loaded in latch 14 at the next clock edge, the previously stored voltage Vab must discharge during the sample period of that next clock period. Since
- the differential current in the resistors 36 , 38 is ⁇ I 2 , and the stored voltage difference Vab has the opposite sign with respect to its value at the end of the hold period of the clock cycle T.
Abstract
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US09/686,236 US6538486B1 (en) | 2000-10-11 | 2000-10-11 | Latch chain having improved sensitivity |
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US09/686,236 US6538486B1 (en) | 2000-10-11 | 2000-10-11 | Latch chain having improved sensitivity |
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Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020130692A1 (en) * | 1999-06-28 | 2002-09-19 | Broadcom Corporation | Current-controlled CMOS logic family |
US20020163374A1 (en) * | 1999-10-08 | 2002-11-07 | Lucent Technologies, Inc. | Trans-admittance trans-impedance logic for integrated circuits |
US20030005378A1 (en) * | 2001-06-28 | 2003-01-02 | Intel Corporation | Body bias using scan chains |
US20030118138A1 (en) * | 2001-12-21 | 2003-06-26 | James Chow | High speed differential data sampling circuit |
US20060001455A1 (en) * | 2004-07-01 | 2006-01-05 | Bernd Wuppermann | Circuit and method for performing track and hold operations |
US20070205818A1 (en) * | 2005-09-30 | 2007-09-06 | Alan Fiedler | High-speed data sampler with input threshold adjustment |
US20080030234A1 (en) * | 2004-10-05 | 2008-02-07 | Nec Corporation | Logic Circuit |
WO2009115865A1 (en) * | 2008-03-20 | 2009-09-24 | Freescale Semiconductor, Inc. | Latch module and frequency divider |
US7849208B2 (en) | 2002-08-30 | 2010-12-07 | Broadcom Corporation | System and method for TCP offload |
US7912064B2 (en) | 2002-08-30 | 2011-03-22 | Broadcom Corporation | System and method for handling out-of-order frames |
US7934021B2 (en) | 2002-08-29 | 2011-04-26 | Broadcom Corporation | System and method for network interfacing |
US8116203B2 (en) | 2001-07-23 | 2012-02-14 | Broadcom Corporation | Multiple virtual channels for use in network devices |
US8135016B2 (en) | 2002-03-08 | 2012-03-13 | Broadcom Corporation | System and method for identifying upper layer protocol message boundaries |
US8180928B2 (en) | 2002-08-30 | 2012-05-15 | Broadcom Corporation | Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney |
US8402142B2 (en) | 2002-08-30 | 2013-03-19 | Broadcom Corporation | System and method for TCP/IP offload independent of bandwidth delay product |
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US5969556A (en) * | 1997-03-05 | 1999-10-19 | Mitsubishi Denki Kabushiki Kaisha | Flip-flop circuit, parallel-serial converting circuit, and latch circuit |
US6218878B1 (en) * | 1997-01-25 | 2001-04-17 | Nippon Precision Circuits, Inc. | D-type flip-flop circiut |
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2000
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Patent Citations (3)
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US5844437A (en) * | 1996-03-28 | 1998-12-01 | Nec Corporation | Differential flipflop circuit operating with a low voltage |
US6218878B1 (en) * | 1997-01-25 | 2001-04-17 | Nippon Precision Circuits, Inc. | D-type flip-flop circiut |
US5969556A (en) * | 1997-03-05 | 1999-10-19 | Mitsubishi Denki Kabushiki Kaisha | Flip-flop circuit, parallel-serial converting circuit, and latch circuit |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6937080B2 (en) * | 1999-06-28 | 2005-08-30 | Broadcom Corporation | Current-controlled CMOS logic family |
US20020130692A1 (en) * | 1999-06-28 | 2002-09-19 | Broadcom Corporation | Current-controlled CMOS logic family |
US20020163374A1 (en) * | 1999-10-08 | 2002-11-07 | Lucent Technologies, Inc. | Trans-admittance trans-impedance logic for integrated circuits |
US7009438B2 (en) * | 1999-10-08 | 2006-03-07 | Lucent Technologies Inc. | Trans-admittance trans-impedance logic for integrated circuits |
US20030005378A1 (en) * | 2001-06-28 | 2003-01-02 | Intel Corporation | Body bias using scan chains |
US6763484B2 (en) * | 2001-06-28 | 2004-07-13 | Intel Corporation | Body bias using scan chains |
US8116203B2 (en) | 2001-07-23 | 2012-02-14 | Broadcom Corporation | Multiple virtual channels for use in network devices |
US9036643B2 (en) | 2001-07-23 | 2015-05-19 | Broadcom Corporation | Multiple logical channels for use in network devices |
US8493857B2 (en) | 2001-07-23 | 2013-07-23 | Broadcom Corporation | Multiple logical channels for use in network devices |
US20030118138A1 (en) * | 2001-12-21 | 2003-06-26 | James Chow | High speed differential data sampling circuit |
US8135016B2 (en) | 2002-03-08 | 2012-03-13 | Broadcom Corporation | System and method for identifying upper layer protocol message boundaries |
US8958440B2 (en) | 2002-03-08 | 2015-02-17 | Broadcom Corporation | System and method for identifying upper layer protocol message boundaries |
US8451863B2 (en) | 2002-03-08 | 2013-05-28 | Broadcom Corporation | System and method for identifying upper layer protocol message boundaries |
US8345689B2 (en) | 2002-03-08 | 2013-01-01 | Broadcom Corporation | System and method for identifying upper layer protocol message boundaries |
US7934021B2 (en) | 2002-08-29 | 2011-04-26 | Broadcom Corporation | System and method for network interfacing |
US8180928B2 (en) | 2002-08-30 | 2012-05-15 | Broadcom Corporation | Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney |
US8677010B2 (en) | 2002-08-30 | 2014-03-18 | Broadcom Corporation | System and method for TCP offload |
US7849208B2 (en) | 2002-08-30 | 2010-12-07 | Broadcom Corporation | System and method for TCP offload |
US8549152B2 (en) | 2002-08-30 | 2013-10-01 | Broadcom Corporation | System and method for TCP/IP offload independent of bandwidth delay product |
US7912064B2 (en) | 2002-08-30 | 2011-03-22 | Broadcom Corporation | System and method for handling out-of-order frames |
US7929540B2 (en) | 2002-08-30 | 2011-04-19 | Broadcom Corporation | System and method for handling out-of-order frames |
US8402142B2 (en) | 2002-08-30 | 2013-03-19 | Broadcom Corporation | System and method for TCP/IP offload independent of bandwidth delay product |
US7154306B2 (en) * | 2004-07-01 | 2006-12-26 | Agilent Technologies, Inc. | Circuit and method for performing track and hold operations |
US20060001455A1 (en) * | 2004-07-01 | 2006-01-05 | Bernd Wuppermann | Circuit and method for performing track and hold operations |
US20080030234A1 (en) * | 2004-10-05 | 2008-02-07 | Nec Corporation | Logic Circuit |
US7671652B2 (en) * | 2004-10-05 | 2010-03-02 | Nec Corporation | Logic circuit for use in a latch circuit and a data reading circuit or the like which includes such a latch circuit |
US20070205818A1 (en) * | 2005-09-30 | 2007-09-06 | Alan Fiedler | High-speed data sampler with input threshold adjustment |
US7813460B2 (en) | 2005-09-30 | 2010-10-12 | Slt Logic, Llc | High-speed data sampler with input threshold adjustment |
US8130018B2 (en) | 2008-03-20 | 2012-03-06 | Freescale Semiconductor, Inc. | Latch module and frequency divider |
WO2009115865A1 (en) * | 2008-03-20 | 2009-09-24 | Freescale Semiconductor, Inc. | Latch module and frequency divider |
US20110018594A1 (en) * | 2008-03-20 | 2011-01-27 | Freescale Semiconductor, Inc | Latch module and frequency divider |
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