US6528357B2 - Method of manufacturing array substrate - Google Patents
Method of manufacturing array substrate Download PDFInfo
- Publication number
- US6528357B2 US6528357B2 US09/266,804 US26680499A US6528357B2 US 6528357 B2 US6528357 B2 US 6528357B2 US 26680499 A US26680499 A US 26680499A US 6528357 B2 US6528357 B2 US 6528357B2
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- array substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 78
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- 238000000034 method Methods 0.000 claims abstract description 75
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- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
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- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims abstract description 12
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
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- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
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- 239000010955 niobium Substances 0.000 claims description 4
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
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- 229910052804 chromium Inorganic materials 0.000 claims description 2
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- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- XMBWDFGMSWQBCA-UHFFFAOYSA-N hydrogen iodide Chemical compound I XMBWDFGMSWQBCA-UHFFFAOYSA-N 0.000 claims description 2
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
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- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims description 2
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 2
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- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 claims description 2
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- 229910052727 yttrium Inorganic materials 0.000 claims description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052688 Gadolinium Inorganic materials 0.000 claims 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims 1
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 claims 1
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 claims 1
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- 239000004973 liquid crystal related substance Substances 0.000 abstract description 11
- UBSJOWMHLJZVDJ-UHFFFAOYSA-N aluminum neodymium Chemical compound [Al].[Nd] UBSJOWMHLJZVDJ-UHFFFAOYSA-N 0.000 abstract description 9
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Images
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Definitions
- the present invention relates to the manufacturing method of array substrates for use in flat panel display devices including liquid crystal display (LCD) devices.
- LCD liquid crystal display
- LCD devices are more frequently developed to replace conventional cathode-ray tube (CRT) units; in particular, LCD devices are becoming commercially attractive more and more due to their advantage such as light weight, thinness, low power consumption and the like.
- the active-matrix LCD device includes a liquid crystal layer held between an array substrate and a counter substrate with orientation films being provided between the liquid crystal layer and any one of such substrates.
- the array substrate has, on a transparent insulative substrate made of glass, quartz or the like, a plurality of signal lines and a scanning lines arranged in a matrix form.
- a thin film transistor abbreviated to “TFT” hereinafter
- a-Si:H semiconductor thin film such as amorphous silicon
- the TFT has a gate electrode electrically connected to a corresponding one of the scanning lines, a drain electrode electrically connected to a corresponding signal line, and a source electrode electrically connected to a transparent conductive material constituting an associated pixel electrode, which material may be indium-tin-oxide (ITO).
- ITO indium-tin-oxide
- the counter substrate is constituted from a glass substrate on which an counter electrode made of ITO is disposed; where displaying of color images is required, a color filter layer will be additionally provided thereon.
- the scanning lines are formed of aluminum (Al) and anodic-oxidized coating layer, which coating layer is formed by anodic oxidation processing on surface layer of the Al in electrolytic solution.
- Storage capacitor lines are formed in the same manner.
- Manufacturing method of these lines is as follows: firstly, an Al layer is deposited on a glass substrate by sputtering technique and then subjected to a patterning treatment to form a prescribed Al wiring pattern; then, certain region of the wiring pattern is selectively covered with anodic-oxidation-proof masking material such as resist, to leave certain Al pattern in the region intact; subsequently, by applying a prescribed voltage onto the Al pattern, an Al oxide layer is formed on the Al wiring pattern to prescribed thickness, for example to 200-300 nm. In this way, the scanning lines, gate electrodes and storage capacitor lines are formed. Subsequently, active portion of the TFT, the pixel electrode, the signal lines, and the source and drain electrodes are formed in a step-by-step manner, to complete the array substrate of the active-matrix LCD device.
- anodic-oxidized films have to cover the surface of the aluminum wiring that is a low-resistivity wiring
- the manufacturing method requires an anodic oxidation processing including a mask-forming process, and requires extra wiring patterns for voltage supply for the anodic oxidation processes.
- gate wiring patterns which are wiring patterns for scanning lines and gate electrodes. This restriction leads to lower productivity and lower freedom in designing.
- the invention aims to secure low-resistivity of the wiring and yet effectively prevent interlayer short-circuit caused by the deformation of the wiring.
- the invention also aims to prevent corrosion of the wiring metal layer during the etching process, and thereby prevent decrease of production yield.
- the invention according to claim 1 provides a method of manufacturing an array substrate for a display device having a scanning line and gate electrode on a substrate; a thin film transistor having a gate insulator film on said scanning line and gate electrode, a semiconductor film thereon, source and drain electrodes electrically connected to said semiconductor film; a signal line as taken out of the drain electrode to extend substantially perpendicularly to said scanning line; and a pixel electrode electrically connected to the source electrode, comprising steps of: forming said scanning line and gate electrode by patterning a multi-layer metal film having an aluminum alloy layer and a refractory metal layer; and depositing said gate insulator film in direct contact with said scanning line and gate electrode at a temperature not less than 300° C.
- the above construction of the scanning line is exemplified as follows.
- an aluminum-neodymium alloy Al—Nd
- Al—Nd aluminum-neodymium alloy
- a refractory metal is deposited on the Al alloy.
- a gate insulator film is formed by plasma CVD techniques at substrate temperature of 350° C.
- the Al alloy undergoes no damage from such etching agents because the refractory metal and the gate insulator film are disposed between the etching agents and the scanning line comprised of Al alloy.
- FIG. 1 is a diagram schematically showing a plan view of part of an array substrate in accordance with one preferred embodiment of the present invention.
- FIG. 2 is a schematic cross-section of the liquid crystal display device taken along line A—A′ in FIG. 1 .
- FIG. 3 is a schematic cross-section of the liquid crystal display device taken along line B—B′ in FIG. 1 .
- FIG. 4 is a schematic cross-section of the liquid crystal display device taken along line C—C′ in FIG. 1 .
- FIG. 5 is a schematic cross-section of the liquid crystal display device taken along line D—D′ in FIG. 1 .
- FIG. 6 is a schematic cross-section of the liquid crystal display device taken along line E—E′ in FIG. 1 .
- FIG. 7 is a diagram for explanation of a first step in the manufacture of the array substrate shown in FIG. 1 .
- FIG. 8 is a diagram for explanation of a second step in the manufacture of the array substrate shown in FIG. 1 .
- FIG. 9 is a diagram for explanation of a third step in the manufacture of the array substrate shown in FIG. 1 .
- FIG. 10 is a diagram for explanation of a fourth step in the manufacture of the array substrate shown in FIG. 1 .
- FIG. 11 is a diagram for explanation of a fifth step in the manufacture of the array substrate shown in FIG. 1 .
- FIG. 12 is a diagram for explanation of a sixth step in the manufacture of the array substrate shown in FIG. 1 .
- FIG. 13 is a diagram for explanation of a seventh step in the manufacture of the array substrate shown in FIG. 1 .
- LCD liquid crystal display
- This LCD device 1 is of the light transmissive type capable of displaying color images. As shown in FIG. 2, LCD device 1 has an array substrate 100 , an counter substrate 200 , and a twisted nematic (TN) liquid crystal held therebetween through orientation films 141 , 241 being laid between it and substrates 100 , 200 . These orientation films 141 , 241 are made of polyimide resin. Also, polarization plates 311 , 313 are adhered to the outer surfaces of array substrate 100 and counter substrate 200 , respectively.
- TN twisted nematic
- FIG. 1 shows a schematical plan view of the array substrate 100 , wherein the lower side of this drawing is to be located at the upper side of the display screen of LCD device 1 while allowing scanning lines to be successively selected in the sequence from the lower to the upper side of the illustration.
- the array substrate 100 includes 480 scanning lines 111 as disposed on a glass substrate 101 .
- One end of each scanning line 111 is taken out to extend toward one edge 101 a of the glass substrate 101 , and is electrically connected through a slant wiring line section 150 to a corresponding one of scanning line connection pads 152 .
- the scanning lines 111 have a double-layer structure, consisting of Aluminum-Neodymium (Al—Nd) alloy film 1110 , Nd content of which is 2 atomic %, and molybdenum (Mo) film 1111 .
- Al—Nd Aluminum-Neodymium
- Mo molybdenum
- atomic % stands for a molar % in which number of atoms is taken as elementary entity; that is a percentage calculated as follows—number of atoms (molar number) of additive element is divided by number of atoms (molar number) in whole of the alloy, and then multiplied by 100.
- the array substrate 100 also includes 1,920 signal lines 110 , which lines extend to intersect the scanning lines 111 at substantially right angles on the glass substrate 101 .
- Each signal line 110 is taken out to run toward the other edge 101 b of the glass substrate 101 , and is electrically connected via a slant wiring line section 160 to a corresponding signal line connection pad 162 .
- the signal lines 110 has a three-layer structure, consisting of a first layer made of Mo, a second layer made of Al, and a third layer made of Mo.
- a TFT 112 is disposed near each of the cross-points of the scanning lines 111 and signal lines 110 .
- a pixel electrode 131 which is made of ITO and coupled to TFT 112 is disposed over the scanning line 111 and signal line 110 with an interlayer dielectric film 127 being provided therebetween.
- This interlayer dielectric film 127 may be an inorganic dielectric film made of silicon nitride, silicon oxide or the like, or an organic resin coated film of acryl-based material; preferably, the interlayer dielectric film is constituted from a multi-layer film of a combination of such inorganic dielectric film and organic resin coated film thereby further improving the surface flatness and interlayer dielectricity.
- TFT 112 An explanation will be given of the structure of TFT 112 .
- Each scanning line 111 includes a fine strip-shaped elongate region 113 extending along the signal line 110 to overlap the edges 131 a , 131 b of one neighboring pixel electrode 131 .
- the pixel electrode 131 and the elongate region 113 from a next scanning line 111 with respect to the scanning line 111 for the pixel electrode 131 overlap each other at certain overlap region (OS), with a first gate insulator film 115 , a second gate insulator film 117 and interlayer dielectric film 127 being laid therebetween, causing such overlap region (OS) to constitute a storage capacitance (Cs).
- OS overlap region
- Cs storage capacitance
- the pixel electrode 131 overlaps the prestage scanning line 111 per se through the first gate insulator film 115 , second gate insulator film 117 and interlayer dielectric film 127 to form a further overlap region which also constitutes the storage capacitor (Cs).
- the counter substrate 200 opposing this array substrate 100 is disposed on a glass substrate 201 , and includes a matrix-shaped light shielding film 211 made of a chosen resin material which shields light rays towards the TFT 121 region and from the gap spacing between the pixel electrode 131 and any one of signal lines 110 and scanning lines 111 .
- a color filter 221 having three color components of red (R), green (G) and blue (B) is disposed in a certain region corresponding to the pixel electrode 131 .
- another counter electrode 231 made of a transparent conductive material.
- the interlayer dielectric film 127 alone or both the first and second gate insulator films 115 , 117 and interlayer dielectric film 127 are disposed between the pixel electrode 131 and any one of signal lines 110 and scanning lines 111 , it is possible for pixel electrode 131 to be disposed sufficiently close to or over respective wiring lines 110 , 111 , thereby enabling achievement of increased aperture ratio.
- Another advantage of the illustrative embodiment is that since the storage capacitor (Cs) is formed between the pixel electrode 131 and the elongate region 113 extended from one scanning line 111 neighboring to such pixel electrode 131 , it is no longer necessary to employ any extra storage capacitor wiring lines enabling achievement of further increased aperture ratio.
- TFT 112 is constituted using as its gate electrode a specific region taken out of the signal line 110 to extend along the signal line 110 , it becomes possible for pixel electrode 131 to overlap the prestage scanning line 111 per se. This may advantageously serve to attain sufficient storage capacitor (Cs) while enabling achievement of high aperture ratio.
- the pixel area is defined in planar size not by the light-shield film 211 disposed on the counter electrode 200 , but by the scanning line 111 and its elongate region 113 on the array substrate 100 . Accordingly, the alignment accuracy of the product is dependent solely upon an alignment accuracy of a first mask pattern for use in patterning scanning lines 111 to a fifth mask pattern for patterning pixel electrodes 131 , rather than depending on an alignment accuracy of the array substrate 100 to counter substrate 200 . This may avoid the need to add extra margins to the width of light shield film 211 in view of possible alignment variations of the array substrate 100 to counter substrate 200 , thus enabling accomplishment of further increased aperture ratio.
- Yet another advantage of the embodiment is that even when the elongate region 113 of scanning line 111 is fully extended along the edges 131 a , 131 b of pixel electrode 131 along the signal line 110 in order to define the boundary of pixel area, it is possible to suppress or eliminate an excessive increase in storage capacitor (Cs) without degrading the productivity.
- the interlayer dielectric film 127 is disposed—in addition to the first gate insulator film 115 and second gate insulator film 117 —between the pixel electrode 131 and the elongate region 113 of scanning line 111 .
- a further advantage of the embodiment is that, as shown in FIG. 5, the signal line 110 is exactly identical in outline to a low-resistance semiconductor film 124 a and semiconductor film 120 . More specifically, not only the first and second gate insulator films 115 , 117 but also the low-resistance semiconductor film 124 a and semiconductor film 120 are laminated at the individual one of crosspoints of signal lines 110 and scanning lines 111 . Due to this, even on occasions where mask deviations take place during patterning process steps, the capacitance can remains unchanged between the signal lines 110 and scanning lines 111 , thereby suppressing variations or fluctuations in scanning-line capacitance or in signal-line capacitance among devices manufactured.
- this may suppress or eliminate interlayer shorting otherwise occurring due to static electricity at crosspoints of signal lines 110 and scanning lines 111 , contaminants during process steps, or presence of pinholes in respective insulator films 115 , 117 , thus enabling provision of higher yield of production.
- a still further advantage is that since the signal line 110 coincides in outline with low-resistance semiconductor film 124 a as shown in FIG. 6, unlike the prior art causing patterning to be done at separate process steps, it is possible to sufficiently suppress occurrence of capacitive variations between the signal lines 110 and scanning lines 111 even if mask alignment deviations take place during respective patterning steps.
- a yet further advantage is that when the signal line 110 is designed to overlap the elongate region 113 of scanning line 111 , that is, even when in the structure of FIG. 6 the elongate region 113 being disposed neighboring through the signal line 110 is connected under the signal line 110 , since the semiconductor film 120 in addition to respective insulator films 115 , 117 is disposed between the signal line 110 and the elongate region 113 of scanning line 111 , any interlayer shorting can be prevented from occurring due to static electricity, contaminants during processes or pinholes within respective insulator films 115 , 117 , attaining high manufacturing yield.
- the capacitive coupling between signal line 110 and pixel electrode 131 can be shielded by elongate region 113 lightening adverse interference of the potential at pixel electrode 131 with potential changes of signal line 110 .
- the semiconductor film 120 as disposed between signal line 110 and insulator films 115 , 117 and low-resistance semiconductor film 124 a are identical in outline with signal line 110 . For these reasons, it is permissible that signal line 110 and pixel electrode 131 are located closely to each other attaining further increased aperture ratio.
- FIGS. 1 and 3 A reference is made to FIGS. 1 and 3 for explanation of the structure near the outer peripheral section of scanning line 111 .
- the scanning line 111 is taken out on the side of one edge 101 a of the glass substrate 101 , constituting a lower-layer wiring line section 111 a that is guided toward a slant wiring line section 150 and a scanning-line connection pad 152 .
- the slant wiring line section 150 two laminated insulator films 115 , 117 are disposed on the lower-layer wiring line section 111 a as extended from the scanning line 111 . Also provided on these two insulator films 115 , 117 are a semiconductor coated film 119 , a low-resistance semiconductor coated film 123 and an upper-layer wiring line section 125 a consisting of a Mo—W alloy film being same as signal line 110 in material and in process, which are laminated sequentially. An interlayer dielectric film 127 is formed on the upper-layer wiring line section 125 a.
- a first contact hole 153 and a second contact hole 154 making a pair are disposed closely to each other in the wiring-line direction, whereby the lower-layer wiring line section 111 a which is extended from the scanning line 111 and the upper-layer wiring line section 125 a are electrically connected to each other by the signal line connection layer 131 , which is the same in material (ITO, here) and process as pixel electrode 131 , through the first contact hole 155 and second contact hole 156 .
- the second contact hole 154 is an opening penetrating the two-layered insulator films 115 , 117 , semiconductor coated film 119 , low-resistance semiconductor coated film 123 and upper-layer wiring line section 125 a causing the principal surface of the lower-layer wiring line section 111 a to be partly exposed
- the first contact hole 153 is an opening penetrating the interlayer dielectric film 127 exposing part of the principal surface of upper-layer wiring line section 125 a.
- first contact hole 155 and second contact hole 156 are disposed closely to each other in the wiring-line direction, whereby the lower-layer wiring line section 111 a of scanning line 111 and the upper-layer wiring line section 125 a are electrically connected by the signal line connection layer 131 —this is the same in material (ITO, here) and process as pixel electrode 131 —to each other through the first contact hole 155 and second contact hole 156 .
- the second contact hole 156 is an opening penetrating the double-layered insulator films 115 , 117 , semiconductor coated film 119 , low-resistance semiconductor coated film 123 and upper-layer wiring line section 125 a causing the principal surface of the lower-layer wiring line section 111 a to be partly exposed in the same manner as in the second contact hole 154 as mentioned above;
- the first contact hole 155 is similar to the aforesaid first contact hole 153 in that it is an opening penetrating the interlayer dielectric film 127 exposing part of the principal surface of upper-layer wiring line section 125 a.
- the resulting slant wiring line section 150 of scanning line 111 is constituted from the upper-layer wiring line section 125 a as comprised of a Mo—W alloy film that is fabricated using the same material and same process as the signal line 110 subjected to patterning separately, and the lower-layer wiring line section 111 a as extended from the scanning line 111 made of Al—Y alloy film; by these two layers, the base section of slant wiring line section 150 and scanning line pad 152 are electrically connected together.
- the slant wiring line section 150 includes the lower-layer wiring line section 111 a formed of Al—Y alloy that is one low-resistance material employing Al as its major component.
- the region of second contact hole 156 that is, the laminated region of lower-layer wiring line section 111 a and signal line connection layer 131 mainly functions as an interconnection region of the scanning line pad 152 .
- FIGS. 1 and 4 A reference is made to FIGS. 1 and 4 for explanation of the structure near the outer peripheral section of signal lines 110 .
- a lower-layer wiring line section 111 b which is the same in material and in process as scanning lines 111 , is disposed at the slant wiring line section 160 of signal line 110 and the signal line pad 162 on the side of one edge 101 b of glass substrate 101 in a one-to-one correspondence manner with each signal line 110 .
- the slant wiring line section 160 two layers of insulator films 115 , 117 are disposed on the lower-layer wiring line section 111 b.
- semiconductor coated film 119 is provided on such two-layered insulator films 115 , 117 as semiconductor coated film 119 , low-resistance semiconductor coated film 123 and upper-layer wiring line section 125 b as extended from signal line 110 while causing the interlayer dielectric film 127 to be disposed on the upper-layer wiring line section 125 b.
- a first contact hole 163 and a second contact hole 164 forming a pair are disposed closely to each other in the wiring-line direction, whereby the upper-layer wiring line section 125 b which is extended from the scanning line 111 and the lower-layer wiring line section 111 b are electrically connected to each other by signal line connection layer 131 same in material—ITO, here—and process as pixel electrode 131 .
- the second contact hole 164 is an opening penetrating the double-layered insulator films 115 , 117 , semiconductor coated film 119 , low-resistance semiconductor coated film 123 and upper-layer wiring line section 125 b causing the principal surface of the lower-layer wiring line section 111 b to be partly exposed
- the first contact hole 163 is an opening penetrating the interlayer dielectric film 127 exposing part of the principal surface of upper-layer wiring line section 125 b.
- first contact hole 165 and second contact hole 166 are disposed closely to each other along the wiring-line direction, whereby the upper-layer wiring line section 125 b extended from signal line 110 and the lower-layer wiring line section 111 b are electrically connected to each other by the signal line connection layer 131 , which is the same in material (ITO, here) and process as pixel electrode 131 .
- the second contact hole 166 is an opening penetrating the double-layered insulator films 115 , 117 , semiconductor coated film 119 , low-resistance semiconductor coated film 123 and upper-layer wiring line section 125 b causing the principal surface of the lower-layer wiring line section 111 b to be partly exposed in the same manner as in the second contact hole 164 as discussed previously;
- the first contact hole 165 is similar to the aforesaid first contact hole 163 in that it is an opening penetrating the interlayer dielectric film 127 exposing part of the principal surface of upper-layer wiring line section 125 b.
- the upper-layer wiring line section 125 b as extended from the signal line 110 and the lower-layer wiring line section 111 b comprised of the same material as scanning lines 111 and fabricated in the same process as scanning lines 111 are disposed in lamination; by these two layers, the base section of slant wiring line section 160 and the signal line pad 162 are electrically coupled together.
- the slant wiring line section 160 includes the lower-layer wiring line section 111 b formed of Al—Nd alloy that is a low-resistance material.
- the region of second contact hole 166 that is, the laminated region of lower-layer wiring line section 111 b and signal line connection layer 131 acts as the major interconnection region of the signal line pad 162 .
- connection region of each scanning line pad 152 is mainly constituted from the lamination structure of the lower-layer wiring line section 111 a as taken out of a corresponding scanning line 111 and the signal line connection layer 131 made of ITO that is the same as the material constituting pixel electrodes 131 ;
- the connection region of each signal line connection pad 162 is mainly constituted from the lower-layer wiring line section 111 b as formed simultaneously with fabrication of scanning lines 111 , and the signal line connection layer 131 made of ITO that is the same as the material constituting pixel electrodes 131 , wherein the structure is substantially the same.
- a method of forming or manufacturing the array substrate 100 will be described in detail with reference to FIGS. 7 through 13.
- An Al—Nd alloy film and an Mo film are sequentially deposited by sputtering techniques on the glass substrate 101 to a thickness of 300 nanometers (nm) and to 30 nm, respectively.
- Thickness of the Mo film in the range of 50-500 nm, preferably 50-300 nm, is proper.
- the thickness is less than the 50 nm, the hillock on the Al film is not sufficiently suppressed. Meanwhile, when the thickness exceeds the 500 nm, a problem of at-step-portion discontinuation of the insulator film arises.
- Al alloy film even in the case where an aluminum-yttrium film (Al—Y film, 2 atomic % of Y) is adopted for example, things goes on almost the same manner with the case where the Al—Nd alloy film is adopted.
- An aluminum-gadolinium film (Al—Gd film, 2 atomic % of Gd), an aluminum-scandium film (Al—Sc film, 2 atomic % of Sc) or the like may also be used.
- the Al alloy film undergoes heat-treatment effects by film-forming process of plasma CVD techniques or the like. And, only impurity ingredients segregated to the vicinity of inter-crystal-grains surface, so as to obstruct moving of Al atoms.
- the impurity ingredients also exists in polycrystalline structure, so as to increase the resistivity by about 30%.
- Content of the above additive elements in the Al alloy ranges preferably from 0.5 to 10 atomic %, more preferably from 1 to 3 atomic %.
- content of the additive elements is below 0.5 atomic %, the effect of preventing hillocks by raising apparent melting point or softening temperature is not sufficient in many cases. Meanwhile, when the content of the additive elements exceeds 10 atomic %, it is undesirable because resistivity and production cost are increased.
- the Al alloy film may be an alloy film that contains at least two additive elements selected from among Sc, Y, Nd, samarium (Sm), and Gd. In this case, it is preferable to set sum of the contents of additive elements in the range of 0.5-10 atomic %.
- Al—Nd—Y alloy containing 1 atomic % of Nd and 1 atomic % of Y, or the like.
- any one metal selected from a group consisting of molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), chromium (Cr), zirconium (Zr) and hafnium (Hf), vanadium (V) and niobium (Nb) may be used.
- Mo molybdenum
- tungsten (W) titanium
- Ta tantalum
- Cr chromium
- Zr zirconium
- V vanadium
- Nb niobium
- any one alloy comprised of two or more metals selected from this group may be used.
- molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta) are preferable.
- a pattern of scanning-lines and a part of storage capacitor lines are formed by use of photolithography techniques. Then, an etching process is carried out in a taper-shape forming manner, using an acid mixture consisting of phosphoric acid, acetic acid or nitric acid, to complete scanning lines and storage capacitor lines pattern.
- a gate electrode is formed which is integral with a corresponding scanning line 111 and is taken out to extend in a specific direction at right angles to scanning lines 111 .
- elongate regions 113 are also fabricated simultaneously each of which is taken out to extend in the perpendicular direction to scanning lines 111 for formation of the storage capacitor (Cs) required (see FIG. 1 ).
- a first gate insulator film 115 made of silicon oxide (SiO X ) is deposited using atmospheric-pressure plasma chemical vapor deposition (CVD) techniques to a thickness of 150 nm while heating the glass substrate 101 to a temperature not less than 300° C., preferably not less than 330° C.
- CVD atmospheric-pressure plasma chemical vapor deposition
- a second gate insulator film 117 made of silicon nitride (SiN X ) 150 nm thick, a 50 nm thick semiconductor coated film 119 made of a-Si:H, and 200 nm thick silicon-nitride channel protective coated film 121 are formed sequentially in this order without exposing them to atmosphere.
- a silicone nitride film may be adopted for each of the first gate insulator film 115 and the second gate insulator film 117 which are mentioned above.
- a silicone nitride film By adopting a silicone nitride film, in addition to the aforementioned dielectric strength, it become easy to obtain an optical band gap value not less than 5 eV.
- the SiO X film which constitutes the above-mentioned first gate insulator film 115 , may be replaced by an SiO 2 film that is formed in use of a thermal CVD technique by heating the glass substrate 101 to a temperature not less than 300° C., preferably not less than 465° C. Even in this case, the hillock is almost suppressed due to synergy effect of Al alloy and Mo, although the heat treatment should give rise a concern of the hillock formation on Al film.
- the channel protective coated film 121 is subject using rear-surface exposure techniques to patterning process with the scanning lines 111 being as a mask while the coated film 121 is self-aligned with scanning lines 111 , and is then subject to exposure process using a second mask pattern to ensure that it corresponds to each TFT region. Thereafter, development and patterning (second patterning) are performed to fabricate an island-like channel protective film 122 .
- a semiconductor coated film 119 After completion of the third step, as shown in FIG. 10, surface treatment using hydrogen fluoride (HF) solution is applied to the surface of a semiconductor coated film 119 as exposed to obtain good ohmic contacts. Then, a low-resistance semiconductor coated film 123 which is made of n + type-doped amorphous silicon (n + a-Si:H) containing therein phosphorus (P) impurity is deposited by low-pressure plasma CVD techniques to a thickness of 30 nm.
- HF hydrogen fluoride
- a three-layer film 125 of 300 nm thick having a three-layer structure, consisting of the first layer in which Mo is predominant, the second layer in which Al is predominant, and the third layer in which Mo is predominant.
- the resulting structure is subject to exposure and development process using a third mask pattern so that all of the three-layer film 125 , low-resistance semiconductor coated film 123 and semiconductor coated film 119 are patterned by plasma etching techniques at a time by controlling the selective etching rate of the first gate insulator film 115 or second gate insulator film 117 and the channel protective film 122 .
- This is the third patterning process.
- the low-resistance semiconductor film 124 a and source electrode 126 b are formed integrally, whereas low-resistance semiconductor film 124 b and its associated signal line 110 are formed integrally.
- the three-layer film 125 is patterned along the lower-layer wiring line section 111 a forming the upper-layer wiring line section 125 a , while the low-resistance semiconductor coated film 123 and semiconductor coated film 119 are patterned simultaneously along the upper-layer wiring line section 125 a .
- openings 154 a , 156 a are formed which correspond to the aforementioned second contact holes 154 , 156 and penetrate the upper-layer wiring line section 125 a , low-resistance semiconductor coated film 123 and semiconductor coated film 119 .
- the three-layer film 125 is patterned along the lower-layer wiring line section 111 b forming the upper-layer wiring line section 125 a as extended from signal line 110 , while the low-resistance semiconductor coated film 123 and semiconductor coated film 119 are patterned simultaneously along the upper-layer wiring line section 125 b .
- openings 164 a , 166 a are formed which correspond to the aforementioned second contact holes 164 , 166 and penetrate the upper-layer wiring line section 125 b , low-resistance semiconductor coated film 123 and semiconductor coated film 119 .
- the interlayer dielectric film 127 of silicon nitride is then deposited on resultant structure to a thickness of 200 nm.
- both the interlayer dielectric film 127 and the first and second gate insulator films 115 , 117 corresponding to the openings 154 a , 156 a are removed away at a time to form second contact holes 154 , 156 (the fourth patterning); simultaneously, the interlayer dielectric film 127 near the second contact holes 154 , 156 is removed to form first contact holes 153 , 155 each of which makes a pair with a corresponding one of the second contact holes 154 , 156 .
- both the interlayer dielectric film 127 and the first and second gate insulator films 117 corresponding to the openings 164 a , 166 a are removed away at a time forming second contact holes 164 , 166 (the fourth patterning); at the same time, the interlayer dielectric film 127 near the second contact holes 164 , 166 is removed away forming first contact holes 163 , 165 which constitute pairs with the second contact holes 164 , 166 , respectively.
- an ITO film is deposited by sputtering techniques to a thickness of 100 nm.
- the resulting structure is then subject to patterning treatment by exposure, development and dry etching techniques using a fifth mask pattern (the fifth patterning), thereby forming pixel electrodes 131 .
- the sputtering for ITO film was carried out at following conditions so as to deposit an amorphous ITO film.
- a target made by Mitsui Mining and Smelt Co. was used; charging electric power on Sputtering was set at 3.5 kW; pressure at film-forming process was set at 0.7 Pa; flow rate of H 2 O was set at 0.5 sccm.
- Thus formed ITO film had a sheet resistivity of 400 ⁇ / ⁇ .
- This amorphous ITO film was then subjected to the patterning treatment by use of etching techniques, and subsequently subjected to heat treatment for converting the film to a crystalline ITO film having a low resistivity.
- the resulted ITO film have a sheet resistivity of 50 ⁇ / ⁇ , which is sufficiently low enough.
- the patterning treatment is facilitated by conducting the patterning treatment at the state of amorphous ITO film as above.
- an IZO (Indium-Zinc-Oxide) film may be adopted in a totally same manner.
- patterning treatment is easily achieved in the same manner with the amorphous ITO film, while its resistivity is sufficiently low enough even without heat treatment.
- HBr aqueous solution On wet-etching of the ITO film, HBr aqueous solution is used. In this occasion, no damage by the etching is observed on the Al alloy film.
- HBr+FeCl 3 As for the other etching liquids, HBr+FeCl 3 , HI aqueous solution, HCl aqueous solution or oxalic acid aqueous solution may also be used.
- a signal line connection layer 131 is formed electrically connecting the first contact holes 153 , 155 to second contact holes 154 , 156 . This results in that the scanning line 111 and scanning line pad 152 are electrically coupled together by the double-layered slant wiring line section 150 consisting of the lower-layer wiring line section 111 a and upper-layer wiring line section 125 a.
- a signal line connection layer 131 is formed electrically connecting the first contact holes 163 , 165 to second contact holes 164 , 166 . This results in that the signal line 110 and signal line pad 162 are electrically coupled to each other by the double-layered slant wiring line section 160 consisting of the lower-layer wiring line section 111 b and upper-layer wiring line section 125 b.
- the array substrate can be formed or manufactured by use of basically five masks. More specifically, the productivity can be improved with a decreased number of masks used while avoiding a decrease in the manufacturing yield thereof, as a result of locating the pixel electrodes at the uppermost position, and of employing a specific manufacturing method allowing several process steps to be done simultaneously which steps include: patterning the semiconductor coated films as well as the signal lines, source and drain electrodes at a time with the same mask pattern used therefor; forming the contact holes for interconnection of each source electrode and its associated pixel electrode; and forming the contact holes for exposure of contact nodes of signal lines and scanning lines.
- each slant wiring line section of signal lines and scanning lines has a double-layered structure consisting of the upper-layer wiring line section constituting an individual signal line and the lower-layer wiring line section constituting a corresponding scanning line permitting electrical connection between the base section of each slant wiring line section and a corresponding pad associated therewith.
- the slant wiring line section includes a specific wiring line layer that is comprised of a low-resistance material using at least Al as its major component.
- signal line pads and scanning line pads for use in connecting bumps of external driver ICs and/or terminals of TCPs are substantially the same in structure, it becomes possible to allow the both to be connected under the same condition.
- resistance of a scanning line is about 4.1 k ⁇ when 10 ⁇ m of average wiring width and 30.5 cm of wiring length are adopted for the device of 15-inch diagonal-size XGA. Reduction of the resistance is known to be achieved when compared with the resistance of about 5.6 k ⁇ for a scanning line having an anodic oxidized Al layer of 200 nm thick and a remaining Al layer of 200 nm thick (initial thickness of the layer before anodic oxidation is 300 nm).
- the embodiment enables omission of anodic oxidation process including mask forming process for the anodic oxidation, thereby making a contribution to improving the productivity.
- the scanning line 111 has a double-layer structure consisting of Al—Nd alloy film 1110 and Mo film 1111 , forming of the hillock at heat treatment is sufficiently suppressed. Moreover, because of this double-layer structure, good cross-sectional shape tapered toward its upper surface (normal taper) is achieved due to etching-rate difference.
- the etching of the ITO film at the seventh process step is carried out in a cathode-coupling type etching apparatus by a dry-etching technique using HI+Ar(argon) gas system, instead of the above-mentioned wet-etching technique. Except this point, the manufacturing method of the modification is in a totally same manner with that of the above-mentioned embodiment.
- the aluminum alloy 1110 that forms the scanning line 111 undergoes no etching damage from the etching gas, because of the presence of Mo film 1111 , the first gate insulator film 115 and other films between the scanning line 111 and the etching gas.
- the etching gas causes no corrosion on “a foundation or a first coat” (aluminum alloy 1110 and the like) through a pin-hole in insulator films, in contrast with the case of the above-mentioned wet-etching technique.
- dry-etching techniques no problem arises on disposal of chemical liquid.
Abstract
Description
Claims (13)
Applications Claiming Priority (9)
Application Number | Priority Date | Filing Date | Title |
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JP10-063253 | 1998-03-13 | ||
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JP10-63251 | 1998-03-13 | ||
JP10-63253 | 1998-03-13 | ||
JP6325298A JPH11259016A (en) | 1998-03-13 | 1998-03-13 | Manufacture of array substrate for display device |
JP10-063252 | 1998-03-13 | ||
JP6325398A JPH11258633A (en) | 1998-03-13 | 1998-03-13 | Production of array substrate for display device |
JP6325198A JPH11258632A (en) | 1998-03-13 | 1998-03-13 | Array substrate for display device |
JP10-63252 | 1998-03-13 |
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US6528357B2 true US6528357B2 (en) | 2003-03-04 |
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US20020180898A1 (en) * | 2001-06-05 | 2002-12-05 | Lg. Phillips Lcd Co., Ltd. | Array substrate for liquid crystal display and method for fabricating the same |
US20030007108A1 (en) * | 2001-07-07 | 2003-01-09 | Hwang Kwang Jo | Array substrate of liquid crystal display and fabricating method thereof |
US20030164290A1 (en) * | 2002-03-01 | 2003-09-04 | Chi-Lin Chen | Method of forming an ITO layer on a heat-sensitive substrate |
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Also Published As
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US20020132385A1 (en) | 2002-09-19 |
TW565719B (en) | 2003-12-11 |
KR100320007B1 (en) | 2002-01-10 |
KR19990077818A (en) | 1999-10-25 |
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