|Publication number||US6432791 B1|
|Application number||US 09/548,061|
|Publication date||13 Aug 2002|
|Filing date||12 Apr 2000|
|Priority date||14 Apr 1999|
|Publication number||09548061, 548061, US 6432791 B1, US 6432791B1, US-B1-6432791, US6432791 B1, US6432791B1|
|Inventors||Louis N. Hutter, Peter S. Ying, Imran Khan|
|Original Assignee||Texas Instruments Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (21), Referenced by (26), Classifications (10), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claim benefit of Ser. No. 60/129,179 Apr. 14, 1999.
The following patent applications disclose related subject matter: Ser. Nos. 09/276,680, filed Mar. 25, 1999 (TI-27203). These applications have a common assignee with the present application.
The invention relates to semiconductor integrated circuits, and more particularly to mixed signal integrated circuits and fabrication methods.
Mixed signal integrated circuits (which contain both analog and digital devices) typically include CMOS and bipolar transistors plus capacitors and resistors. Such integrated circuits compromise performance of the various devices in order to reduce process complexity. However, circuits such as 12-bit analog-to-digital converters require precision capacitors with minimal capacitance dependence upon applied voltage. But known mixed signal processes do not provide precision capacitors without undue complexity.
The invention provides a precision capacitor in a mixed signal process by use of a single polysilicon layer for both MOS gates and capacitor plates but with diffusive doping in the capacitor plates portion and implant doping in the polysilicon gates portion.
This has the advantages of high doping to limit variation of capacitance with applied voltage to the capacitors and avoidance of diffusive doping affecting MOS channel regions.
The drawings are heuristic for clarity.
FIG. 1 is a flow diagram.
FIGS. 2a-2 r are cross sectional elevation views of preferred embodiment fabrication method steps.
FIGS. 3a-3 b show difference capacitance density capacitor preferred embodiment fabrication method steps.
FIG. 4 illustrates experimental results.
The preferred embodiments provide capacitor plates and MOS gates from a single polysilicon layer with the plates doped by masked diffusion (e.g., POCl3) together with gates doped by implantation. This provides high doping to limit capacitance dependence upon applied voltage and avoids dopant diffusion into the MOS channel region. FIG. 1 summarizes possible doping permutations; the diffusive doping requires a hard mask, whereas the implants may use soft masks. Gate doping may include either an implant prior to gate formation, the self-aligned source/drain implant, or both (as illustrated in the preferred embodiment of FIGS. 2a-2 r). FIG. 1 omits the formation and doping of second capacitor plates for simplicity: the gates may be made from first or second level polysilicon with the capacitors using both levels, or there may be only one polysilicon level with the capacitors using a metal or polycide level for the other plate.
Mixed signal fabrication method
A preferred embodiment fabrication method includes the following steps as illustrated in cross-sectional elevation views by FIGS. 2a-2 r which will show fabrication of six different components (from upper left to lower right): an NPN bipolar, a low Vt NMOS, an isolated NMOS, a poly-poly capacitor, a poly resistor, and a PMOS.
(1) Begin with P type silicon substrate 200 having (100) orientation and a resistivity of 6-8 ohm-cm. Alternative wafer types would include silicon-on-insulator (SOI) and n type with the conductivity types reversed in the following. First, grow an initial silicon dioxide (“oxide”) layer of about 500 nm thickness. Next, spin on photoresist and expose and develop it to define the locations of N type buried layers. Then etch the oxide with the photoresist as etch mask, and strip the photoresist.
(2) Implant a 2×1015 atoms/cm2 dose of antimony at 60 KeV using the oxide as implant mask. Drive in the implant at 1250° C. for 30 minutes. Then strip the oxide with HF. Optionally, blanket implant a 6×1012 atoms/cm2 dose of boron (BF2) at 50 KeV to improve the isolation between adjacent N type buried layers 202.
(3) Epitaxially grow (e.g., thermal decomposition of dichlorosilane) 3.5 um thick silicon layer 204 with in-situ doping P type to a resistivity 6-8 ohm-cm. See FIG. 2a illustrating four N+ buried layers 202: one for each of: the NPN, isolated NMOS, capacitor, and PMOS. Note that the epitaxial growth causes antimony updiffusion so the buried layers extend into the epitaxial layer.
(4) Thermally grow pad oxide 206 to a thickness of 20 nm, and deposit (e.g., low pressure chemical vapor deposition) a layer of silicon nitride (“nitride”) to a thickness of 140 nm. Spin on photoresist and expose and develop it to define the locations for N wells. Etch the nitride using the photoresist as etch mask, and then implant phosphorus through the exposed pad oxide with a dose of 1×1013 atoms/cm2 at 150 KeV. This phosphorus will form the N wells. Strip the photoresist and thermally grow oxide 210 over the implanted phosphorus to a thickness of 400 nm. Note that the patterned nitride prevents oxidation at its locations.
(5) Strip the nitride (e.g., phosphoric acid). Next, implant a 6×1012 atoms/cm2 dose of boron at 50 KeV using the oxide 210 as implant mask; this phosphorus will form the P wells and will be aligned to the N wells. Drive in the phosphorus and boron implants at 1100° C. for 8 hours to form the wells: N wells 208 and P wells 212. See FIG. 2b which shows the N well diffusing down to contact an underlying N+ buried layer.
(6) Strip oxides 206 and 210 with HF. Thermally grow new pad oxide 214 to a thickness of 20 nm, and deposit nitride 216 to a thickness of 150 nm. Spin on photoresist and expose and develop it to define the locations of active areas. Etch the nitride using the photoresist as mask and strip the photoresist; see FIG. 2c.
(7) Thermally grow field oxide 218 to a thickness of 620 nm. Oxide 218 will provide isolation between transistors and isolate capacitors and resistors from the underlying substrate. See FIG. 2d.
(8) Strip nitride 216 and underlying pad oxide 214; this removal of pad oxide 214 will also remove about 20 nm of field oxide 218. Then grow dummy gate oxide 220 of thickness 20 nm. Spin on photoresist 222 and expose and develop it to define the locations of implants for NMOS threshold, punchthrough, and channel stop plus bipolar base 211; but mask off the low threshold NMOS in the upper center portion of the Figures. Then implant boron at energies and doses for NMOS threshold voltage adjustment, punchthrough suppression, and channel stop (under field oxide) of 1.5×1012 atoms/cm2 at 20 KeV, 4×1012 atoms/cm2 at 70 KeV, and 2×1012 atoms/cm2 at 180 KeV, respectively. These implants also augment the base 211 doping for the NPN bipolar; see FIG. 2e. Note that the implants could be omitted from the NPN to increase the gain.
(9) Strip photoresist 222. Then spin on photoresist 224 and expose and develop it to define the locations of implants for PMOS threshold, punchthrough, and channel stop. Then implant phosphorus at energies and doses for PMOS threshold voltage adjustment, punchthrough suppression, and channel stop (under field oxide) of 1.5×1012 atoms/cm2 at 50 KeV, 5×1012 atoms/cm2 at 150 KeV, and 2.5×1012 atoms/cm2 at 380 KeV, respectively. See FIG. 2f which shows NPN collector contact also being implanted to lower resistance but the emitter region masked due to the depth of the implant.
(10) Strip photoresist 224 and dummy gate oxide 220; this will also remove about 20 nm of field oxide 218. Next, thermally grow gate oxide 226 to a thickness of about 9 nm, and deposit by LPCVD undoped polysilicon 227 (or amorphous silicon) to a thickness of 310 nm. Note that a gate oxide thickness of 9 nm will lead to an electric field of about 4.5 MV/cm for a gate voltage of 4 volts; so this process should provide 3.3 volt operation. Then spin on photoresist 228 and expose and develop it to define the locations of implants for NMOS gates and (optionally) the lower capacitor plate. Then implant phosphorus with a dose of 3×1015 atoms/cm2 at 50 KeV. See FIG. 2g.
(11) Strip photoresist 228; then deposit (e.g., TEOS plus ozone) oxide 230 to a thickness of 200 nm. Spin on photoresist and expose and develop it to define the location of capacitor bottom plates. Next, etch oxide 230 using the photoresist as the etch mask, and strip the photoresist. Then decompose POCl3 on the patterned oxide 230 and exposed polysilicon; this generates phosphorus dopants which diffuse into the exposed polysilicon. Perform the POCl3 doping at 900° C. for 30 minutes; this essentially saturates the exposed polysilicon with phosphorus and yields a resistivity of 25 ohm/square. This also diffuses the implanted phosphorus in the portion of polysilicon 227 which will eventually form the NMOS gates. The phosphorus diffuses roughly 1 um laterally under oxide 230 diffusion mask, so layout capacitor bottom plates spaced from the MOS devices. Note that a POCl3 doping of the NMOS gate polysilicon (instead of the implant of the foregoing step) likely would lead to some phosphorus diffusion through the thin gate oxide and into the channel region. See FIG. 2h which labels the POCl3 doped portion of polysilicon 227 as N+, the implant doped NMOS gate portion as N, and the remaining undoped polysilicon as I (intrinsic).
(12) Strip oxide 230, and deposit (LPCVD) nitride 232 to a thickness of 45 nm. Next, deposit second polysilicon layer 234 to a thickness of 310 nm. Then POCl3 dope polysilicon 234; the nitride prevents phosphorus diffusion into underlying polysilicon 227. Nitride 232 will be the capacitor dielectric, and polysilicon 234 the top capacitor plates. See FIG. 2i.
(13) Spin on photoresist 236 and expose and develop it to define the location of capacitor top plates. Next, etch polysilicon 234 and nitride 232 using the photoresist as the etch mask; see FIG. 2j. The etch could be a two-main-step plasma etch with Cl2+HBr to etch the polysilicon and CHF3+CF4 to etch the nitride.
(14) Strip photoresist 236. Spin on photoresist 238 and expose and develop it to define the locations of MOS gates, capacitor bottom plates, and poly resistors. Next, etch polysilicon 227 using the photoresist as the etch mask; see FIG. 2k. The MOS gates will be about 0.6 um long and with width dependent upon desired drive current. The capacitor plates will vary in size with a capacitance of roughly 1.4 fF/um2 for the 45 nm thick nitride.
(15) Strip photoresist 238; then a short thermal oxidation will seal the sides of the poly gates and maintain the exposed gate oxide. Spin on photoresist 240 and expose and develop it to define the locations of NMOS devices except for eventual P well contacts, N well contacts in PMOS devices, and both the emitter and collector contact in the NPN bipolar. Then implant phosphorus with a dose of 6×1013 atoms/cm2 at 50 KeV; this forms the lightly doped drain implant for the NMOS and further dopes the gate plus the NPN emitter and collector contact; see FIG. 21.
(16) Strip photoresist 240. Next, deposit a 200 nm thick conformal layer of nitride (or oxide), and anisotropically etch back the layer to leave sidewall spacers 242 on the gates plus the edges of the capacitor plates and resistor poly. With oxide sidewall spacers, the anisotropic etchback will also remove some field oxide, whereas nitride sidewall spacers allow better selectivity in the etchback. Sidewall spacers 242 have a thickness of about 200 nm at the base. After the etchback, a short thermal oxidation will regrown a screen oxide on the exposed silicon. See FIG. 2m.
(17) Spin on photoresist 244 and expose and develop it to define the locations of NMOS devices except for P well contacts, N well contacts in PMOS devices, the capacitor plates, and both the emitter and the collector contact in the NPN bipolar. Then implant phosphorus and arsenic to form self-aligned NMOS source/drains and further dope the NMOS gates plus the NPN emitter and collector contact. The arsenic has a dose of 3×1015 atoms/cm2 at 120 KeV and the phosphorus has a dose of 4×1014 atoms/cm2 at 50 KeV; see FIG. 2n.
(18) Strip photoresist 244. Spin on photoresist 246 and expose and develop it to define the locations of PMOS devices except for N well contacts (which were doped N+ in the previous implants), P well contacts in NMOS devices, the poly resistor, and the extrinsic base of the NPN bipolar. Then implant boron to form self-aligned PMOS source/drains and also dope the PMOS gates plus the NPN extrinsic base and the resistor. The boron has a dose of 3×1015 atoms/cm2 at 20 KeV; see FIG. 2o.
(19) Strip photoresist 246. Deposit (LPCVD) 100 nm thick layer 250 of oxide which will mask off silicon to prevent silicidation on the poly resistor and the NPN emitter periphery. Next, anneal to activate the source/drain implants. Then spin on photoresist 252 and expose and develop it to define the locations for silicidation. Lastly, etch oxide 250 using photoresist 252 as etch mask; this etch will also strip screen oxide to expose silicon for silicidation. See FIG. 2p.
(20) Strip photoresist 252. Deposit (sputtering) a 60 nm thick layer of titanium; and react (rapid thermal anneal at 700° C.) the titanium in a nitrogen atmosphere to form titanium silicide where the titanium abutted silicon and titanium nitride for the titanium on oxide or nitride. Strip the titanium nitride (plus any unreacted titanium metal) with a HCl+H202 solution to leave the silicide as illustrated in FIG. 2q. The silicide may be annealed to convert from C49 phase to C54 phase and thereby lower the resistivity. Note that self-aligned cobalt silicide or nickel silicide could analogously be formed in place of the titanium silicide. FIG. 2q shows capacitor 270, resistor 272, PMOS gate 274, NMOS gate 276, low threshold voltage NMOS gate 278, and NPN bipolar 280 with emitter contact 282, base contact 284, and collector contact 286.
(21) Deposit 1 um thick layer of dielectric 260, such as a stack of 100 nm of conformal undoped oxide followed by 900 nm of borophosphosilicate glass (BPSG), and planarize, such as by chemical mechanical polishing (CMP) or resist etchback. Next, spin on photoresist and expose and develop it to define the locations for vias (holes, contacts) to the various devices: source/drains, gates, emitters, bases, collector contacts, resistor ends, and capacitor plates. The vias may have a diameter of about 1 um, and multiple vias may be used to contact a single device although the silicidation provides a very low lateral resistance to lessen the need for multiple vias. Then anisotropically etch the dielectric masked by the photoresist; the etch stops on silicide, so the differing via depths do not pose an overetch problem. Strip the photoresist. Lastly, deposit metal 262 to fill the vias and cover planarized dielectric 260; and etch the metal with a photoresist mask to form first level metal interconnects. Strip the photoresist; see FIG. 2r which shows. Metal 262 may be a stack of 50 nm of sputtered TiN, 500 nm of Al (copper doped), and 50 nm of TiN. Alternatively, the vias may be filled with metal (such as TiN plus W) by a blanket deposition followed by etch back and the first level interconnects may then be formed by metal deposition (e.g., TiN, Al:Cu, TiN) and patterned etching to form first level interconnects.
(22) Repeat the foregoing step (with etch stops on first level metal) to form successively higher levels of metal interconnects.
FIG. 4 shows the capacitance dependence upon applied voltage. Note that the linear voltage coefficient (the change in capacitance with respect to the change in applied voltage) in parts per million per volt is about 15-20 ppm/V as compared with coefficients on the order of 100-200 ppm/V for implanted polysilicon plates even with very high implant doses of 1.3-1.6×1016 atoms/cm2.
Two capacitor types
Step (12) deposits a single nitride capacitor dielectric. Alternatives include two or more capacitor dielectrics so that a single integrated circuit could contain both high and low voltage capacitors and both high and low capacitance density capacitors. In particular, replace step (12) with the following steps:
Strip oxide 230, and deposit (LPCVD) nitride 301 to a thickness of 55 nm. Spin on photoresist and expose and develop it to define the dielectric difference between high and low capacitance density capacitors. Plasma etch the nitride 301 using the photoresist as etch mask and stopping on N+ polysilicon 227; see FIG. 3a which shows a high capacitance density capacitor area in the lefthand portion and a low capacitance density capacitor area in the righthand portion with the etched nitride 301 and photoresist.
Strip the photoresist and deposit (LPCVD) second nitride 232 to a thickness of 45 nm; this forms 100 nm total thickness nitride at nitride 301. Next, deposit second polysilicon layer 234 to a thickness of 310 nm. Then POCl3 dope polysilicon 234; the nitride prevents phosphorus diffusion into underlying polysilicon 227. Nitride 232 will be the capacitor dielectric for high capacitance density, low voltage capacitors; nitride 232 plus nitride 301 will be the capacitor dielectric for low capacitance density, high voltage capacitors; and polysilicon 234 the top capacitor plates for both types of capacitors. See FIG. 3b. The remainder of the fabrication for high capacitance density capacitors and low capacitance density capacitors are the same as described in the foregoing.
The polysilicon resistors of the first preferred embodiment received the PMOS source/drain P+ doping. Alternative resistors on in same integrated circuit could instead (by varying photoresist exposed areas) receive the N+ doping for the NMOS source/drains, the N doping for the NMOS lightly-doped drains, the initial NMOS gate doping, or any combination of these dopings or no doping at all, and in all of the light doping cases the contact ends of the resistor could still receive the heavy source/drain doping. This allows a range of resistivities for conveniently-sized resistors, and also varying thermal resistance dependencies.
Second poly gates
Another preferred embodiment modifies the foregoing preferred embodiments by using the second polysilicon layer for the MOS gates. That is, dope (POCl3) and etch the first level polysilicon to form the bottom capacitor plates; next, do gate oxide and capacitor dielectric formations, and then dope (masked POCl3 and implant) and etch to form gates and top capacitor plates. Likewise, floating gate transistors could use the both polysilicon levels.
The preferred embodiments can be modified in various ways while retaining the feature of a masked diffusion doping of a polysilicon layer subsequently etched to form gates and capacitor plates.
For example, the N type implant prior to polysilicon etching to form NMOS gates could be omitted and the self-aligned source/drain implant relied on for gate doping. Similarly, the self-aligned silicidation could be omitted and metal contact could have an initial titanium deposition followed by reaction to form titanium silicide at metal-(poly)silicon interfaces. The masked diffusive doping could be with materials other than POCl3.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4290186 *||23 Jul 1979||22 Sep 1981||National Semiconductor Corp.||Method of making integrated semiconductor structure having an MOS and a capacitor device|
|US5045966 *||17 Sep 1990||3 Sep 1991||Micrel Semiconductor||Method for forming capacitor using FET process and structure formed by same|
|US5356826 *||5 Aug 1993||18 Oct 1994||Yamaha Corporation||Method of manufacturing semiconductor device provided with capacitor and resistor|
|US5652172 *||29 Apr 1996||29 Jul 1997||Taiwan Semiconductor Manufacturing Company Ltd.||Method for controlling the etch profile of an aperture formed through a multi-layer insulator layer|
|US5766992 *||11 Apr 1997||16 Jun 1998||Taiwan Semiconductor Manufacturing Company Ltd.||Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure|
|US5770494 *||18 Mar 1996||23 Jun 1998||Nec Corporation||Process of fabricating semiconductor device having gate structure doped through diffusion from refractory metal silicide into polysilicon|
|US5837581 *||4 Apr 1997||17 Nov 1998||Vanguard International Semiconductor Corporation||Method for forming a capacitor using a hemispherical-grain structure|
|US6084214 *||19 Feb 1999||4 Jul 2000||Conceptronic, Inc.||Reflow solder convection oven multi-port blower subassembly|
|US6091154 *||26 Jan 1998||18 Jul 2000||Fujitsu Limited||Semiconductor device with self-aligned contact and manufacturing method thereof|
|US6165861 *||14 Sep 1998||26 Dec 2000||Taiwan Semiconductor Manufacturing Company||Integrated circuit polysilicon resistor having a silicide extension to achieve 100% metal shielding from hydrogen intrusion|
|US6274411 *||21 Dec 1999||14 Aug 2001||Stmicroelectronics S.R.L.||Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks|
|US6284586 *||1 Nov 1999||4 Sep 2001||Lsi Logic Corporation||Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking|
|US6284592 *||5 Apr 2000||4 Sep 2001||Hyundai Electronics Industries Co., Ltd.||Method for fabricating a semiconductor device|
|US6287911 *||2 Mar 1999||11 Sep 2001||Nec Corporation||Semiconductor device with silicide layers and fabrication method thereof|
|US6291287 *||9 Feb 1998||18 Sep 2001||Infineon Technologies Ag||Method for producing a memory cell|
|EP0053654A2 *||28 Aug 1981||16 Jun 1982||Rockwell International Corporation||High capacitance single transistor memory cell suitable for high density RAM applications|
|JP3431522A *||Title not available|
|JP40525939A *||Title not available|
|JP40623235A *||Title not available|
|JP40623697A *||Title not available|
|WO1990005993A1 *||21 Nov 1988||31 May 1990||Micron Technology, Inc.||High performance sub-micron p-channel transistor with germanium implant|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6979624 *||15 Oct 2003||27 Dec 2005||Intersil Americas Inc.||Reduced mask count buried layer process|
|US7067414||27 Mar 2000||27 Jun 2006||Micron Technology, Inc.||Low k interlevel dielectric layer fabrication methods|
|US7105060 *||13 Aug 2004||12 Sep 2006||Tokyo Electron Limited||Method of forming an oxidation-resistant TiSiN film|
|US7208805 *||12 Sep 2001||24 Apr 2007||Micron Technology, Inc.||Structures comprising a layer free of nitrogen between silicon nitride and photoresist|
|US7592216 *||27 May 2008||22 Sep 2009||Fujitsu Microelectronics Limited||Fabrication process of a semiconductor device having a capacitor|
|US7804115||7 Jul 2006||28 Sep 2010||Micron Technology, Inc.||Semiconductor constructions having antireflective portions|
|US7825443||29 Aug 2005||2 Nov 2010||Micron Technology, Inc.||Semiconductor constructions|
|US8039355 *||7 Dec 2009||18 Oct 2011||Dongbu Hitek Co., Ltd.||Method for fabricating PIP capacitor|
|US8138040 *||3 Sep 2010||20 Mar 2012||Semiconductor Components Industries, Llc||Method of manufacturing semiconductor device|
|US9704647 *||7 Apr 2015||11 Jul 2017||Nxp B.V.||Integrated transformer|
|US9786657 *||4 Apr 2016||10 Oct 2017||Globalfoundries Inc.||Semiconductor structure including a transistor including a gate electrode region provided in a substrate and method for the formation thereof|
|US20020047142 *||12 Sep 2001||25 Apr 2002||Deboer Scott Jeffrey||Structures comprising silicon nitride|
|US20020098684 *||19 Mar 2002||25 Jul 2002||Weimin Li||Low k interlevel dielectric layer fabrication methods|
|US20020151160 *||30 May 2002||17 Oct 2002||Deboer Scott Jeffrey||Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride|
|US20020151191 *||30 May 2002||17 Oct 2002||Micron Technology, Inc.||Semiconductor processing methods of transferring patterns from patterned Photoresists to materials, and structures comprising silicon nitride|
|US20020187628 *||25 Jul 2002||12 Dec 2002||Weimin Li||Low k interlevel dielectric layer fabrication methods|
|US20040171229 *||15 Oct 2003||2 Sep 2004||Beasom James D.||Reduced mask count buried layer process|
|US20040180537 *||19 Mar 2004||16 Sep 2004||Micron Technology, Inc.||Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks|
|US20050020003 *||31 Oct 2003||27 Jan 2005||Ted Johansson||Semiconductor process and integrated circuit|
|US20050020065 *||13 Aug 2004||27 Jan 2005||Tokyo Electron Limited||Method of forming an oxidation-resistant TiSiN film|
|US20090098696 *||27 May 2008||16 Apr 2009||Fujitsu Limited||Fabrication Process of a Semiconductor Device Having a Capacitor|
|US20100163947 *||7 Dec 2009||1 Jul 2010||Lee Jong-Ho||Method for fabricating pip capacitor|
|US20110097860 *||3 Sep 2010||28 Apr 2011||Sanyo Electric Co., Ltd.||Method of manufacturing semiconductor device|
|US20110168782 *||12 Jan 2010||14 Jul 2011||Nxp B.V.||Capacitance under a fringe capacitor of a radio frquency integrated circuit|
|US20150270061 *||7 Apr 2015||24 Sep 2015||Nxp B.V.||Integrated transformer|
|EP2317541A3 *||19 Oct 2010||7 May 2014||Sanyo Electric Co., Ltd.||A method of manufacturing semiconductor device|
|U.S. Classification||438/381, 438/352, 257/E27.016, 438/396, 438/253, 438/255, 438/239|
|5 Jun 2000||AS||Assignment|
Owner name: TEXAS INSTRUMENTS INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUTTER, LOUIS N.;YING, PETER S.;KHAN, IMRAN;REEL/FRAME:010888/0871
Effective date: 20000501
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