US6356122B2 - Clock synthesizer with programmable input-output phase relationship - Google Patents
Clock synthesizer with programmable input-output phase relationship Download PDFInfo
- Publication number
- US6356122B2 US6356122B2 US09/366,897 US36689799A US6356122B2 US 6356122 B2 US6356122 B2 US 6356122B2 US 36689799 A US36689799 A US 36689799A US 6356122 B2 US6356122 B2 US 6356122B2
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- United States
- Prior art keywords
- output
- input
- feedback
- clock
- oscillator
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/366,897 US6356122B2 (en) | 1998-08-05 | 1999-08-04 | Clock synthesizer with programmable input-output phase relationship |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US9546998P | 1998-08-05 | 1998-08-05 | |
US09/366,897 US6356122B2 (en) | 1998-08-05 | 1999-08-04 | Clock synthesizer with programmable input-output phase relationship |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020008551A1 US20020008551A1 (en) | 2002-01-24 |
US6356122B2 true US6356122B2 (en) | 2002-03-12 |
Family
ID=26790266
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/366,897 Expired - Lifetime US6356122B2 (en) | 1998-08-05 | 1999-08-04 | Clock synthesizer with programmable input-output phase relationship |
Country Status (1)
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US (1) | US6356122B2 (en) |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6515526B2 (en) * | 1999-04-26 | 2003-02-04 | Ando Electric Co., Ltd. | Phase fluctuation generation |
US6526109B1 (en) * | 1999-07-16 | 2003-02-25 | Conexant Systems, Inc. | Method and apparatus for hybrid smart center loop for clock data recovery |
US20030065962A1 (en) * | 2001-09-28 | 2003-04-03 | Lim Chee How | Global I/O timing adjustment using calibrated delay elements |
US20030169086A1 (en) * | 1999-11-18 | 2003-09-11 | Kyoengho Lee | Zero-delay buffer circuit for a spread spectrum clock system and method therefor |
US20040008065A1 (en) * | 2002-07-12 | 2004-01-15 | Dinh Bui | Signal timing adjustment circuit with external resistor |
US6775342B1 (en) * | 1998-06-22 | 2004-08-10 | Xilinx, Inc. | Digital phase shifter |
US6806750B1 (en) * | 2002-04-23 | 2004-10-19 | National Semiconductor Corporation | Method and system for clock deskewing using a continuously calibrated delay element in a phase-locked loop |
US20060055441A1 (en) * | 2004-09-10 | 2006-03-16 | Lsi Logic Corporation | Method and apparatus for calibrating a delay line |
US20060139103A1 (en) * | 2002-12-30 | 2006-06-29 | Peter Beeson | Phase locked loop |
US7242229B1 (en) | 2001-05-06 | 2007-07-10 | Altera Corporation | Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode |
US20070208831A1 (en) * | 2006-02-28 | 2007-09-06 | Chris Wunderlich | Autonomous transfer of data |
US20070213845A1 (en) * | 2006-02-28 | 2007-09-13 | Chris Wunderlich | Clock system for controlling autonomous transfer of data |
US7323917B2 (en) | 2003-09-15 | 2008-01-29 | Texas Instruments Incorporated | Method and apparatus for synthesizing a clock signal having a frequency near the frequency of a source clock signal |
US7472033B1 (en) * | 2000-06-16 | 2008-12-30 | Transmeta Corporation | Apparatus for controlling semiconductor chip characteristics |
US20090183046A1 (en) * | 2008-01-13 | 2009-07-16 | Cisco Technology, Inc., A Corporation Of California | Programmable Test Clock Generation Responsive to Clock Signal Characterization |
US7564283B1 (en) | 1998-06-22 | 2009-07-21 | Xilinx, Inc. | Automatic tap delay calibration for precise digital phase shift |
US7635997B1 (en) * | 2005-06-29 | 2009-12-22 | Xilinx, Inc. | Circuit for and method of changing a frequency in a circuit |
US7711328B1 (en) | 2005-06-29 | 2010-05-04 | Xilinx, Inc. | Method of and circuit for sampling a frequency difference in an integrated circuit |
US20100117701A1 (en) * | 2008-11-12 | 2010-05-13 | Qualcomm Incorporated | Techniques for minimizing control voltage noise due to charge pump leakage in phase locked loop circuits |
US20100219894A1 (en) * | 2009-02-27 | 2010-09-02 | Analog Bits, Inc. | Phase shift phase locked loop |
TWI422157B (en) * | 2009-12-02 | 2014-01-01 | Mstar Semiconductor Inc | Phase generating apparatus and phase generating method |
US20170048057A1 (en) * | 2015-08-13 | 2017-02-16 | Samsung Electronics Co., Ltd. | Semiconductor device and communication system including the same |
US20180159219A1 (en) * | 2016-12-05 | 2018-06-07 | Infineon Technologies Ag | Device System and Method for Radio Frequency Signal Path Calibration |
US20230017177A1 (en) * | 2020-04-15 | 2023-01-19 | Mitsubishi Electric Corporation | Delay synchronization circuit, clock transmission circuit, and clock transmission and reception circuit |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101062135B1 (en) * | 2003-12-10 | 2011-09-02 | 텔레폰악티에볼라겟엘엠에릭슨(펍) | Oscillator circuit with adjustable signal delay means |
EP1624575B1 (en) * | 2004-08-06 | 2009-01-28 | Stmicroelectronics SA | Frequency synthesiser architecture |
WO2010076599A1 (en) * | 2008-12-30 | 2010-07-08 | Tommaso Zerilli | Non-volatile configuration for serial non-volatile memory |
US10320401B2 (en) * | 2017-10-13 | 2019-06-11 | Xilinx, Inc. | Dual-path digital-to-time converter |
KR102426797B1 (en) | 2018-04-04 | 2022-07-29 | 주식회사 엘지에너지솔루션 | Negative electrode active material for lithium secondary battery, method of manufacturing the same, negative electrode for lithium secondry battery and lithium secondary battery comprising the same |
US10496127B1 (en) * | 2018-06-04 | 2019-12-03 | Linear Technology Holding Llc | Multi-chip timing alignment to a common reference signal |
US11211936B1 (en) * | 2021-01-05 | 2021-12-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Delay lock loop circuits and methods for operating same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4868513A (en) * | 1987-09-11 | 1989-09-19 | Amdahl Corporation | Phase-locked loop with redundant reference input |
US5446867A (en) * | 1992-05-29 | 1995-08-29 | Intel Corporation | Microprocessor PLL clock circuit with selectable delayed feedback |
US5687202A (en) * | 1995-04-24 | 1997-11-11 | Cyrix Corporation | Programmable phase shift clock generator |
US5926053A (en) * | 1995-12-15 | 1999-07-20 | National Semiconductor Corporation | Selectable clock generation mode |
US5933032A (en) | 1995-12-29 | 1999-08-03 | Cypress Semiconductor Corp. | Apparatus and method for generating a pulse signal |
US5936977A (en) | 1997-09-17 | 1999-08-10 | Cypress Semiconductor Corp. | Scan path circuitry including a programmable delay circuit |
US5936451A (en) * | 1994-12-29 | 1999-08-10 | Stmicroeletronics, Inc. | Delay circuit and method |
US6043717A (en) * | 1998-09-22 | 2000-03-28 | Intel Corporation | Signal synchronization and frequency synthesis system configurable as PLL or DLL |
-
1999
- 1999-08-04 US US09/366,897 patent/US6356122B2/en not_active Expired - Lifetime
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4868513A (en) * | 1987-09-11 | 1989-09-19 | Amdahl Corporation | Phase-locked loop with redundant reference input |
US5446867A (en) * | 1992-05-29 | 1995-08-29 | Intel Corporation | Microprocessor PLL clock circuit with selectable delayed feedback |
US5936451A (en) * | 1994-12-29 | 1999-08-10 | Stmicroeletronics, Inc. | Delay circuit and method |
US5687202A (en) * | 1995-04-24 | 1997-11-11 | Cyrix Corporation | Programmable phase shift clock generator |
US5926053A (en) * | 1995-12-15 | 1999-07-20 | National Semiconductor Corporation | Selectable clock generation mode |
US5933032A (en) | 1995-12-29 | 1999-08-03 | Cypress Semiconductor Corp. | Apparatus and method for generating a pulse signal |
US5936977A (en) | 1997-09-17 | 1999-08-10 | Cypress Semiconductor Corp. | Scan path circuitry including a programmable delay circuit |
US6043717A (en) * | 1998-09-22 | 2000-03-28 | Intel Corporation | Signal synchronization and frequency synthesis system configurable as PLL or DLL |
Non-Patent Citations (3)
Title |
---|
Cypress CY2308, "3.3V Zero Delay Buffer", Jun. 27, 1997, pp. 1-7. |
Cypress RoboClockII(TM) CY7B994V/CY7B993V, "High-Speed Multi-Phase PLL Clock Buffer", December 1998, p. 1. |
Cypress RoboClockII™ CY7B994V/CY7B993V, "High-Speed Multi-Phase PLL Clock Buffer", December 1998, p. 1. |
Cited By (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7564283B1 (en) | 1998-06-22 | 2009-07-21 | Xilinx, Inc. | Automatic tap delay calibration for precise digital phase shift |
US6775342B1 (en) * | 1998-06-22 | 2004-08-10 | Xilinx, Inc. | Digital phase shifter |
US6515526B2 (en) * | 1999-04-26 | 2003-02-04 | Ando Electric Co., Ltd. | Phase fluctuation generation |
US6526109B1 (en) * | 1999-07-16 | 2003-02-25 | Conexant Systems, Inc. | Method and apparatus for hybrid smart center loop for clock data recovery |
US6993109B2 (en) * | 1999-11-18 | 2006-01-31 | Anapass Inc. | Zero-delay buffer circuit for a spread spectrum clock system and method therefor |
US20030169086A1 (en) * | 1999-11-18 | 2003-09-11 | Kyoengho Lee | Zero-delay buffer circuit for a spread spectrum clock system and method therefor |
US7472033B1 (en) * | 2000-06-16 | 2008-12-30 | Transmeta Corporation | Apparatus for controlling semiconductor chip characteristics |
US7242229B1 (en) | 2001-05-06 | 2007-07-10 | Altera Corporation | Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode |
US20030065962A1 (en) * | 2001-09-28 | 2003-04-03 | Lim Chee How | Global I/O timing adjustment using calibrated delay elements |
US7197659B2 (en) * | 2001-09-28 | 2007-03-27 | Intel Corporation | Global I/O timing adjustment using calibrated delay elements |
US6806750B1 (en) * | 2002-04-23 | 2004-10-19 | National Semiconductor Corporation | Method and system for clock deskewing using a continuously calibrated delay element in a phase-locked loop |
US6882195B2 (en) | 2002-07-12 | 2005-04-19 | Ics Technologies, Inc. | Signal timing adjustment circuit with external resistor |
US20040008065A1 (en) * | 2002-07-12 | 2004-01-15 | Dinh Bui | Signal timing adjustment circuit with external resistor |
US20060139103A1 (en) * | 2002-12-30 | 2006-06-29 | Peter Beeson | Phase locked loop |
US7394322B2 (en) * | 2002-12-30 | 2008-07-01 | Nokia Corporation | Phase locked loop |
US7323917B2 (en) | 2003-09-15 | 2008-01-29 | Texas Instruments Incorporated | Method and apparatus for synthesizing a clock signal having a frequency near the frequency of a source clock signal |
US7157948B2 (en) * | 2004-09-10 | 2007-01-02 | Lsi Logic Corporation | Method and apparatus for calibrating a delay line |
US20060055441A1 (en) * | 2004-09-10 | 2006-03-16 | Lsi Logic Corporation | Method and apparatus for calibrating a delay line |
US7711328B1 (en) | 2005-06-29 | 2010-05-04 | Xilinx, Inc. | Method of and circuit for sampling a frequency difference in an integrated circuit |
US7635997B1 (en) * | 2005-06-29 | 2009-12-22 | Xilinx, Inc. | Circuit for and method of changing a frequency in a circuit |
US7464202B2 (en) * | 2006-02-28 | 2008-12-09 | Infineon Technologies Ag | Clock system for controlling autonomous transfer of data |
US20070213845A1 (en) * | 2006-02-28 | 2007-09-13 | Chris Wunderlich | Clock system for controlling autonomous transfer of data |
US20070208831A1 (en) * | 2006-02-28 | 2007-09-06 | Chris Wunderlich | Autonomous transfer of data |
US8015323B2 (en) * | 2006-02-28 | 2011-09-06 | Infineon Technologies Ag | Acquisition of data and autonomous transfer of data through communication interface in automotive system |
US7844875B2 (en) * | 2008-01-13 | 2010-11-30 | Cisco Technology, Inc. | Programmable test clock generation responsive to clock signal characterization |
US20090183046A1 (en) * | 2008-01-13 | 2009-07-16 | Cisco Technology, Inc., A Corporation Of California | Programmable Test Clock Generation Responsive to Clock Signal Characterization |
US20100117701A1 (en) * | 2008-11-12 | 2010-05-13 | Qualcomm Incorporated | Techniques for minimizing control voltage noise due to charge pump leakage in phase locked loop circuits |
US8164369B2 (en) * | 2008-11-12 | 2012-04-24 | Qualcomm Incorporated | Techniques for minimizing control voltage noise due to charge pump leakage in phase locked loop circuits |
US8866556B2 (en) * | 2009-02-27 | 2014-10-21 | Analog Bits, Inc. | Phase shift phase locked loop |
US20100219894A1 (en) * | 2009-02-27 | 2010-09-02 | Analog Bits, Inc. | Phase shift phase locked loop |
TWI422157B (en) * | 2009-12-02 | 2014-01-01 | Mstar Semiconductor Inc | Phase generating apparatus and phase generating method |
US20170048057A1 (en) * | 2015-08-13 | 2017-02-16 | Samsung Electronics Co., Ltd. | Semiconductor device and communication system including the same |
US9847870B2 (en) * | 2015-08-13 | 2017-12-19 | Samsung Electronics Co., Ltd. | Semiconductor device and communication system including the same |
TWI711277B (en) * | 2015-08-13 | 2020-11-21 | 南韓商三星電子股份有限公司 | Semiconductor device including modulator and semiconductor device including demodulator |
US20180159219A1 (en) * | 2016-12-05 | 2018-06-07 | Infineon Technologies Ag | Device System and Method for Radio Frequency Signal Path Calibration |
US10862207B2 (en) * | 2016-12-05 | 2020-12-08 | Infineon Technologies Ag | Device system and method for radio frequency signal path calibration |
US20230017177A1 (en) * | 2020-04-15 | 2023-01-19 | Mitsubishi Electric Corporation | Delay synchronization circuit, clock transmission circuit, and clock transmission and reception circuit |
US11757454B2 (en) * | 2020-04-15 | 2023-09-12 | Mitsubishi Electric Corporation | Delay synchronization circuit, clock transmission circuit, and clock transmission and reception circuit |
Also Published As
Publication number | Publication date |
---|---|
US20020008551A1 (en) | 2002-01-24 |
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AS | Assignment |
Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SEVAILA, PIYUSH;FOX, J. KEN;REEL/FRAME:010341/0427;SIGNING DATES FROM 19990823 TO 19990826 |
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Owner name: 8540098 CANADA INC., CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CYPRESS SEMICONDUCTOR CORPORATION;REEL/FRAME:031529/0019 Effective date: 20130606 |
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Owner name: PLL TECHNOLOGIES, INC., DELAWARE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:8540098 CANADA INC.;REEL/FRAME:032378/0211 Effective date: 20140307 |
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IPR | Aia trial proceeding filed before the patent and appeal board: inter partes review |
Free format text: TRIAL NO: IPR2015-00148 Opponent name: XILINX, INC. Effective date: 20141024 |
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IPRC | Trial and appeal board: inter partes review certificate |
Kind code of ref document: K1 Free format text: INTER PARTES REVIEW CERTIFICATE; TRIAL NO. IPR2015-00148, OCT. 24, 2014INTER PARTES REVIEW CERTIFICATE FOR PATENT 6,356,122, ISSUED MAR. 12, 2002, APPL. NO. 09/366,897, AUG. 4, 1999INTER PARTES REVIEW CERTIFICATE ISSUED JUL. 26, 2018 Effective date: 20180726 |