Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS6316833 B1
Publication typeGrant
Application numberUS 09/305,425
Publication date13 Nov 2001
Filing date5 May 1999
Priority date8 May 1998
Fee statusLapsed
Publication number09305425, 305425, US 6316833 B1, US 6316833B1, US-B1-6316833, US6316833 B1, US6316833B1
InventorsNoriaki Oda
Original AssigneeNec Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device with multilayer interconnection having HSQ film with implanted fluorine and fluorine preventing liner
US 6316833 B1
Abstract
A semiconductor device with a multilevel interconnection has hydrogen silsesquioxane films which are made porous by etching action of hydrogen fluoride or by ion-implantation of impurities containing fluorine, as an interlayer insulating film for filling up a space between wires. Consequently, a dielectric constant of HSQ is low and wiring capacitance of the multilayer interconnection can be reduced.
Images(6)
Previous page
Next page
Claims(9)
What is claimed is:
1. A semiconductor device with multilevel interconnection comprising a porous hydrogen silsesquioxane film having a dielectric constant less than 3.0 as an interlayer insulating film for filling a space between wires, wherein said hydrogen silsesquioxane film is made porous by ion-implantation of impurities containing fluorine, and a fluorine-resistant liner film between said wire and said hydrogen silsesquioxane film.
2. The semiconductor device with a multilevel interconnection according to claim 1, wherein said hydrogen silsesquioxane film is made porous by ion-implantation of impurities containing fluorine performed under the conditions of 10 to 30 keV and 1×1014 to 3×1015 cm−2.
3. A manufacturing method of a semiconductor device with a multilevel interconnection, comprising the steps of:
forming a fluorine-resistant liner film on wires;
forming a hydrogen silsesquioxane film on said fluorine-resistant liner film so as to fill up a space between wires;
baking the hydrogen silsesquioxane film; and
lowering the dielectric constant of said hydrogen silsesquioxane film to less than about 3.0 by performing ion-implantation of impurities containing fluorine.
4. The manufacturing method of a semiconductor device with a multilevel interconnection according to claim 3, wherein said ion-implantation of impurities containing fluorine is performed under the conditions of 10 to 30 keV and 1×1014 to 3×1015 cm−2.
5. The manufacturing method of claim 3, wherein said ion-implantation of impurities containing fluorine is performed using an energy level of 10 to 30 keV and 1×1014 to 3×1015 cm−2.
6. A semiconductor device, comprising:
a first layer wiring;
a first fluorine-resistant liner film on said first layer wiring;
a second layer wiring; and
a second fluorine-resistant liner film on said second layer wiring; and
a first porous hydrogen silsesquioxane film having a dielectric constant less than 3.0 disposed between said first fluorine-resistant liner film and said second fluorine-resistant liner film, wherein said first hydrogen silsesquioxane film is made porous by ion-implantation of impurities containing fluorine.
7. The semiconductor device of claim 6, further comprising:
a third layer wiring;
a second porous hydrogen silsesquioxane film having a dielectric constant less than 3.0 disposed between said second layer wiring and said third layer wiring, wherein said second hydrogen silsesquioxane film is made porous by ion-implantation of impurities containing fluorine; and
a third fluorine-resistant liner film between said third layer wiring and said hydrogen silsesquioxane film.
8. The semiconductor device of claim 6, wherein said ion-implantation of impurities containing fluorine is performed using an energy level of 10 to 30 keV and 1×1014 to 3×1015 cm−2.
9. The semiconductor device of claim 7, wherein said ion-implantation of impurities in said second film is performed using an energy level of 10 to 30 keV and 1×1014 to 3×1015 cm−2.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device with multilevel interconnection structure and a manufacturing method thereof, and more particularly, it relates to a semiconductor device with a multilevel interconnection whose wiring capacitance is reduced and a manufacturing method thereof.

2. Description of the Related Arts

There is observed an effective wherein as the wiring pitch becomes smaller, and the distance between adjacent wires becomes shorter, the wiring capacitance increases as a semiconductor device becomes more minute. When the wiring capacitance increases, the operational speed of a circuit becomes slower, the electric power consumed becomes larger. Therefore, for reducing wiring capacitance, it is required to use a low dielectric constant film as an interlayer insulating film.

An inorganic SOG (Spin-on-glass) such as HSQ (hydrogen silsesquioxane) has a comparatively low dielectric constant of approximately 3.0, and further, it has a thermal resistance of approximately 400° C., and therefore, it is a very useful material. However, the dielectric constant of HSQ is still high when compared with that of an organic film, and it is desired to further lower this dielectric constant of HSQ. As a method to reduce the dielectric constant of an inorganic SOG film, for example, there is a method shown in “Study of Porous Interlayer Insulating Film Material” Aoi, et al. (Proceedings of the 52th symposium on Semiconductor and Integrated Circuits Technology, pp. 62-67 (1997), in which silylation is performed by adding a silylation agent to an SOG solution, coupled with, amine processing the resulting dielectric constant is lowered to approximately 2.3, the diameter of a pore is made fine, and humidity resistance is improved.

However, in the above conventional semiconductor device with multilayer structure, solution processing is troublesome, and there is also a problem in stability of wiring capacitance.

In Japanese Patent Laid-Open Publication No. 8-250490, a method is disclosed, where a thin film of a modified HSQ thin film precursor is coated on a semiconductor substrate with a conductor. This HSQ thin film precursor comprises a hydrogen silsesquioxane resin, and preferably a modifier selected from among the group consisting of alkylalkoxysilane, alkylalkoxysilane fluoride, and a combination thereof. However, the prior art described in this publication also has a weak point because solution processing is troublesome and the stability of wiring capacitance is low.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductor device with a multilevel interconnection in which the dielectric constant of HSQ is low and wiring capacitance can be reduced, and a manufacturing method thereof.

A semiconductor device with a multilevel interconnection according to the present invention comprises a hydrogen silsesquioxane film made porous by etching with hydrogen fluoride and used as an interlayer insulating film for filling the space between wires.

Another semiconductor device with a multilevel interconnection according to the present invention comprises hydrogen silsesquioxane film made porous by ion-implantation of impurities containing fluorine used as an interlayer insulating film for filling the space between wires.

In this semiconductor device with a multilevel interconnection, it is preferable to perform said ion-implantation of impurities containing fluorine under the condition of 10 to 30 keV and 1×1014 to 3×1015 cm−2.

A manufacturing method of a semiconductor device with a multilevel interconnection according to the present invention comprises the steps of disposing a hydrogen silsesquioxane film so as to fill the space between wires, baking the hydrogen silsesquioxane film, and implanting impurities containing fluorine by ion-implantation.

In this manufacturing method of a semiconductor device with a multilevel interconnection, it is preferable to perform said ion-implantation of impurities containing fluorine under the condition of 10 to 30 keV and 1×1014 to 3×1015 cm−2.

According to the present invention, the dielectric constant of an HSQ film is low, and wiring capacitance can remarkably be reduced. Furthermore, according to the present invention, HSQ is made porous by etching of hydrogen fluoride or ion-implantation of impurities containing fluorine, and therefore the processing is extremely easy.

BRIEF DESCRIPTION OF THE INVENTION

FIG. 1 is a cross sectional view showing a semiconductor device with a multilevel interconnection according to a first embodiment of the present invention;

FIG. 2 is a cross sectional view showing 1 step of a manufacturing method;

FIG. 3 is a cross sectional view showing the next step;

FIG. 4 is a cross sectional view showing the next step;

FIG. 5 is a cross sectional view showing the next step;

FIG. 6 is a figure showing an advantageous effect of the present invention; and

FIG. 7 is a cross sectional view showing a semiconductor device with a multilevel interconnection according to a second embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will concretely be described below by referring to accompanying drawings. FIG. 1 is a cross sectional view showing a semiconductor device according to an embodiment of the present invention. On the surface of a semiconductor substrate 1, element separating areas 2 are formed, and between these element separating areas 2, a diffusion layer area 3 is provided. Then, on the substrate 1, a first interlayer insulating film 4 is formed, and on this first interlayer insulating film 4, a first layer wiring 7 comprising aluminum is patterned through a barrier metal layer 6. On the first layer wiring 7, a high fusing point metal layer 8 is formed, and to cover the first layer wiring 7 and the high fusing point metal layer 8, a plasma oxide film 9 is formed. Then, to fill the space between these wires, a porous hydrogen silsesquioxane film (hereafter, referred to simply as an HSQ film) 10 is formed. This HSQ film 10 is made porous by etching action of hydrogen fluoride or by ion-implantation of impurities containing fluorine. Then, on this HSQ film 10, a plasma SiON layer 11 and a plasma oxide film 12 are formed, and the upper surface of the plasma oxide film 12 is made flat. Accordingly, under the porous HSQ film 10, a liner film (film thickness: approximately 50 nm) comprising the plasma oxide film 9 exists, and on the porous HSQ film 10, the plasma SiON layer 11 (film thickness: approximately 50 nm) exists, and on that, a plasma oxide film 12 exists.

A second layer wiring layer with the same structure is formed on the first layer wiring layer. That is, on a plasma oxide film 12, a high fusing point metal layer 17, a second layer wiring 16 comprising aluminum, a high fusing point metal layer 19, a plasma oxide film 20, a porous HSQ film 21, a plasma SiON layer 22, and a plasma oxide film 23 are formed, and the surface of this plasma oxide film 23 is made flat.

Moreover, on the second layer wiring layer, a third layer wiring layer is formed. That is, on a plasma oxide film 23, a high fusing point metal layer 28 is formed, and on this high fusing point metal layer 28, a third layer wiring 27 comprising aluminum is patterned. Then, on this third layer wiring 27, a high fusing point metal layer 30 is formed, and a cover film 31 is formed so as to cover each space between wires.

As mentioned above, the present embodiment has 3 layer wiring structure, and an interlayer insulating film between the second layer wiring 16 and the third layer wiring 27 also has the same structure as the interlayer insulating film between the first layer wiring 7 and the second layer wiring 16.

Then, the first layer wiring 7 and the second layer wiring 16 are connected by a via hole 13, and the peripheral surface of this via hole 13 is covered by the high fusing point metal layer 17, and further, the interior of the via hole 13 is filled up by a tungsten area 15, and this tungsten area 15 electrically connects the first layer wiring 7 and the second layer wiring 16. Similarly, the second layer wiring 16 and the third layer wiring 27 are connected by a via hole 24, the high fusing point metal layer 28, and the tungsten area 26.

In a semiconductor device composed like this, HSQ films 10, 21 as interlayer insulating films existing between the first layer wiring 7 and the second layer wiring 16 and between the second layer wiring 16 and the third layer wiring 27 are formed with porous HSQ, and therefore, the dielectric constant is extremely low, and the wiring capacitance can remarkably be reduced. Consequently, the acting speed of a circuit using a multilayer wiring becomes fast. On the other hand, since this porosity of HSQ is made by etching action of HF, the manufacturing process of a semiconductor is uncomplicated, and the stability of the manufacturing process is also high.

Next, a manufacturing method of this semiconductor device with a multilevel interconnection will be described. FIG. 2 to FIG. 5 are cross sectional views showing the manufacturing method of a semiconductor device according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 2, on a semiconductor substrate 1 where an element separating area 2 and a diffusion layer area 3 are formed, a first interlayer insulating film 4 is formed, and on that, a first layer wiring 5 is formed. The first layer wiring 5 comprises, for example, titanium (film thickness: 30 nm), a barrier metal layer 6 including titanium nitride (film thickness: 50 nm), aluminum, and a high fusing point metal layer 8 including titanium such as titanium nitride in this order from the bottom. A liner film (film thickness: approximately 50 nm) comprising a plasma oxide film 9 is formed, and an HSQ film 41 (film thickness: approximately: 0.4 microns at the flat portion) is coated, and baking (approximately 400° C.) is performed.

Next, as shown in FIG. 3, ion-implantation of fluorine 42 is performed (10 to 30 keV and 1×1014 to 3×1015 cm−2). This ion-implantation is performed under the condition that the peak comes at a depth of approximately half of the film thickness of the HSQ film 41.

Next, as shown in FIG. 4, a plasma SiON 11 (film thickness: approximately 50 nm) is formed, and a plasma oxide film 12 is formed to have a film thickness of approximately 1.4 μm, and it is made flat by a chemical and mechanical polishing (CMP).

Next, as shown in FIG. 5, a via hole 13 is selectively opened, and the interior of a high fusing point metal 17 containing titanium such as titanium nitride (film thickness: approximately 500 Å) is filled up by a conductor (tungsten 15), and a second layer wiring 16 is formed. By repeating the same process, it is also possible to form wiring of more multiple layers.

In the present embodiment, by performing ion-implantation of fluorine to the HSQ film 10, Si—H connection in the HSQ film is broken, and fluorine and hydrogen are connected to be hydrogen fluoride (HF). When this is formed in the HSQ film, the HSQ film becomes porous, and the dielectric constant lowers. Then, since the HSQ film is buried in a space between adjacent wires in large amounts, the wiring capacitance is largely reduced.

By the way, it is also possible to make the HSQ film porous by etching action of hydrogen fluoride instead of ion-implantation of impurities containing fluorine.

FIG. 6 is a figure of a graph showing a difference in wiring capacitance between the present embodiment (first embodiment) and a conventional semiconductor device by comparing them, taking wiring capacitance in the vertical axis. A width and a space of wires are respectively 0.3 μm and 0.3 μm, and a film thickness of wires is approximately 0.6μm. In the first embodiment, reduction of capacity of approximately 5% is achieved when compared with the case of a conventional HSQ.

Next, another embodiment of the present invention will be described by referring to FIG. 7. In FIG. 7, the same numerals are given to the components identical with those in FIG. 1, and the detailed description thereof will be omitted. The present embodiment is different from the first embodiment shown in FIG. 1 in that plasma SiON layers 43, 44 are formed instead of plasma oxide films 9, 20 of the first layer wiring layer and the second layer wiring layer of the first embodiment. In the present embodiment, an HSQ film 10 made porous by etching action of hydrogen fluoride also exists between wires of the first layer wiring 7 and on the first layer wiring 7. Under this porous HSQ film 10, there is a liner film (film thickness: approximately 50 nm) 43 comprising a plasma SiON layer. Furthermore, on the porous HSQ film 10, there is a plasma SiON layer (film thickness: approximately 50 nm) 11, and on that, there is a plasma oxide film 12. The upper surface of this plasma oxide film 12 is made flat. Furthermore, a plasma SiON layer 44 is also used for a liner film under the porous HSQ film 21 buried between wires of the second layer wiring 16.

In this embodiment, a plasma SiON layer 43 is used as a liner film under the porous HSQ film, and therefore, there is such an effect that it is possible to prevent HF generated in the HSQ film from diffusing in the wiring direction, and that it is possible to prevent corrosion of wiring.

Moreover, it is sufficient that impurities implanted into the HSQ layer by ion-implantation contain fluorine, and for example, BF2 is also possible. In this case, it is necessary to perform implantation with accelerating energy larger than that of B ions.

In the present invention, the wiring capacitance is also remarkably reduced as shown in the second embodiment of FIG. 6.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5757079 *21 Dec 199526 May 1998International Business Machines CorporationMethod for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structure
US5818111 *21 Mar 19976 Oct 1998Texas Instruments IncorporatedLow capacitance interconnect structures in integrated circuits using a stack of low dielectric materials
US5899751 *29 Dec 19974 May 1999United Microelectronics Corp.Method for forming a planarized dielectric layer
US5939789 *16 Jul 199717 Aug 1999Hitachi, Ltd.Multilayer substrates methods for manufacturing multilayer substrates and electronic devices
US5990558 *18 Dec 199723 Nov 1999Advanced Micro Devices, Inc.Reduced cracking in gap filling dielectrics
US6008540 *28 May 199828 Dec 1999Texas Instruments IncorporatedIntegrated circuit dielectric and method
US6054769 *17 Jan 199725 Apr 2000Texas Instruments IncorporatedLow capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials
US6114186 *11 Jul 19975 Sep 2000Texas Instruments IncorporatedHydrogen silsesquioxane thin films for low capacitance structures in integrated circuits
JPH0473964A Title not available
JPH0864679A Title not available
JPH0945769A Title not available
JPH0969562A Title not available
JPH07240460A Title not available
JPH08250490A Title not available
JPH10303295A Title not available
Non-Patent Citations
Reference
1"Porous SOG for Intermetal Dielectrics" Aoi et al; Proceedings of the 52th Symposium on Semiconductor and Integrated Circuits Technology; pp. 62-67; Jun. 1997.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6498384 *5 Dec 200024 Dec 2002Advanced Micro Devices, Inc.Structure and method of semiconductor via testing
US6593251 *9 Jul 200115 Jul 2003Interuniversitair Microelektronica Centrum (Imec)Method to produce a porous oxygen-silicon layer
US6603204 *28 Feb 20015 Aug 2003International Business Machines CorporationLow-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
US6670710 *31 Jul 200130 Dec 2003Kabushiki Kaisha ToshibaSemiconductor device having multi-layered wiring
US6710450 *28 Feb 200123 Mar 2004International Business Machines CorporationInterconnect structure with precise conductor resistance and method to form same
US671674212 Nov 20026 Apr 2004International Business Machines CorporationLow-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
US6753563 *1 Nov 200122 Jun 2004Texas Instruments IncorporatedIntegrated circuit having a doped porous dielectric and method of manufacturing the same
US683136625 Mar 200314 Dec 2004International Business Machines CorporationInterconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer
US6858511 *26 Sep 200222 Feb 2005Advanced Micro Devices, Inc.Method of semiconductor via testing
US6903459 *17 May 20027 Jun 2005Matsushita Electric Industrial Co., Ltd.High frequency semiconductor device
US715375429 Aug 200226 Dec 2006Micron Technology, Inc.Forming a layer of organic polymer on a semiconductor device structure;polymerizing the organic polymer to form solid matrix; forming voids in the organic polymer, includingembedding microcapsule, exposing the semiconductor device structure to a catalyst to substantially remove the filler
US72624871 Sep 200428 Aug 2007Micron Technology, Inc.Semiconductor devices and other electronic components including porous insulators created from “void” creating materials
US72855021 Sep 200423 Oct 2007Micron Technology, Inc.Forming a layer of organic polymer on a semiconductor device structure; polymerizing the organic polymer to form solid matrix; forming voids in the organic polymer, includin gembedding microcapsule, exposing the semiconductor device structure to a catalyst to substantially remove the filler
US736840113 May 20046 May 2008Texas Instruments IncorporatedIntegrated circuit having a doped porous dielectric and method of manufacturing the same
US75542001 Sep 200430 Jun 2009Micron Technology, Inc.Semiconductor devices including porous insulators
US834998528 Jul 20098 Jan 2013Cheil Industries, Inc.Boron-containing hydrogen silsesquioxane polymer, integrated circuit device formed using the same, and associated methods
US86139792 Jan 201324 Dec 2013Cheil Industries, Inc.Boron-containing hydrogen silsesquioxane polymer, integrated circuit device formed using the same, and associated methods
US868068022 Jun 200925 Mar 2014Micron Technology, Inc.Semiconductor devices including porous insulators
USRE4194826 Aug 200823 Nov 2010Kabushiki Kaisha ToshibaSemiconductor device having multi-layered wiring
Classifications
U.S. Classification257/758, 257/760, 438/780, 257/E23.167, 257/E21.576, 257/757, 257/623, 438/697, 438/694
International ClassificationH01L21/316, H01L21/312, H01L23/532, H01L21/768, H01L23/522
Cooperative ClassificationH01L23/5329, H01L21/76825, H01L21/7682
European ClassificationH01L21/768B8D, H01L21/768B6, H01L23/532N
Legal Events
DateCodeEventDescription
10 Jan 2006FPExpired due to failure to pay maintenance fee
Effective date: 20051113
14 Nov 2005LAPSLapse for failure to pay maintenance fees
2 Jun 2005REMIMaintenance fee reminder mailed
25 Feb 2003ASAssignment
Owner name: NEC ELECTRONICS CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013774/0295
Effective date: 20021101
5 May 1999ASAssignment
Owner name: NEC CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ODA, NORIAKI;REEL/FRAME:009955/0099
Effective date: 19990428