US6294824B1 - Bonding support for leads-over-chip process - Google Patents
Bonding support for leads-over-chip process Download PDFInfo
- Publication number
- US6294824B1 US6294824B1 US09/102,702 US10270298A US6294824B1 US 6294824 B1 US6294824 B1 US 6294824B1 US 10270298 A US10270298 A US 10270298A US 6294824 B1 US6294824 B1 US 6294824B1
- Authority
- US
- United States
- Prior art keywords
- lead frame
- protective material
- frame portion
- assembly
- wafer section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
Description
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/102,702 US6294824B1 (en) | 1996-01-11 | 1998-06-22 | Bonding support for leads-over-chip process |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/584,672 US5770479A (en) | 1996-01-11 | 1996-01-11 | Bonding support for leads-over-chip process |
US09/102,702 US6294824B1 (en) | 1996-01-11 | 1998-06-22 | Bonding support for leads-over-chip process |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/584,672 Continuation US5770479A (en) | 1996-01-11 | 1996-01-11 | Bonding support for leads-over-chip process |
Publications (1)
Publication Number | Publication Date |
---|---|
US6294824B1 true US6294824B1 (en) | 2001-09-25 |
Family
ID=24338341
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/584,672 Expired - Lifetime US5770479A (en) | 1996-01-11 | 1996-01-11 | Bonding support for leads-over-chip process |
US09/102,702 Expired - Lifetime US6294824B1 (en) | 1996-01-11 | 1998-06-22 | Bonding support for leads-over-chip process |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/584,672 Expired - Lifetime US5770479A (en) | 1996-01-11 | 1996-01-11 | Bonding support for leads-over-chip process |
Country Status (1)
Country | Link |
---|---|
US (2) | US5770479A (en) |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030143780A1 (en) * | 2001-12-07 | 2003-07-31 | Kenichi Shirasaka | Method and apparatus for manufacture and inspection of semiconductor device |
US20030201525A1 (en) * | 2002-04-25 | 2003-10-30 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US20040130010A1 (en) * | 2002-10-29 | 2004-07-08 | Kuan Lee Choon | Method for fabricating semiconductor component with multi layered leadframe |
US20040245613A1 (en) * | 2003-05-14 | 2004-12-09 | Lee Kyu-Han | Chip scale package and method of fabricating the same |
US20060012055A1 (en) * | 2004-07-15 | 2006-01-19 | Foong Chee S | Semiconductor package including rivet for bonding of lead posts |
US20060250139A1 (en) * | 2001-08-10 | 2006-11-09 | Micron Technology, Inc. | Bond pad structure comprising multiple bond pads with metal overlap |
US20070158792A1 (en) * | 2006-01-06 | 2007-07-12 | Stats Chippac Ltd. | Overhang integrated circuit package system |
US20070252248A1 (en) * | 2004-08-26 | 2007-11-01 | Yip Tian S | Packaging of Intergrated Circuits to Lead Frames |
US20080230879A1 (en) * | 2005-11-01 | 2008-09-25 | Nirmal Sharma | Methods and apparatus for flip-chip-on-lead semiconductor package |
US8629539B2 (en) | 2012-01-16 | 2014-01-14 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
US20150170905A1 (en) * | 2007-07-30 | 2015-06-18 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction and related devices |
US9411025B2 (en) | 2013-04-26 | 2016-08-09 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame and a magnet |
US9494660B2 (en) | 2012-03-20 | 2016-11-15 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US10991644B2 (en) | 2019-08-22 | 2021-04-27 | Allegro Microsystems, Llc | Integrated circuit package having a low profile |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5796158A (en) * | 1995-07-31 | 1998-08-18 | Micron Technology, Inc. | Lead frame coining for semiconductor devices |
US5770479A (en) * | 1996-01-11 | 1998-06-23 | Micron Technology, Inc. | Bonding support for leads-over-chip process |
US5673845A (en) * | 1996-06-17 | 1997-10-07 | Micron Technology, Inc. | Lead penetrating clamping system |
US5890644A (en) | 1996-01-26 | 1999-04-06 | Micron Technology, Inc. | Apparatus and method of clamping semiconductor devices using sliding finger supports |
US5940686A (en) * | 1996-04-12 | 1999-08-17 | Conexant Systems, Inc. | Method for manufacturing multi-chip modules utilizing direct lead attach |
US5798570A (en) * | 1996-06-28 | 1998-08-25 | Kabushiki Kaisha Gotoh Seisakusho | Plastic molded semiconductor package with thermal dissipation means |
US5879965A (en) | 1997-06-19 | 1999-03-09 | Micron Technology, Inc. | Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication |
US6544820B2 (en) * | 1997-06-19 | 2003-04-08 | Micron Technology, Inc. | Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication |
JP2954108B2 (en) * | 1997-09-22 | 1999-09-27 | 九州日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US6384487B1 (en) | 1999-12-06 | 2002-05-07 | Micron Technology, Inc. | Bow resistant plastic semiconductor package and method of fabrication |
US6700210B1 (en) * | 1999-12-06 | 2004-03-02 | Micron Technology, Inc. | Electronic assemblies containing bow resistant semiconductor packages |
US6229202B1 (en) | 2000-01-10 | 2001-05-08 | Micron Technology, Inc. | Semiconductor package having downset leadframe for reducing package bow |
US6559537B1 (en) * | 2000-08-31 | 2003-05-06 | Micron Technology, Inc. | Ball grid array packages with thermally conductive containers |
KR100470897B1 (en) * | 2002-07-19 | 2005-03-10 | 삼성전자주식회사 | Method for manufacturing dual die package |
US20040217471A1 (en) * | 2003-02-27 | 2004-11-04 | Tessera, Inc. | Component and assemblies with ends offset downwardly |
US20060131734A1 (en) * | 2004-12-17 | 2006-06-22 | Texas Instruments Incorporated | Multi lead frame power package |
US7808088B2 (en) * | 2006-06-07 | 2010-10-05 | Texas Instruments Incorporated | Semiconductor device with improved high current performance |
JP2015095474A (en) * | 2013-11-08 | 2015-05-18 | アイシン精機株式会社 | Electronic component package |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4716124A (en) | 1984-06-04 | 1987-12-29 | General Electric Company | Tape automated manufacture of power semiconductor devices |
US4862245A (en) | 1985-04-18 | 1989-08-29 | International Business Machines Corporation | Package semiconductor chip |
US4984059A (en) | 1982-10-08 | 1991-01-08 | Fujitsu Limited | Semiconductor device and a method for fabricating the same |
US5107328A (en) | 1991-02-13 | 1992-04-21 | Micron Technology, Inc. | Packaging means for a semiconductor die having particular shelf structure |
US5140404A (en) | 1990-10-24 | 1992-08-18 | Micron Technology, Inc. | Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
US5177032A (en) | 1990-10-24 | 1993-01-05 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
US5198883A (en) | 1988-08-06 | 1993-03-30 | Kabushiki Kaisha Toshiba | Semiconductor device having an improved lead arrangement and method for manufacturing the same |
US5231755A (en) | 1991-08-20 | 1993-08-03 | Emanuel Technology, Inc. | Method of forming soluble alignment bars |
US5256598A (en) | 1992-04-15 | 1993-10-26 | Micron Technology, Inc. | Shrink accommodating lead frame |
US5286679A (en) | 1993-03-18 | 1994-02-15 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer |
US5321204A (en) | 1990-10-13 | 1994-06-14 | Gold Star Electron Co., Ltd. | Structure of charged coupled device |
US5334803A (en) | 1991-10-30 | 1994-08-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of producing the same |
US5336649A (en) | 1991-06-04 | 1994-08-09 | Micron Technology, Inc. | Removable adhesives for attachment of semiconductor dies |
US5387554A (en) | 1992-09-10 | 1995-02-07 | Vlsi Technology, Inc. | Apparatus and method for thermally coupling a heat sink to a lead frame |
US5409866A (en) | 1991-12-27 | 1995-04-25 | Fujitsu Ltd. | Process for manufacturing a semiconductor device affixed to an upper and a lower leadframe |
US5420752A (en) | 1993-08-18 | 1995-05-30 | Lsi Logic Corporation | GPT system for encapsulating an integrated circuit package |
US5770479A (en) * | 1996-01-11 | 1998-06-23 | Micron Technology, Inc. | Bonding support for leads-over-chip process |
-
1996
- 1996-01-11 US US08/584,672 patent/US5770479A/en not_active Expired - Lifetime
-
1998
- 1998-06-22 US US09/102,702 patent/US6294824B1/en not_active Expired - Lifetime
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4984059A (en) | 1982-10-08 | 1991-01-08 | Fujitsu Limited | Semiconductor device and a method for fabricating the same |
US4716124A (en) | 1984-06-04 | 1987-12-29 | General Electric Company | Tape automated manufacture of power semiconductor devices |
US4862245A (en) | 1985-04-18 | 1989-08-29 | International Business Machines Corporation | Package semiconductor chip |
US5198883A (en) | 1988-08-06 | 1993-03-30 | Kabushiki Kaisha Toshiba | Semiconductor device having an improved lead arrangement and method for manufacturing the same |
US5321204A (en) | 1990-10-13 | 1994-06-14 | Gold Star Electron Co., Ltd. | Structure of charged coupled device |
US5140404A (en) | 1990-10-24 | 1992-08-18 | Micron Technology, Inc. | Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
US5177032A (en) | 1990-10-24 | 1993-01-05 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
US5304842A (en) | 1990-10-24 | 1994-04-19 | Micron Technology, Inc. | Dissimilar adhesive die attach for semiconductor devices |
US5107328A (en) | 1991-02-13 | 1992-04-21 | Micron Technology, Inc. | Packaging means for a semiconductor die having particular shelf structure |
US5336649A (en) | 1991-06-04 | 1994-08-09 | Micron Technology, Inc. | Removable adhesives for attachment of semiconductor dies |
US5231755A (en) | 1991-08-20 | 1993-08-03 | Emanuel Technology, Inc. | Method of forming soluble alignment bars |
US5334803A (en) | 1991-10-30 | 1994-08-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of producing the same |
US5409866A (en) | 1991-12-27 | 1995-04-25 | Fujitsu Ltd. | Process for manufacturing a semiconductor device affixed to an upper and a lower leadframe |
US5256598A (en) | 1992-04-15 | 1993-10-26 | Micron Technology, Inc. | Shrink accommodating lead frame |
US5387554A (en) | 1992-09-10 | 1995-02-07 | Vlsi Technology, Inc. | Apparatus and method for thermally coupling a heat sink to a lead frame |
US5286679A (en) | 1993-03-18 | 1994-02-15 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer |
US5420752A (en) | 1993-08-18 | 1995-05-30 | Lsi Logic Corporation | GPT system for encapsulating an integrated circuit package |
US5770479A (en) * | 1996-01-11 | 1998-06-23 | Micron Technology, Inc. | Bonding support for leads-over-chip process |
Cited By (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060250139A1 (en) * | 2001-08-10 | 2006-11-09 | Micron Technology, Inc. | Bond pad structure comprising multiple bond pads with metal overlap |
US20030143780A1 (en) * | 2001-12-07 | 2003-07-31 | Kenichi Shirasaka | Method and apparatus for manufacture and inspection of semiconductor device |
US7319042B2 (en) | 2001-12-07 | 2008-01-15 | Yamaha Corporation | Method and apparatus for manufacture and inspection of semiconductor device |
US7501309B2 (en) | 2002-04-25 | 2009-03-10 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US20040169292A1 (en) * | 2002-04-25 | 2004-09-02 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US20030201525A1 (en) * | 2002-04-25 | 2003-10-30 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US7462510B2 (en) | 2002-04-25 | 2008-12-09 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US7459797B2 (en) | 2002-04-25 | 2008-12-02 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US7323767B2 (en) * | 2002-04-25 | 2008-01-29 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US20050023562A1 (en) * | 2002-04-25 | 2005-02-03 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US20060292750A1 (en) * | 2002-04-25 | 2006-12-28 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US20060237832A1 (en) * | 2002-04-25 | 2006-10-26 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US20040130010A1 (en) * | 2002-10-29 | 2004-07-08 | Kuan Lee Choon | Method for fabricating semiconductor component with multi layered leadframe |
US6972214B2 (en) | 2002-10-29 | 2005-12-06 | Micron Technology, Inc. | Method for fabricating a semiconductor package with multi layered leadframe |
US20050087847A1 (en) * | 2002-10-29 | 2005-04-28 | Kuan Lee C. | Method for fabricating a semiconductor package with multi layered leadframe |
US6835599B2 (en) * | 2002-10-29 | 2004-12-28 | Micron Technology, Inc. | Method for fabricating semiconductor component with multi layered leadframe |
US20040245613A1 (en) * | 2003-05-14 | 2004-12-09 | Lee Kyu-Han | Chip scale package and method of fabricating the same |
US20060012055A1 (en) * | 2004-07-15 | 2006-01-19 | Foong Chee S | Semiconductor package including rivet for bonding of lead posts |
WO2006019461A1 (en) * | 2004-07-15 | 2006-02-23 | Freescale Semiconductor, Inc. | Semiconductor package including rivet for bonding of lead posts |
US20070252248A1 (en) * | 2004-08-26 | 2007-11-01 | Yip Tian S | Packaging of Intergrated Circuits to Lead Frames |
US7645639B2 (en) * | 2004-08-26 | 2010-01-12 | Infineon Technologies Ag | Packaging of integrated circuits to lead frames |
US8785250B2 (en) * | 2005-11-01 | 2014-07-22 | Allegro Microsystems, Llc | Methods and apparatus for flip-chip-on-lead semiconductor package |
US20080230879A1 (en) * | 2005-11-01 | 2008-09-25 | Nirmal Sharma | Methods and apparatus for flip-chip-on-lead semiconductor package |
US20070158792A1 (en) * | 2006-01-06 | 2007-07-12 | Stats Chippac Ltd. | Overhang integrated circuit package system |
US7365417B2 (en) * | 2006-01-06 | 2008-04-29 | Stats Chippac Ltd. | Overhang integrated circuit package system |
US20150170905A1 (en) * | 2007-07-30 | 2015-06-18 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction and related devices |
US11348788B2 (en) | 2007-07-30 | 2022-05-31 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction |
US10522348B2 (en) | 2007-07-30 | 2019-12-31 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction |
US10333055B2 (en) | 2012-01-16 | 2019-06-25 | Allegro Microsystems, Llc | Methods for magnetic sensor having non-conductive die paddle |
US8629539B2 (en) | 2012-01-16 | 2014-01-14 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
US9299915B2 (en) | 2012-01-16 | 2016-03-29 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
US9620705B2 (en) | 2012-01-16 | 2017-04-11 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
US9494660B2 (en) | 2012-03-20 | 2016-11-15 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US10230006B2 (en) | 2012-03-20 | 2019-03-12 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an electromagnetic suppressor |
US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US10916665B2 (en) | 2012-03-20 | 2021-02-09 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an integrated coil |
US11444209B2 (en) | 2012-03-20 | 2022-09-13 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an integrated coil enclosed with a semiconductor die by a mold material |
US11677032B2 (en) | 2012-03-20 | 2023-06-13 | Allegro Microsystems, Llc | Sensor integrated circuit with integrated coil and element in central region of mold material |
US11828819B2 (en) | 2012-03-20 | 2023-11-28 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US11961920B2 (en) | 2012-03-20 | 2024-04-16 | Allegro Microsystems, Llc | Integrated circuit package with magnet having a channel |
US9411025B2 (en) | 2013-04-26 | 2016-08-09 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame and a magnet |
US10991644B2 (en) | 2019-08-22 | 2021-04-27 | Allegro Microsystems, Llc | Integrated circuit package having a low profile |
Also Published As
Publication number | Publication date |
---|---|
US5770479A (en) | 1998-06-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6294824B1 (en) | Bonding support for leads-over-chip process | |
JP3526788B2 (en) | Method for manufacturing semiconductor device | |
US5007576A (en) | Testable ribbon bonding method and wedge bonding tool for microcircuit device fabrication | |
JP3032964B2 (en) | Ball grid array semiconductor package and manufacturing method | |
KR100467946B1 (en) | Method for manufacturing a semiconductor chip | |
US6949470B2 (en) | Method for manufacturing circuit devices | |
US6420787B1 (en) | Semiconductor device and process of producing same | |
JPH0567647A (en) | Method of flip chip bonding of semiconductor chip | |
JP3663295B2 (en) | Chip scale package | |
US6013944A (en) | Semiconductor device in which chip electrodes are connected to terminals arranged along the periphery of an insulative board | |
US7247576B2 (en) | Method of manufacturing a semiconductor device | |
JPH053183A (en) | Semiconductor device and manufacture thereof | |
JP2001250876A (en) | Semiconductor device and its manufacturing method | |
JP3129169B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2000040676A (en) | Manufacture of semiconductor device | |
JPS62281435A (en) | Semiconductor device | |
JP3866777B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH11260990A (en) | Lead frame, resin-sealed semiconductor device and its manufacture | |
JP3827978B2 (en) | Manufacturing method of semiconductor device | |
JP3335562B2 (en) | Semiconductor chip connection bump forming method | |
JPH0350736A (en) | Manufacture of bump of semiconductor chip | |
JPH0236556A (en) | Pin grid array and mounting of semiconductor element | |
JP3055496B2 (en) | Semiconductor device mounting structure | |
JP2780375B2 (en) | Method of connecting TAB tape to semiconductor chip and bump sheet used therefor | |
JP3619752B2 (en) | Manufacturing method of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001 Effective date: 20180629 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001 Effective date: 20190731 |
|
AS | Assignment |
Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 |