US6265249B1 - Method of manufacturing thin film transistors - Google Patents
Method of manufacturing thin film transistors Download PDFInfo
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- US6265249B1 US6265249B1 US08/982,004 US98200497A US6265249B1 US 6265249 B1 US6265249 B1 US 6265249B1 US 98200497 A US98200497 A US 98200497A US 6265249 B1 US6265249 B1 US 6265249B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000010409 thin film Substances 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000010408 film Substances 0.000 claims description 133
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 93
- 239000004065 semiconductor Substances 0.000 claims description 93
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910052715 tantalum Inorganic materials 0.000 claims description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- 229910052593 corundum Inorganic materials 0.000 claims description 9
- 239000012212 insulator Substances 0.000 claims description 9
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 7
- 229910003070 TaOx Inorganic materials 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- AYTAKQFHWFYBMA-UHFFFAOYSA-N chromium dioxide Chemical compound O=[Cr]=O AYTAKQFHWFYBMA-UHFFFAOYSA-N 0.000 claims 9
- 230000005669 field effect Effects 0.000 claims 6
- 239000011819 refractory material Substances 0.000 claims 4
- 238000001465 metallisation Methods 0.000 claims 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 2
- 239000012780 transparent material Substances 0.000 claims 2
- 150000002739 metals Chemical class 0.000 claims 1
- 239000003870 refractory metal Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005286 illumination Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Definitions
- This invention relates to thin film transistors (TFT), in particular to TFT for use in active matrix liquid crystal display (LCD) devices.
- TFT thin film transistors
- LCD active matrix liquid crystal display
- each picture element has LCD device and a switch to turn the LCD device on and off.
- a matrix of pixels are placed at the cross-points of a number of rows of sequential scan signals and a number of columns of data signals.
- the pixel at that particular cross-point is activated.
- the coincident addressing of this particular pixel is accomplished by a TFT, where the scan signal may be applied to the gate of the TFT and the data signal may be impressed on the drain of the TFT and driving the corresponding LCD from the source of the TFT.
- FIG. 1 shows the cross-sectional views of the conventional amorphous silicon (a-Si) TFTs.
- a-Si amorphous silicon
- step 6 is controlled by the etching time, which is critical, and the thickness of the a-Si layer must be much thicker than that of the N+ a-Si layer. Typically, the thickness of the a-Si layer is more than 2000 Angstroms.
- Type A and type B TFTs have the same structure except that in the type A TFT, the a-Si layer protrudes beyond both edges of the gate electrode, as described by Sakamoto et al in paper, “A 10 -In.-DIAGONAL ACTIVE-MATRIX LCD ADDRESSED BY a-Si TFTs”, Proceedings of the SID , Vol.28/2, pp.145-148 (1987).
- the a-Si layer is located completely inside the shadow of of the gate electrodes.
- leakage current is observed in the type A structure, because carriers are generated in the illuminated protruded region due to photoelectric effect.
- the type A TFT cannot be used in the TFTLCD.
- the a-Si layer is totally shielded by the gate electrode.
- the a-SiN layer, i.e. the gate insulating layer, beyond the active region is attacked during the N 31 a-Si etching step (Step 3 ). Therefore, the yield of the type B structure is very poor when it is used for the TFTLCD which is a matrix array of a large number of pixels.
- an a-Si TFT which has a second layer of a-SiN has been developed as shown in FIG. 1 C.
- the fabrication process of the type C device is similar to that of type A and type B, except that the top nitride (a-SiN) layer is deposited after the deposition of the a-Si film and the top a-SiN film and the top a-SiN layer is removed from the source and drain contact regions before the deposition of the N+ a-Si layer.
- a-SiN top nitride
- the top a-SiN layer remains in the channel region of the transistor, and can be used as the etching stopper during etching of the N+ a-Si layer between the source and drain electrodes because the SiN is resistant to Si etch.
- the thickness of the a-Si layer can be made very thin, typically less than 500 Angstroms. Due to the low photon absorption in the thin a-Si layer, the a-Si layer can protrude outside both the edges of the gate electrode without incurring substantial amount of leakage current. Since the gate insulating a-SiN layer is not attacked during the formation of the active region, the type C device has a higher manufacturing yield than the type B device.
- the channel length is equal to the space between the source and the drain electrodes.
- the channel length is equal to the length of the top a-SiN and is longer than the space between the source-drain electrodes.
- the channel length of the type C device must be longer than that of type A or type B devices.
- the type C device occupies a large area, and is not suitable for high resolution displays. The detailed discussion of this effect is described in a paper by H. Katoh, “TFT-LCD Technology Achieves Color Notebook PC”, Nikkei Electronics ASIA , Apr., pp.68-71 (1992).
- An object of this invention is to construct a thin film transistor (TFT) for active matrix liquid crystal display which is free from leakage photocurrent due to backside illumination.
- TFT thin film transistor
- Another object of this invention is to construct a TFT, which is smaller than conventional TFT.
- a further object of this invention is to construct a TFT with a high yield process.
- this invention by adding an insulating layer on the gate before the a-Si layer is deposited.
- this insulating layer can be grown at a high temperature, and free from pin holes.
- the a-Si layer is shielded by the gate electrode to reduce the generation of leakage photocurrent and to reduce the geometry of the structure.
- the structure also reduces the step at the interconnection crossings to avoid breakage.
- FIGS. 1A-1E show the structures of conventional thin film transistors.
- FIGS. 2A-2D show the first four steps in fabricating the TFT structure of the present invention.
- FIGS. 2E-2G show the next three steps in fabricating the TFT structure.
- FIGS. 3A-3C show cross-sectional views of crossovers of the data line and the scan line of a LCD using the conventional TFTs and the TFT of the present invention.
- FIGS. 4A-4D show cross-sectional views of the contacts for the present invention.
- FIG. 5 shows the cross section of a prior art TFT.
- FIGS. 6A-6G show the masks for fabricating the TFT of the present invention.
- FIGS. 7A-7G show the process flow of a second embodiment of the present invention.
- FIGS. 8A-8E show the first five steps in fabricating a modified TFT structure of the present invention with double-layered gate insulator.
- FIGS. 8F-8H show the next three steps in fabricating the modified TFT.
- FIGS. 9A-9D show the cross-sectional views of the modified contacts of the present invention.
- FIGS. 2A-2G and FIGS. 8A-8H show the process flow of our invention for fabricating a high yield a-Si TFT.
- the process includes the following steps:
- a-SiN conformal silicon nitride
- a-Si conformal amorphous silicon
- N+ amorphous silicon N+ a-Si second semiconductor film 15
- the silicon nitride film 13 extends down into the channel window covering the top surface of the gate electrode leaving a first hollow above the window.
- the amorphous first semiconductor film 14 covers the silicon nitride film 13 and extends down into the first hollow towards the channel window leaving a second hollow above the first hollow.
- the heavily doped second semiconductor film 15 covers the first semiconductor film 14 extending down in the second hollow down towards the channel window leaving a third hollow above the second hollow.
- etch the N+ a-Si film 15 and the a-Si film 14 except in the active region of the TFT by standard photographic processes and dry etching.
- Both the N+ a-Si film 15 and the a-Si film 14 are patterned to form an island with a length aligned with the gate electrode 11 , but shorter than the gate electrode 11 to serve as the source region, the drain region, and the channel region for the TFT.
- the N+ a-Si film 15 and the a-Si film 14 are thus patterned into a self-aligned island above the second insulating layer 13 not aligned with the gate electrode 11 .
- This invention has the same number of mask layers as the type C TFT in FIGS. 1A-1E.
- the structure of this invention has the following advantages over the type C TFT:
- the first insulating layer 12 as compared with the type C TFT, can be deposited at high temperatures (>400° C.) and has a better quality than the a-SiN, which is deposited at a lower temperature (250° C.).
- the top a-SiN film of the type C device is deposited after the a-Si film.
- the deposition temperature of the a-Si film is about 250° C. If the deposition temperature of the top a-SiN film is higher than the deposition temperature of the a-Si film, the deposited a-Si film is degraded or damaged during the a-SiN deposition process.
- the integrity (i.e. freedom from pin holes) of the first insulating layer of this invention is better than that of the type C device, and hence the fabrication yield of the new TFT is better than the prior art.
- FIGS. 3A-3C The cross-sectional views of the crossovers of the data lines and the scan lines of the TFTLCD is shown in FIGS. 3A-3C.
- metal 1 Cr
- type A, type B and this invention have only one step T 1 for the data line (metal 2 , Al).
- the type C structure has two steps T 2 for the data line 16 C.
- the yield can be better than the type A and type B structures, because the step caused by the metal 1 step is improved by the use of multilayers, i.e., the first insulating layer 12 and the gate insulator 13 .
- the use of two step contact holes improves the yield for this invention, as shown in FIGS. 4A-4D.
- the contacts 11 A are located at the periphery of this display area, where the design rule is non-critical, e.g. larger than 100 ⁇ m ⁇ 100 ⁇ m. Therefore the design of the contact hole is not critical.
- An important advantage of this invention is that the leakage photocurrent is less than that of the type A device, and is suitable for projection television which uses the TFTLCD panel as the light valve.
- Some manufacturers use the the type C prior art device for this purpose, as shown in FIG. 5 .
- the substrate 10 C and the films 12 C, 13 C, 14 C, 15 C and 16 C correspond to substrate 10 , films 12 , 13 , 14 , 15 and 16 in FIGS. 2A-2D and FIGS. 2E-2G respectively.
- the a-Si film 14 C is located entirely inside the shadow of the gate electrode 11 C.
- the “weak point” of the type C TFT is at the edge of the source-drain electrodes, which occupies a larger area.
- the channel length of the TFT of this invention is equal to the space between the source electrode and the drain electrode, as shown in FIG. 2 G.
- the length of the channel 14 C is equal to the length of the top a-SiN layer and is longer than the space between the source and drain electrodes. Therefore, if the same design rule is used, the channel length of the type C TFT must be longer than that of the type A or type B devices. In other words, the channel length and hence the transistor size of the type C device is larger than that of this invention.
- FIGS. 6A-6G The plan views of each mask layer of this invention are shown in FIGS. 6A-6G.
- FIG. 6A shows the first mask to pattern the gate electrode 21 A and the scan line 21 B.
- FIG. 6B shows the second mask to pattern the windows 23 A, 23 B of the first insulating layer for the TFT region and the contact region, respectively.
- FIG. 6C shows the third mask to pattern the active region 24 A of the TFT and the cross-over region 24 B of the data line and the scan line.
- FIG. 6D shows the fourth mask to pattern the transparent pixel electrode 27 of indium tin oxide (ITO).
- FIG. 6E shows the fifth mask to pattern the contact windows 28 .
- FIG. 6F shows the sixth mask to pattern the source-drain 26 A of the TFT and the data line 26 B of the panel.
- ITO indium tin oxide
- the contact metal 26 C for the contact window is also defined.
- the N+ a-Si 24 A between the source and the drain electrodes is etched without photo-masking showing the seventh mask for etching the N+ a-Si 24 A between the source and the drain electrodes.
- FIGS. 8A-8E and FIGS. 8F-8H show the modified structure of the present invention, in which a double-layered gate insulator is used to reduce gate leakage.
- the process includes the following steps:
- a gate electrode 11 As shown in FIG. 8A, deposit and pattern a gate electrode 11 on a transparent substrate 10 .
- the preferred material is Ta, Al etc.
- the first insulating layer 100 is a metal oxide material such as Ta 2 O 5 or Al 2 O 3 can be formed on the surface of the electrode by sputtering of anodization, as explained in a published paper by Y. Nanno et al., “High-resolution 6-inch LCD using a-Si TFT with TaO x /SiN double insulating layer”, Displays, January 1990, pp.36-40, and another paper by Y.
- FIGS. 7A and 7B show the process flow of a second embodiment of this invention.
- the cross-over region of this embodiment has three dielectric layers.
- the manufacturing yield is higher than the first embodiment, because of the thicker layer.
- this process requires one more mask layer than the first embodiment.
- the fabrication process is as follows:
- the preferred material is Cr, Ta, Al etc. Again, if Ta or Al is used as the gate material, metal oxide such as Ta2O5 or Al2O3 (not shown in FIG. 7A can be formed on the surface of the electrode.
- a-SiN 13 , a-Si 14 and top a-SiN 17 films deposit the a-SiN 13 , a-Si 14 and top a-SiN 17 films on the substrate 10 .
- the films 13 , 14 and 17 are conformal to the layers below.
- the function of the top a-SiN film is to passivate the active channel region and serves as the etching stopper during the N+ a-Si etching.
- the usual masking is employed, as will be well understood by those skilled in the art, to protect the block during etching.
- amorphous silicon is used as the active semiconductor material, and silicon nitride is used as the insulating layers. It should be understood that other semiconductor and other insulating material can also be used for the TFT structure, and are within the scope of this invention.
Abstract
Description
Claims (30)
Priority Applications (1)
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US08/982,004 US6265249B1 (en) | 1994-03-01 | 1997-12-01 | Method of manufacturing thin film transistors |
Applications Claiming Priority (4)
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US87565194A | 1994-03-01 | 1994-03-01 | |
US43161095A | 1995-04-28 | 1995-04-28 | |
US08/810,094 US5828082A (en) | 1992-04-29 | 1997-03-03 | Thin film transistor having dual insulation layer with a window above gate electrode |
US08/982,004 US6265249B1 (en) | 1994-03-01 | 1997-12-01 | Method of manufacturing thin film transistors |
Related Parent Applications (1)
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US08/810,094 Division US5828082A (en) | 1992-04-29 | 1997-03-03 | Thin film transistor having dual insulation layer with a window above gate electrode |
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US6265249B1 true US6265249B1 (en) | 2001-07-24 |
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Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020106840A1 (en) * | 1995-02-11 | 2002-08-08 | Samsung Electronics Co. Ltd, Republic Of Korea | Thin film transistor-liquid crystal display and manufacturing method therefor |
US6545291B1 (en) * | 1999-08-31 | 2003-04-08 | E Ink Corporation | Transistor design for use in the construction of an electronically driven display |
US20030107265A1 (en) * | 2000-07-18 | 2003-06-12 | Armin Arnold | Method and brake system for controlling the braking process in a motor vehicle |
US20040262606A1 (en) * | 1994-06-09 | 2004-12-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
US20070058100A1 (en) * | 2005-09-15 | 2007-03-15 | Seiko Epson Corporation | Electro-optical device and manufacturing method thereof, electronic apparatus, and capacitor |
EP1981086A1 (en) * | 2006-01-30 | 2008-10-15 | Sharp Kabushiki Kaisha | Thin film transistor, and active matrix substrate and display device provided with such thin film transistor |
US20090057682A1 (en) * | 2006-02-24 | 2009-03-05 | Sharp Kabushiki Kaisha | Active matrix substrate, display device, television receiver, manufacturing method of active matrix substrate, forming method of gate insulating film |
US20100051916A1 (en) * | 2000-10-04 | 2010-03-04 | Cambridge University Technical Services Limited | Method for forming an electronic device in multi-layer structure |
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US20110062432A1 (en) * | 2009-09-16 | 2011-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
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US20140291683A1 (en) * | 2013-03-28 | 2014-10-02 | Samsung Display Co., Ltd. | Display panel and method of manufacturing the same |
US20150028342A1 (en) * | 2013-03-25 | 2015-01-29 | Boe Technology Group Co., Ltd. | Array substrate, manufacturing method thereof and display device |
CN105390451A (en) * | 2015-12-03 | 2016-03-09 | 深圳市华星光电技术有限公司 | Manufacture method of low-temperature polysilicon TFT substrate |
US20160240559A1 (en) * | 2015-02-17 | 2016-08-18 | Innolux Corporation | Thin film transistor substrate and display panel comprising the same |
CN105990332A (en) * | 2015-02-17 | 2016-10-05 | 群创光电股份有限公司 | Thin film transistor substrate and display panel thereof |
CN107369693A (en) * | 2017-08-04 | 2017-11-21 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display panel |
WO2019213899A1 (en) * | 2018-05-10 | 2019-11-14 | 深圳市柔宇科技有限公司 | Carrying device and vacuum drying apparatus |
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US4545112A (en) * | 1983-08-15 | 1985-10-08 | Alphasil Incorporated | Method of manufacturing thin film transistors and transistors made thereby |
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Title |
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Cited By (42)
Publication number | Priority date | Publication date | Assignee | Title |
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