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• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
  • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L29/107—Substrate region of field-effect devices
  • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
  • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
  • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
  • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
  • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
  • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
  • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
  • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
  • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
  • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
  • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
  • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
  • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L21/8232—Field-effect technology
  • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
  • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
  • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L21/8232—Field-effect technology
  • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
  • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
  • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

Definitions

• the present invention relates to semiconductor circuits and, more particularly, to semiconductor circuits in which the bodies of at least some transistors are forward-biased.
• CMOS complementary metal oxide semiconductor
• MOSFET n-Channel metal oxide semiconductor field effect transistor
• pMOS transistor p-Channel MOSFET
• Other circuit schemes have been proposed where a reverse bias is applied statically or dynamically to the body node of a MOSFET to reduce subthreshold leakage current when the MOSFET is not switching.
• the body of the pMOS transistor is connected to a voltage source larger (more positive) than the supply voltage
• the body of the nMOS transistor is connected to a voltage source smaller (more negative) than the ground potential.
• the maximum achievable performance and the minimum supply voltage allowed at a desired performance level in microprocessor and communication chips which use the above-recited schemes may be limited by 1) the intrinsic transistor drive current and 2) the controllability of device parameters offered by the process technology.
• the predominant source of device parameter fluctuations across a die may be a variation of critical dimension (CD).
• CD critical dimension
• the device may be carefully engineered to have sufficiently large margin for short-channel-effect (SCE), drain-induced-barrier-lowering (DIBL), and punch-through (PT) immunity.
• SCE short-channel-effect
• DIBL drain-induced-barrier-lowering
• PT punch-through
• a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors.
• a semiconductor circuit in another embodiment, includes first and second groups of field effect transistors.
• the circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations.
• aspects of the invention include forward biased decoupling transistors and a method of testing for leakage.
• FIG. 1 is a schematic representation of a transistor according an embodiment of the present invention.
• FIG. 2 is a schematic cross-sectional view of the transistor of FIG. 1.
• FIG. 3 is a graphical representation of drive current Ids vs. gate-to-source voltage Vgs for a forward bias, zero bias, and reverse bias in the transistor of FIG. 1.
• FIG. 4 is a schematic representation of a two-input NAND gate according to an embodiment of the invention.
• FIG. 5 is an example of a voltage source used in FIG. 4.
• FIG. 6 is a block diagram representation of circuitry including a functional unit block (FUB) that selectively receives forward biasing according to an embodiment of the present invention.
• FUB functional unit block
• FIG. 7 is a schematic representation of a circuit including voltage sources to provide, for example, the Vbbn and Vbbp voltages of FIG. 4.
• FIG. 8 is a schematic representation of a voltage source to provide, for example, the Vbbn voltage of FIG. 4.
• FIG. 9 is a block diagram representation illustrating multiple voltages applied to transistor bodies in a circuit.
• FIG. 10 is a block diagram representation illustrating multiple voltages applied to transistor bodies in a circuit.
• FIG. 11 is a schematic cross-sectional view of a portion of a semiconductor die with transistors in a twin-well arrangement according to an embodiment of the invention.
• FIG. 12 is a schematic cross-sectional view of a portion of a semiconductor die with transistors in a triple-well arrangement according to an embodiment of the invention.
• FIG. 13 is a schematic cross-sectional view of a portion of a semiconductor die showing multiple transistors in a well.
• FIG. 14 is a schematic representation of an inverter circuit according to an embodiment of the invention.
• FIG. 15 is a schematic cross-sectional view of a portion of a semiconductor die in a twin well arrangement according to an embodiment of the invention.
• FIG. 16 is a schematic cross-sectional view of a portion of a semiconductor die in a triple well arrangement according to an embodiment of the invention.
• FIG. 17 is a schematic representation of a NAND circuit according to an embodiment of the invention.
• FIG. 18 is a schematic representation of a NAND circuit according to an embodiment of the invention.
• FIG. 19 is a schematic representation of an inverter circuit according to an embodiment of the invention.
• FIG. 20 is a schematic representation of forward biased decoupling transistors.
• FIG. 21 is a schematic representation of a cross-section of a portion of a semiconductor die illustrating soft error rate reduction according to an embodiment of the invention.
• FIG. 22 is a schematic representation of a cross-section of a portion of a semiconductor die illustrating application of doping and angled implants.
• a MOSFET transistor 10 includes a source 14 at a reference voltage Vss (which may be earth ground), a drain 16 receiving a source voltage Vcc (often called VDD), and a gate 20 receiving a gate voltage Vg.
• Vss a reference voltage
• Vcc a source voltage
• Vg a gate voltage
• Gate 20 is an example of a control voltage port. If source 14 is at the reference voltage, the gate-to-source voltage Vgs equals the gate voltage Vg.
• Transistor 10 is an nMOS or n-Channel transistor in which a body or substrate 24 is of a doped P type material, and source 14 and drain 16 are each of N+ type material. A P+ type tap 26 provides a path to body 24. When a gate voltage is applied, a channel 28 provides a path between the source and drain. Transistor 10 has a threshold voltage Vt that may be defined as the voltage applied between the gate and the source below which the drain-to-source current Ids drops to very close to zero. Transistors that are used in connection with the present invention are not limited to the particular details of transistor 10, which are provided only by way of example.
• a body bias voltage Vbb is applied to body 24 through tap 26.
• Vbb could be called Vbs for voltage of body to source.
• the voltage Vbb is such that a forward bias is applied to body 24 with Vbb being higher than Vss.
• the threshold voltage without a forward body bias is Vt(NFB).
• the threshold voltage with a forward bias is Vt(FB).
• Vt(FB) is lower than Vt(NFB). With a lower threshold voltage, transistor 10 can provide a greater drive current for a given Vgs.
• the drive current is the maximum drain-to-source current Ids for a given maximum Vgs.
• transistor 10 in a forward bias condition can provide the same drive current with a lower Vgs as compared to transistor 10 not in a forward bias condition.
• transistor 10 in a forward bias condition can provide a greater drive current with the same Vgs and Vcc as compared to transistor 10 not in a forward bias condition.
• a forward bias leads to a lower threshold voltage Vt, an increase in drive current, and faster switching for a given Vgs, Vcc, and Vds.
• the amount of the forward body bias is less than or equal to the built-in potential Vpn of the pn-junction between body 24 and source 14.
• the built-in potential Vpn for silicon MOS transistors is about 0.7 volts.
• Vbb may be on the verge of full forward biasing but not be actually to full forward biasing.
• the forward body bias could be about 500 millivolts for some embodiments of the invention.
• Vbb may be changed from a forward bias to a zero bias, a substantially zero bias, or a reverse bias.
• a "substantially zero bias” includes a range from a very small forward bias to a very small reverse bias, and significant leakage may occur during substantially zero bias. Leakage is much smaller or non-existent with a reverse bias condition.
• FIG. 3 is a graph including three curves for drain-to-source current Ids as a function of gate-to-source voltage Vgs for a given drain-to-source voltage Vds.
• FIG. 3 includes Ids vs. Vgs curves for three different body bias conditions: a forward bias, zero bias, and a reverse bias.
• the threshold voltage Vt(FB) is the threshold voltage associated with the forward bias curve.
• the threshold voltage Vt(ZB) is the threshold voltage associated with the zero bias curve.
• the threshold voltage Vt(RB) is the threshold voltage associated with the reverse bias curve.
• the curves include a generally linear region and a non-linear region that approaches zero. There are three vertical lines that touch the Vgs axis.
• the threshold voltage is smaller with a forward bias than with a zero bias or a reverse bias.
• Vds could be 50-100 millivolts for some embodiments of the invention.
• the graph of FIG. 3 is provided to illustrate the general effect of body biasing on threshold voltage and is not intended to be precisely accurate. Transistor according to the present invention are not required to have curves that have the appearance of those of FIG. 3.
• FIG. 4 an example of present invention is illustrated in connection with a two-input NAND gate circuit 50 having inputs A and B at the gates of nMOS transistors 54 and 56 and at the gates of pMOS transistors 60 and 62.
• the sources of transistors 60 and 62 are connected in parallel to the output of circuit 50 on conductor 88.
• the voltage at conductor 88 is determined according to the logic of a NAND gate depending on the inputs A and B.
• a voltage Vbbn is supplied to the bodies of transistors 60 and 62 on conductors 78 (including conductors 78 A and 78 B) from a variable voltage source 68.
• the voltage level of voltage Vbbn is controlled by voltage control circuitry 72, which controls variable voltage source 68 through conductor 76.
• the voltage is referred to as Vbbn because the body in an n-well or n-type substrate is being biased.
• a voltage Vbbp is supplied to the bodies of transistors 54 and 56 on conductors 84 (including conductors 84A and 84B) from a variable voltage source 80.
• the voltage level of voltage Vbbp is controlled by voltage control circuitry 72, which controls variable voltage source 80 through conductor 82.
• Vbbp The voltage is referred to as Vbbp because the body in a p-well or p-type substrate is being biased.
• Vbbn and Vbbp are in the forward bias condition and transistors 54, 56, 60, and 62 are forward body biased.
• circuitry 50 is in the standby mode, Vbbn and Vbbp are in the zero, substantially zero, or reverse bias conditions. Zero, substantially zero, and reverse bias conditions are each examples of non-forward bias conditions during which transistors 54, 56, 60, and 62 are not forward biased.
• Circuitry 50 may include resistors or other components not illustrated in FIG. 4.
• the body bias voltage Vbbp applied on conductors 84 from variable voltage source 80 is Vss+X1.
• Vbbp is Vss-X2.
• the body bias voltage Vbbn applied on conductor 78 from variable voltage source 68 is Vcc-X3.
• Vbbn is Vcc+X4.
• Values X1, X2, X3, and X4 may each equal each other.
• some of values X1, X2, X3, and X4 may equal each other, while others of values X1, X2, X3, and X4 do not.
• values X1 and X3 may equal each other, but be different than values X2 and X4.
• Values X2 and X4 may equal each other, but be different than values X1 and X3. If X1 and X3 are greater than Vpn, there could be a significant amount of conduction between the source/drain to body junctions, which is undesirable.
• Standby mode may include submodes.
• standby mode may include a low power mode in which the transistor bodies are, for example, zero biased, reverse biased, or less forward biased and Vcc and Vg remain the same.
• Standby mode may also include a sleep mode in which Vcc and Vg could be reduced (but if too low may lead to loses of data) and the bodies are, for example, zero biased, reverse biased, or less forward biased.
• FIG. 5 illustrates details of an embodiment of variable voltage source 68, which is representative of variable voltage source 80.
• Variable voltage source 80 is analogous to variable voltage source 68.
• Isolation/voltage bias generation circuitry 90 receives a voltage control signal on conductor 76 from voltage control circuitry 72 and receives Vcc through conductor 86.
• Isolation/voltage bias generation circuitry 90 supplies Vbbn to transistors 60 and 62 through conductors 78, 78A, and 78B. Any of various well known circuits could be used to implement isolation/voltage bias generation circuitry 90.
• FIG. 4 illustrates variable voltage sources 68 and 80 as being separate, they may share some circuitry in common.
• a voltage divider circuit 130 provides voltage signals Vbbn and Vbbp on conductors 78 and 84.
• An active/standby signal is applied to conductors 76 and 82. Conductors 76 and 82 are connected to each other, although they do not have to be.
• the active/standby signal may be the clock gating signal or related to it.
• active mode is associated with an active/standby signal having, for example, a logic high voltage
• standby mode is associated with an active/standby signal having, for example, a logic low voltage.
• state control circuitry 134 in voltage control circuitry 72 causes the active/standby signal on conductors 76 and 82 to be a logic high signal.
• Inverters 136 and 138 invert the signal on conductors 76 and 82. With a logic high voltage on conductors 76 and 82, transistors T1 and T2 are turned on and transistors T3 and T4 are turned off. By properly selecting the resistances (e.g., sizes) of transistor T1 and T2, the voltage drop across transistors T1 and T2 will provide a desired forward body bias through conductors 78 and 84.
• the resistance of transistor T1 is not necessarily equal to the resistance of transistor T2.
• Vcc 1.0 volt
• Vss 0.0 volts
• the voltage drop across transistor T1 is 400 millivolts
• the voltage drop across transistor T2 is 400 millivolts
• the voltage drop across transistors T5 and T6 together is 200 millivolts.
• Vbbn would be 600 millivolts and a forward body bias of 400 millivolts (Vcc-Vbbn) is applied to transistors connected to conductor 78; and Vbbp would be 400 millivolts and a forward body bias of 400 millivolts (Vbbp-Vss) is applied to transistors connected to conductor 84.
• Vcc-Vbbn does not necessarily equal Vbbp-Vss.
• Vbbn would result in non-forward body bias, although it could result in a lesser forward body bias.
• Vcc+ were 1.3 volts and the voltage drop across transistor T3 were 200 millivolts
• Vbbn would be 1.1 volts and the transistors having bodies connected to conductor 78 would be reverse biased.
• Voltage decreasing circuitry 144 (e.g., a charge pump) provides a voltage Vss-, which is less than Vss. For example, if Vss is 0.0 volts, Vss- might be -0.3 volts.
• Transistor T4 is selected to have a resistance that provides a desired voltage drop.
• Vbbp would result in a non-forward body bias. For example, if Vss- were -0.3 volts and the voltage drop across transistor T4 were 200 millivolts, Vbbp in standby mode would be -0.1 volts and the transistors having bodies connected to conductor 84 would be reverse body biased during standby mode.
• Capacitors 150, 152, 154, and 156 which may be transistors, (as well as additional capacitors not shown) may be connected to conductors 78 and 84 to reduce the effects of noise in Vcc and Vss. To reduce leakage, transistors T1-T6 would not be forward body biased, and may be reverse body biased. Capacitors 150 and 154 might be forward biased transistors in which the body is tied to conductors 78 and 84, respectively.
• only the pMOS transistors are forward body biased.
• only the nMOS transistors are forward body biased.
• a forward body bias to one type of transistor (i.e., only pMOS or only nMOS, but particularly only pMOS transistors) as compared to not applying a forward body bias to any transistors.
• even if both pMOS and nMOS transistors are forward body biased, there may be some pMOS and some nMOS transistors that are not forward body biased.
• a reference voltage supply 174 (e.g., band gap reference) provides to a comparator 176 a precise reference Vref that is relatively independent of fluctuations in Vcc.
• a conductor 178 provides to comparator 176 a signal f(Vt), the voltage of which is a function of the Vt of a transistor 180 in a resistor divider circuit including transistors 180 and 182.
• the body of transistors 180 receives the Vbbn signal on conductor 78, while the body of resistor 182 is connected to Vcc.
• Conductor 78 is positioned between transistors 188 and 190. In active mode, with the active/standby signal having a logic high voltage on conductor 76, transistors 188 and 190 are turned on. Transistor 192 is always on (as long as Vcc is high). In one embodiment, when the voltage f(vt) is less than Vref, comparator 176 passes a clock signal CLK to the gate of pMOS transistor 186, but otherwise provides a high voltage to the gate of pMOS transistor 186. The signal Vbbn is pulled up or down or remains the same accordingly.
• the resistances of transistors 186, 188, 190, and 192 may be chosen to provide the desired voltage of Vbbn considering that transistor 192 is always on, but transistor 186 is not always on.
• Capacitors 196 and 198 (or merely capacitor 198) allow charge to build up and provide smooth voltage changes and filter noise.
• Circuit 170 provides feedback to keep the value of Vbbn constant, even as there are fluctuations in Vcc. With Vbbn constant, the threshold voltage Vt of the transistors having bodies coupled to conductor 78 are also relatively constant even with fluctuations in Vcc.
• Capacitor 196 might be forward biased pMOS transistor in which the body is tied to conductor 78.
• transistors 188 and 190 are turned off and transistor 194 is turned on.
• Voltage increasing circuitry 184 e.g., charge pump
• Vcc+ which is greater than Vcc, which provides a reverse body bias.
• the feedback mechanism of circuit 170 can be used even if no standby mode is used.
• Transistors 188, 190, and 194 are not required.
• Preferred embodiments of the invention can eliminate additional masking steps and process complexities inevitable in a multiple-threshold-voltage process, and yield an assortment of n- and p-MOSFETs with varying degrees of leakage and drive currents on the same die at low cost.
• a forward body bias provides certain benefits such as increased switching speed and improved aspect ratio (explained below). However, it also increases leakage. For some circuits, such as those in a critical path where switching speed is important, the leakage can be tolerated. However, for other circuits, switching speed is not as important and the advantage of greater switching speed and improved aspect ratio does not justify the additional leakage.
• a forward body bias is applied to a first group of transistors (e.g., in a critical switching speed path) such that the transistors have a lower Vt than those of a second and third group.
• the bodies of transistors of a second and third group are tied, for example, to their respective sources and have a higher Vt.
• the second group is in a critical speed path.
• transistors of the second group may be in circuits (e.g., certain domino circuits) for which forward body biasing is not desirable because it might degrade performance (e.g., through worse noise margin).
• the third group of transistors is not in a critical switching speed path and is not forward biased (either to reduce leakage or because the transistors are in circuits for which forward body biasing is undesirable for additional reasons). Accordingly, the transistors of the first group have different threshold voltages Vt than do the transistors of the second and third groups, without processing the transistors differently other than through perhaps a trace to a body tap.
• the transistors are in an electronic device die 204, which may be, for example, a microprocessor, memory device, or communication device, etc.
• the voltages applied to the bodies may be generated on or off the die (also called a chip). For example, circuits the same as or similar to circuitry 130 or 170 could be off the die including the transistors whose bodies are being forward biased.
• a reverse bias may be applied to the body of the transistors of the second and/or third groups or a portion of the transistors therein.
• voltages Vbbn and Vbbp resulting in a forward body bias are applied to the first group of transistors (of course, this could be changed during a standby mode).
• Voltages Vbbn and Vbbp resulting in reverse body bias are applied to at least some of the second and third group of transistors. (Some of the second and third group of transistors could have their bodies tied to the respective source or drain, in which case there could be at least three sets of threshold voltages Vt.) It is not required that some wells be reverse or zero biased.
• some groups of transistors could be less forward biased than others (e.g., first group). There may be more or less than three groups.
• the transistors are in an electronic device die 206, which may be, for example, a microprocessor, memory device, or communication device, etc.
• the voltages applied to the bodies may be generated on or off the die.
• CMOS circuits tend to have good noise margin and, therefore, tend to be able to tolerate lower Vts which may degrade noise margin to some extent.
• Some dynamic circuits, such as some domino circuits have less noise margin and, therefore, may not be suitable for forward body bias.
• voltages Vbbp and Vbbn may be in a forward body biased condition even when transistors 54, 56, 60, and 62 are temporarily in the standby mode (e.g., when there are no A and B inputs to act on). Further, voltages Vbbp and Vbbn may be in a non-forward biased condition when transistors 54, 56, 60, and 62 are temporarily in the active mode (e.g., when there are A and B inputs to act on).
• One reason for doing so is that it may be desirable to not rapidly change the body bias voltage and to just keep a forward bias condition if the transistors will rapidly change between active and standby modes.
• transistors 54, 56, 60, and 62 may be part of larger circuitry and voltage control circuitry 72 may provide body bias control to all the circuits. Accordingly, some of the transistors could be in a different mode from transistors 54, 56, 60, and 62. This is discussed in greater detail with respect to FIG. 6 as follows.
• FIG. 6 illustrates exemplary circuitry 100 that includes a FUB 110 that receives voltage control signals from voltage control circuitry 114 for numerous nMOS and nMOS circuits in a functional unit block (FUB) 110.
• Voltage control circuitry 114 determines a priori or simultaneously when FUB 110 will be in active mode and when it will be in standby mode.
• Voltage control circuitry 114 can make the a priori or simultaneous determination through various means. For example, the same circuitry that controls the applications of inputs to FUB 110 can also supply that information to voltage control circuitry 114 with advance or concurrent notice. It is possible that some transistors within FUB 110 will be in active mode, at the same time other transistors within FUB 110 will in standby mode.
• Voltage control circuitry 114 may follow certain rules in determining whether FUB 110 as a whole is in active or standby mode. For example, a rule could be that if 50 % of the transistors are to be in the active mode, the entire FUB 110 is in active mode. Other rules could be used with different percentages. Also, voltage control circuitry 114 could ignore temporary conditions in which a large percentage of transistors are in standby mode. Rather than be concerned with the percentage of transistors, the rule could be to put voltages Vbbp and Vbbn in the forward body bias condition if any of the transistors in a group are in the active mode. Voltages Vbbp and Vbbn could remain in the forward body bias condition for at least a certain number of clock cycles. The rules could be flexible to balance speed and leakage. The enable signal for clock gating on conductor 118 could be supplied in connection with voltage control circuitry 114 or independently of voltage control circuitry 114.
• each transistor be in the forward or non-forward bias conditions at the same time. That is, some transistors may be forward body biased while other transistors are non-forward body biased.
• Various embodiments of the present invention include static or quasi-static, limited and controlled forward body biasing of the body node of any/all pMOS or nMOS or both in any static/dynamic/differential MOS logic and memory circuitry implemented in bulk silicon.
• static forward bias means that the bias is constantly forward, regardless of whether the circuits are in active or standby modes.
• quadsi-static means a forward body bias is applied during only a portion of the time, while a zero bias, substantially zero bias or reverse bias is applied during some other times.
• the bias voltage can be generated and distributed from a voltage source either on-chip or off-chip. Forward-biasing of different n-wells and p-wells by different amounts can be used to generate an assortment of n- and p-MOSFETs with varying degrees of leakage and drive currents on the same die.
• FIG. 11 is a schematic cross-sectional illustration of a portion of a semiconductor die 210 having a p-type substrate 212 on which numerous transistors are formed. Only two nMOS transistors, formed in p-wells 214 and 224, and one pMOS transistor formed in an n-well 220 are illustrated. In practice there may be one or more additional n-wells and p-wells. Further, there may be many (e.g., tens, hundreds, or thousands) of transistors formed in each well. For example, in FIG.
• FIG. 13 illustrates two nMOS transistors formed in a well with a body B.
• Die 210 includes a twin-well or twin-top arrangement, where one well is p-substrate 212 and the other well is well 214, 220, or 224 depending on which transistors are being referenced.
• the transistors include a source (S), gate (G), drain (D), body (B), and body tap (BT).
• Lateral isolators (I) also called trench isolators, such as oxide isolators, separate the wells.
• a substrate tap (ST) provides a tap to the substrate.
• a voltage Vbbp is applied to the body tap of p-well 214 such that a forward body bias is provided to each transistor in p-well 214.
• the body-tap of p-well 224 is shorted to the source of at least one of the nMOS transistors in p-well 224.
• p-well 214 may have a somewhat different doping than p-substrate 212, there is a conduction path between p-well 214 and p-well 224. Accordingly, the transistors of p-well 214 and/or the transistors of p-well 224 may not have the desired body bias and resulting threshold voltage Vt, etc.
• the pn-junction between n-well 220 and p-substrate 212 provides some isolation to the transistors of n-well 220. However, additional isolation may be added if desirable.
• FIG. 12 is a schematic cross-sectional illustration of a portion of a semiconductor die 230 having a p-type substrate 212 on which numerous transistors are formed. Only two nMOS transistors and one pMOS transistor are illustrated, but there may be more wells and many transistors in each well. Some or all of the P-wells are formed in an n-isolation well or layer, such as n-isolation wells 238 and/or 240, that may be n-doped silicon with the same or different doping levels than other n-doped regions.
• an isolation structure includes an n-isolation layer and one or more lateral isolators. An isolation tap (IT) may be shorted to the body tap.
• Die 230 includes a triple well arrangement, where one well is p-substrate 212, one well is either n-isolation well 238 or 240, and the other well is well 214, 220, or 224 depending on which transistor is being referenced. It is not required that there be n-isolation wells 238 and 240 for both p-wells 214 and 224. For example, there could be isolation wells for each p-well at one bias and no-isolation well for each p-well at another bias. (An n-substrate die could be used with different corresponding changes in isolation wells.)
• the isolation wells allow spatial locality of the application of forward body bias to wells or wells and the substrate.
• the wells may be selectively chosen for different voltages of body bias including forward, reverse, and zero.
• a circuit 310 includes a pMOS transistor 316 and an nMOS transistor 318, each having a gate (G), drain (D), source (S), and body (B).
• Circuit 310 is an inverter circuit with an input at the gates and an output at the drains of transistors 316 and 318.
• Circuit 310 includes a supply voltage node 326 providing supply voltage (e.g., Vcc often called VDD) and a ground voltage node 324 providing ground voltage (e.g., Vss).
• the nodes are not necessarily connected to pads or other ports on the surface of the die.
• the supply and ground voltage nodes are not necessarily at the same voltages as supply and ground voltage pads or other ports, respectively, on the surface of the die.
• the supply and ground voltage nodes may also be the supply and ground voltage nodes, respectively, for various other circuits.
• a voltage Vbbn is the voltage of the n-type body of pMOS transistor 316.
• the body of pMOS transistor 316 is forward biased by making Vbbn ⁇ Vcc. More specifically, the body of pMOS transistor 316 is coupled to ground voltage node 324 through conductor 320.
• a voltage Vbbp is the voltage of the p-type body of nMOS transistor 318.
• the body of nMOS transistor 318 is forward biased by making Vbbp>Vss. More specifically, the body of nMOS transistor 318 is coupled to supply voltage node 326 through conductor 322.
• Transistors 316 and 318 each have a threshold voltage Vt.
• the threshold voltages of transistors 316 and 318 are lowered because of the forward body bias.
• Vcc is less than or equal to 700 millivolts, but may be higher. (If the forward body bias is greater than about 700 millivolts, there may be significant current between the source and body, which is generally undesirable.)
• a Vcc of 450 to 500 millivolts may be optimal. However, higher or lower Vcc levels may be optimal depending on the transistors or circuits involved.
• the transistors may be designed to provide the desired Vt when the forward body bias is applied.
• a cross-sectional view of a die 370 implements circuit 310 of FIG. 14.
• pMOS transistor 316 is formed in an n-well 360 and nMOS transistor 318 is formed in a p-well 362 on a p-substrate 364 of die 370.
• a body B of transistor 316 is included in n-well 360, and a body B of transistor 318 is included in p-well 362.
• Die 370 also includes an nMOS transistor 374 having a body B included in a p-well 376. (There may be additional n-wells and/or p-wells.
• FIG. 13 illustrates two of multiple nMOS transistors formed in a p-well.
• a body tap BT of n-well 360 couples the body B of pMOS transistor 316 through a conductor 320 to ground voltage node 324.
• a body tap BT of p-well 362 couples the body B of nMOS transistor 318 through a conductor 322 to supply voltage node 326.
• NMOS transistor 374 also includes a body tap BT, but the bias applied to it is not known from FIG. 14. The body bias could be forward (when Vbbp is greater than Vss), reverse (when Vbbp is less than Vss), or zero (when Vbbp is equal to Vss).
• a substrate tap (ST) provides, for example, Vcc to p-substrate 364.
• Lateral isolators such as oxide isolation, separate the wells. However, there may be a forward junction current between p-well 362 and n-well 360 through p-substrate 364. When Vcc (and the gate voltage) are relatively low, there is a relatively low drive current. The forward junction current can be significant relative to the drive current of pMOS transistor 316.
• an n-isolation well or layer 390 may be formed between p-well 362 and p-substrate 364 to isolate at least p-well 360. N-isolation well 390 will prevent forward junction current between p-well 362 and n-well 360.
• an isolation structure includes an n-isolation layer and one or more lateral isolators.
• An isolation tap (IT) couples n-isolation well 390 through a conductor to, for example, supply voltage node 326.
• the substrate tap (ST) may be couple to, for example, ground voltage node 324.
• an n-isolation well 392 may be formed between p-well 376 and p-substrate 364.
• n-well 376 may be shorted to Vss or reverse body biased.
• n-isolation layer 390 would also isolate p-well 376 from p-well 362.
• N-isolation well 392 might not be used if p-well 376 is shorted to Vss. N-isolation well 392 may be used if there are other p-wells or n-wells, not shown, having a different bias voltage.
• the n-isolation layer(s) allows different wells to be selectively biased at different voltages and thereby provide different threshold voltages to transistors in different wells, similar to that shown in FIGS. 9 and 10. Using different body biases to obtain multiple threshold voltages may be significantly less costly than using different process techniques on different transistors.
• FIG. 17 illustrates a NAND gate circuit 336 and further provides an example of how switches might be used to so that there are different body biases in active and standby modes.
• Voltage control circuitry 356 provides, for example, a logic high voltage in an active mode and a logic low voltage in a standby mode.
• the bodies of pMOS transistors 340 and 342 are coupled to ground voltage node 324 through transistor 352, such that they each have a forward body bias of Vcc minus the voltage drop across transistor 352 (which voltage drop may be quite small).
• nMOS transistors 346 and 348 are coupled to supply voltage node 326 through transistor 350, such that they each have a forward body bias of Vcc minus the voltage drop across transistor 350 (which voltage drop may be quite small).
• the bodies of pMOS transistors 340 and 342 are coupled to supply voltage node 326 through transistor 360, such that they are each biased by the voltage drop across transistor 360 (which voltage drop may be quite small).
• the bodies of nMOS transistors 346 and 348 are coupled to ground voltage node 324 through transistor 354, such that they are each biased by the voltage drop across transistor 350 (which voltage drop may be quite small).
• transistors 346, 348, 350, and 352 may be slightly forward body biased or possibly substantially zero body biased.
• FIG. 18 illustrates another NAND circuit in which Vcc is higher than would be desirable to bias the bodies of transistors 340, 342, 346, and 348 as they are in FIG. 14.
• Vcc may be well above 0.7 volts.
• Voltage reduction circuit 364 reduces the voltage between Vcc and the nMOS bodies and voltage reduction circuitry 366 reduces the voltage between the pMOS bodies and Vss.
• the voltage reduction circuit could be voltage dividers (e.g., formed of transistors) or a transistor as in FIG. 17 (although the current may be so small that there would be little voltage drop between the source and drain of a transistor).
• FIG. 19 illustrates an embodiment of the invention in which only n-wells (for pMOS transistors) are forward body biased. Depending on the embodiment, doing so may eliminate the process step of forming the n-isolation layer. However, not all of the n-wells need to be forward biased. In another embodiment, only the p-wells (for the nMOS transistors) are forward body biased. Features of FIGS. 17 and 18 can be added to the circuit of FIG. 19.
• a decoupling capacitor may be positioned between Vcc and ground of circuit 50.
• circuit 310 of FIG. 14 there are parallel capacitances from a natural pn junction diode between Vcc and the body of pMOS transistor 316 (which is at Vss), and a natural pn junction diode between Vss and the body of nMOS transistor 318 (which is at Vcc).
• the parallel capacitances are such that a lower decoupling capacitor may have to be added than if they the capacitances of the natural pn junction diodes were in series.
• forward body biased transistors 290 and 292 are used as decoupling capacitors between a first voltage level node (e.g., Vcc) and a second voltage level node (e.g., Vss).
• the voltage Vbbn may be provided from Vss or another voltage source such as a voltage bias generation circuitry.
• the capacitance increases and the size of the decoupling transistors does not have to be as large, or a greater capacitance is given for the same size as would otherwise be the case.
• the increase in capacitance between Vcc and Vbbn will also provide decoupling capacitance between Vcc and Vbbn.
• capacitors 150, 154, and 196 might be forward biased transistors.
• Soft errors are changes in the state held by a transistor or circuit node caused by ionizing radiation, such as alpha particles and cosmic rays, striking a transistor or circuit node.
• the change in state may be from a high to low or low to high voltage. It is believed that soft errors occur as a result of charge (electron hole pairs) generation by ionizing radiation.
• the generated charge interacts with the desired charge stored on nodes and circuits, hence creating an error.
• Capacitance C A ⁇ /D, where A is the area and D is the distance between the different voltages plates.
• Charge Q CV, where C is the capacitance and V is the voltage (e.g., Vcc).
• Soft errors will become more likely as the dimensions (A) of transistors decreases and/or as Vcc decreases (voltage scaling) resulting in a smaller amount of charge held by the capacitor (a node). It is believed that forward body bias reduces soft error rate (SER) by reducing the junction depletion volume (making a smaller target for a strike of ionized radiation) and increasing node storage capacitance (by decreasing the depletion region distance D). As the node storage capacitance increases, the node's critical charge is larger. It is believed, therefore, that radiation must have a higher charge to upset the charge stored on a node having forward body bias. For example, referring to FIG. 21, a nMOS transistor and a storage capacitor are used in a memory cell.
• a depletion region around the drain collects minority carriers. If the charge is collected in a smaller area, it is less likely to be struck by radiation and the cell is more likely to hold its charge if it is hit by radiation because the smaller depletion region has a larger junction capacitance.
• the forward bias junction diode (e.g., between source and body) can assist recovery of a node after a strike.
• Applying a forward body bias lowers Vt leading to a higher transistor drive current (e.g., IDSAT). If drive current is higher, it is more likely that a transistor can replenish upset charge faster making it less likely that the charge will be lost altogether.
• the weak parasitic bipolar action from the source side with forward body bias may affect existing minority carrier flow in the well which may improve SER.
• the storage capacitor is illustrated schematically as being a separate capacitor.
• the capacitance may be trench capacitance or stacked gate capacitors.
• An isolated p-well creates a natural barrier to electron hole pairs.
• Multiple/triple well technology can improve SER by pn junctions formed between the body of the device and its corresponding isolation well. The junctions create a natural barrier to minority carriers produced by ionizing radiation which has penetrated deep into the silicon (creating electron hole pairs underneath the wells).
• both pMOS and nMOS transistors will have equal protection by pn junctions and both are isolated from the substrate by a pn-junction well using a multiple/triple well technology.
• the level of forward body bias to apply to achieve good SER reduction may vary significantly depending on various factors. It may be that the level of forward body bias will be higher or lower than the level to apply for good performance or power consumption levels. With certain circuits and temperatures (e.g., 110° C.), percent increase in switching speed increases as the forward body bias increases from 0 to an inflection point or region and then begins to decreases as the forward body bias further increases past the inflection point or region. For a temperature of about 110° C., for some circuits, the inflection point or region may be about 500 millivolts forward body bias for a range of Vcc/Vt ratios of 4.5, 3.5, and 3. It may be that a forward body bias of 400 to 500 millivolts is optimal.
• SER inflection point or range varies with temperature changes.
• there may be a similar curve for SER wherein SER improves as forward body bias increases until an inflection point or region following which SER gets worse as forward body bias increases.
• the inflection point or region of forward body bias at which SER improvement is optimal may be less or greater than would be acceptable for other reasons (e.g., when the forward body bias exceeds the built-in potential also called diode turn-on voltage or the contact potential or offset voltage of around 0.6 to 0.7 volts).
• the amount of forward body bias for maximum immunity to SER may be lower or higher than optimal value for performance (e.g., 500 millivolts).
• the switching speed of a transistor or circuit is related to the ratio of supply voltage to threshold voltage or Vcc/Vt. If the ratio is too low, the switching speed may not be sufficient for a particular use and the noise margin may also be affected. However, for example, if the ratio is high by maintaining Vcc and decreasing the threshold voltage Vt, the speed may be high with well controlled active power, but the static power consumption may be unacceptably high due to high leakage at low Vt. Further, if Vcc is too high, the active power will be high and the electrical field E may be too high for the dimensions of the transistors, leading to reliability failure of the transistors. In many situations it is desirable that the both Vcc and Vt be lowered by roughly comparable amounts for aggressive voltage and technology scaling.
• Short channel effect is the phenomenon by which the gate does not have good control over the channel region. It is believed that application of a forward body bias reduces short channel effects such as Vt roll-off, IOFF roll-up (IOFF vs. L (channel length)), and DIBL. SCE may be a critical limitation in developing future technologies with low Vt transistors. SCE can be visualized by looking at the change in Vt as a function of channel length (dVt/dL). It can be costly to develop transistors meeting performance and power specifications because of degradation of SCE for advanced devices. By improving SCE, forward body bias enables transistors with low Vt and good SCE. Consequently, forward body bias helps introduce more aggressive technologies and a low cost capability to scale Vcc along with Vt.
• the aspect ratio of a MOSFET is a known measure of SCE and is defined in equation (1) below:
• Leff is an effective channel length between source and drain
• Tox is the thickness of the gate oxide between the gate and silicon
• D is the depth of the channel depletion region
• Xj is the junction depth of the source and drain.
• Smaller short-channel effects may facilitate flattening the Vt roll-off vs. L curve, decreasing DIBL, reducing target Leff, increasing IDSAT at the target Leff, improving delay for target IDSAT (Ids v. Vds curve), and reducing parameter variations by improving sensitivity of Vt to L.
• L tracks Leff, so that either L or Leff could be mentioned.
• forward body bias can reduce the effects of variations in transistor parameters (parameter variations). Forward body bias improves device parameter variation critical for developing small dimension transistors for scaled power supply voltage technologies. Forward body bias applied to transistors may improve the sensitivity of threshold voltage to transistor channel length variation (i.e., smaller rate of Vt change with L variation). Consequently, a device can tolerate more parameter variation. Examples of device parameters improved with forward body bias are: Vt, IOFF, and IDSAT. With improved parameter variation, critical dimension (CD) control may not need to be as tightly managed and it may not have to scale with technology generation or be less of a scaling factor. Relaxed CD control will allow faster deployment of next generation process technology. This relieves pressure from lithography and design to provide, for example, lower 3-sigma CD control and products that are not as CD sensitive. Furthermore, as sensitivity to parameter variation improves, a technology becomes more manufacturable and more cost effective.
• sensitivity to parameter variation improves, a technology becomes more manufacturable and more cost effective.
• the application of forward body bias may reduce jitter because with a small Vt, variations in Vcc or Vss are less of an impact on transistor drive current Id and hence delay.
• Applying a forward body bias may improve saturation drain conductance, which may be an important parameter for circuit gain.
• Applying a forward body bias may achieve results in addressing the above-described problems at lower cost that through process techniques such as doping. Further, a forward body bias may achieve results that might not be attainable through process techniques alone.
• a desired low Vt with forward body bias is selected.
• a value of forward body bias is selected. It is determined how much a drop in Vt will occur because of the forward body bias. (Alternatively, the Vt at zero bias is selected and then it is determined what forward body bias will give the desired low Vt at the forward body bias.)
• Transistors are designed and processed to have a Vt at zero bias which when lowered by forward body bias will have the desired low Vt. If forward body bias is applied to both nMOS and pMOS transistors, all nMOS transistors are designed and processed the same and all pMOS transistors are designed and processed the same.
• transistors for which forward body bias is not applied will have a slower switching speed (since they have a higher Vt) than those for which forward body bias is applied, but will have lower leakage and, therefore, lower static power consumption.
• some transistors could be reverse biased in active and/or static mode. Referring to FIGS. 9 and 10, there may be more than two Vts while the transistors are in active mode.
• the transistors should be designed and processed so that Vt with zero bias is such that each transistor has acceptable speed and active and static power consumption. This provides a process design that may be easier and less costly to achieve because the channel doping can remain high.
• the transistors have zero body bias threshold voltages (even if the transistors do not have a zero body bias in operation).
• the transistors have a forward body bias threshold voltage (VtFBB) when the transistors are forward body biased.
• the transistors have parameters including a net channel doping level (e.g., equal to DL1).
• DL1 is selected to be higher than a net channel doping level in the transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged.
• the net effect of the extra channel doping and doping of the angled implants may be a net channel doping that is about 100% (or 2 times) or more higher than that which would provide a zero bias threshold voltage. In other embodiments, the net doping may be substantially less than 100% higher (e.g., at least 25% higher, 50% higher, or 75% higher).
• the amounts of extra channel doping and angled implants may be the same for pMOS and nMOS transistors (although the charge will be different), or the amounts may be different for pMOS and nMOS transistors.
• Vt without a forward body bias is chosen such that each transistor has acceptable speed and active and static power consumption.
• the transistors could be designed and processed differently to have different Vts with zero body bias. However, this can be significantly more expensive than have all nMOS transistors designed and processed the same and all pMOS transistors designed and processed the same. There may be a need for extra masks and implants.
• SCE SCE
• One or more of these transistors are designed and processed for the transistors to have low SCE.
• a process technique that may be used is to perform ion implementation at an angle (other than perpendicular) with respect to the die surface. This is called angled implants and may effect the net amount of channel doping, which is a function of channel length.
• the implants include boron, phosphorus, and arsenic, which are implanted into the sides of the channel region around source and drain edges to improve SCE.
• the gate blocks part of the implants leading to a halo effect.
• Angle implants are also referred to as halo implants or pocket implants.
• FIG. 22 schematically illustrates general areas of extra channel doping and angle implants. Sources and drains may be added before or after the angle implants. Possible locations of source and drains are shown in dashed lines. Angled implant sections 280 and 282 are between the source and drains at the edges of the channel. Angled implants are examples of roll off compensation implants. Other roll off compensation implants may be used.
• the channel may include at least a portion of the angled implants.
• a transistor may have differently designed channel doping and/or angled implants with forward body biasing as higher channel doping was mentioned above. Other techniques in place of or addition to these may be used to achieve desired Vts and/or SCE.
• FET transistors field effect transistors
• MOSFET transistors field effect transistors
• MOSFET transistors field effect transistors
• MOSFET transistors are not MOSFET transistors, because for example they do not include an insulator (often called an oxide gate).
• a MOSFET transistor is an example of a FET transistor.
• MOSFET is sometimes used to refer to transistors which have a non-metal gate and a non-oxide insulator. (Although the term "transistor” is redundant in "FET transistor” it is used as a matter of style.) FET transistors may have a p-channel (pFET transistor) and n-channel (nFET transistor).
• Vcc may be optimal for a latch up or active power view point. There may be significant problems with latch up with a Vcc of around 2.0 volts or even less.
• Vcc may be around 500 millivolts in sub-100 nm Leff with Vcc/Vt>4 for gate overdrive. Vcc/Vt may be less than 4.
• a forward body bias of 500 millivolts may be lower than linear Vt by, for example, less than or equal to 100 millivolts to 150 millivolts and may improve the sensitivity of Vt to Leff, measured as change in Vt over change in L.
• Vt values used in sub-1V, sub 100 nm Leff, high-performance technology may be relatively small. Accordingly, a larger subthreshold swing is not expected to impact the leakage current significantly.
• Minimizing IOFF-increase with transistor channel length L variation can be increasingly critical in low-Vt technologies for achieving the largest drive current subject to 1) a maximum worst-case leakage current constraint and 2) a specific amount of L-control.
• the junction capacitance is a small fraction of the total load capacitance, then the drive current increase can translate directly into higher operating clock frequency.
• threshold voltages Vt are typically not equal across a wafer or die.
• Dynamic forward body bias feedback may be used to make the threshold voltages equal.
• the present invention may be used in low-cost, high-performance, and low-power microprocessor and communication chips in, for example, sub-0.18 micrometer technology generations.
• the invention provides a means of providing leakier, higher-performance MOSFETs on the same die that contains low-leakage, lower performance transistors through affordable process technology. This helps with the noise-immunity requirements of dynamic CMOS logic and memory circuits. Accordingly, the invention can potentially eliminate additional masking steps and process complexities inevitable in a multiple-threshold-voltage process and provide a low-cost alternative to design and manufacture of future high-performance/low-power microprocessors and communication chips.
• the present invention may be applied to all or selected nMOS/pMOS devices in (1) conventional static CMOS logic and memory circuits, (2) all varieties of dynamic or differential CMOS logic circuits (e.g. Domino, D1/D2 Domino, self-resetting (SR)-Domino, Zipper, Dual-Rail Domino, cascade voltage switch logic (CVSL), cascade differential nMOS logic (CDNL), etc.) and (3) pass transistors, resident in clock drivers/receivers, latches/flip-flops, control logic datapath logic, I/O drivers/receivers etc., each of which may be used inside or in connection with a microprocessor.
• the present invention may provide significant speed improvements compared to present technology.
• nMOS/pMOS devices may benefit from the invention: (1) transistors in static CMOS gates resident in critical paths, (2) clocked transistors in gated or untagged clock drivers, (3) clocked transistors in domino logic, and (4) transistors in a static receiver logic stage at the output of a domino gate.
• the invention may enable ultra-aggressive scaling of supply voltage in selected portions of all parts of a chip without incurring any speed penalty, and thus may provide significant reductions in active power consumption at a desired performance level set by the process technology.
• Preferred embodiments of the invention may alleviate signal swing degradation across non-complementary pass transistors. Preferred embodiments may significantly improve the device parameters control on a die (by improving the SCE/DIBL/PT characteristics of MOSFETs) which may be a key limiter to both performance enhancement and supply voltage scaling for lower power.
• IDDQ leakage testing
• the forward body bias mode may be disabled and a non-forward body bias (e.g., a reverse body bias, a zero body bias, or a less forward bias) may be applied. In that case, the threshold voltage will be higher leading to lower leakage and better testability and quality through the IDDQ testing.
• a non-forward body bias e.g., a reverse body bias, a zero body bias, or a less forward bias
• Throttling may be used by an operating system (or other software or hardware) in opportunistically establishing when to use active versus standby mode to, for example, reduce power consumption.
• the various structures of the present invention may be implemented according to any of various materials and methods known to those skilled in the art. There may be intermediate structure (such as a buffer or resistor) or signals that are between two illustrated structures. Some conductors may not be continuous as illustrated, but rather be broken up by intermediate structure. The borders of the boxes in the figures are for illustrative purposes. An actual device would not have to include such defined boundaries. The relative size of the illustrated components is not to suggest actual relative sizes.
• the figures are schematic in nature and not intended to be exact representations of, for example, cross-sections.
• various well known features of the transistors are not illustrated in some of the cross-section representations. Arrangements other than those illustrated could be used.
• an n-substrate could be used. If a p-substrate is used, a p-well is not required. If a n-substrate is used, an n-well is not required.
• different embodiments of the invention may have somewhat different details.
• the particular location and order of source (S), drain (D), body tap (BT), substrate tap (ST), and isolation tap (IT) are made for convenience of illustration and may be the same or somewhat different in different embodiments.
• connection and related terms are used in an operational sense and are not necessarily limited to a direct connection. If the specification states a component “may”, “can”, “could”, or is “preferred” to be included or have a characteristic, that particular component is not required to be included or have the characteristic.

Abstract

Description

______________________________________                                    
Transistor                                                                
        Bias       Body Bias Voltage                                      
                                Mode                                      
______________________________________                                    
nMOS    Forward    Vbbp = Vss + X1                                        
                                typically active                          
nMOS    Non-forward                                                       
                   Vbbp = Vss - X2                                        
                                typically standby                         
pMOS    Forward    Vbbn = Vcc - X3                                        
                                typically active                          
pMOS    Non-forward                                                       
                   Vbbn = Vcc + X4                                        
                                typically standby                         
______________________________________                                    

Aspect ratio=Leff/Deff=Leff/(Tox D Xj).sup.1/3             (1),

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• 1998
  • 1998-05-13 US US09/078,432 patent/US6100751A/en not_active Expired - Lifetime

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