US6057237A - Tantalum-containing barrier layers for copper - Google Patents

Tantalum-containing barrier layers for copper Download PDF

Info

Publication number
US6057237A
US6057237A US08/841,058 US84105897A US6057237A US 6057237 A US6057237 A US 6057237A US 84105897 A US84105897 A US 84105897A US 6057237 A US6057237 A US 6057237A
Authority
US
United States
Prior art keywords
tantalum
layer
copper
tantalum nitride
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/841,058
Inventor
Peijun Ding
Tony Ping-Chen Chiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to US08/841,058 priority Critical patent/US6057237A/en
Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DING, PEIJUN, CHIANG, TONY PING-CHEN
Priority to EP98303338A priority patent/EP0875924A3/en
Priority to KR1019980015253A priority patent/KR19980081819A/en
Priority to JP10158286A priority patent/JPH1174224A/en
Priority to TW087106617A priority patent/TW565625B/en
Application granted granted Critical
Publication of US6057237A publication Critical patent/US6057237A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/203—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using physical deposition, e.g. vacuum deposition, sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations

Definitions

  • This invention relates to depositing improved tantalum barrier layers for overlying copper metal lines in the manufacture of semiconductor devices. More particularly, this invention relates to the deposition of tantalum-containing barrier layers having enhanced barrier performance.
  • conductive metal contacts and lines are deposited over dielectric layers, such as silicon oxide.
  • the metal lines connect various devices to each other to form integrated circuits. Openings are made in the dielectric layer and filled with a conductive material so that contact between overlying lines and underlying devices can also be made.
  • the openings in the dielectric layer have a smaller diameter. These small diameter openings are difficult to fill, particularly using conventional sputter deposition processing.
  • FIG. 1 illustrates a conventional sputtering chamber.
  • a vacuum chamber 10 includes a target 12 of the material to be sputtered and a substrate support 14.
  • a source of DC power 13 is connected to the target 12.
  • a pair of opposed magnets 16 and 18 are mounted on top of the target 12.
  • a power source 20, such as a source of RF power, is connected to the substrate support 14.
  • a substrate 22 is mounted on the substrate support 14.
  • a gas inlet 19 permits gases to be passed into the chamber.
  • Argon is generally used as a sputtering gas.
  • the argon is ionized in the chamber and is attracted to the target 12 by the magnets 16, 18.
  • the argon atoms strike the surface of the target and sputter off particles of target material which deposit on the substrate 22. If a material such as a nitride is to be formed on the substrate, nitrogen gas is also passed into the chamber where it is ionized and reacts with sputtered metal on the substrate.
  • FIG. 2 illustrates an opening 100 partially filled with sputtered metal 110.
  • Aluminum has been widely used for the manufacture of conductive lines and contacts, but more recently copper has been tried. Copper is more conductive than aluminum, but has a similar problem as aluminum with respect to an underlying silicon substrate., i.e., at elevated temperatures the copper diffuses and reacts with other materials in the integrated circuit, and thus a barrier layer needs to be deposited between the conductive metal and the substrate.
  • Tantalum and tantalum nitride have been accepted as good barrier materials for copper to prevent the diffusion of copper into underlying layers. Tantalum can be deposited by sputtering, and, when sputtered in the presence of nitrogen, tantalum nitride is formed. Tantalum nitride is not as conductive as tantalum, and it has a tendency to peel off the underlying substrate, probably due to high stress in the tantalum nitride film. This peeling also has the disadvantage that it causes the formation of particles, which is always undesirable.
  • Tantalum is a better conductor and a better wetting agent, and thus is a good adhesive between copper and the underlying substrate.
  • tantalum alone has the disadvantage that it is not as good a barrier as tantalum nitride.
  • efforts to improve tantalum-containing barrier layers for copper have continued.
  • FIG. 1 is a schematic cross sectional view of a cnventional sputtering chamber.
  • FIG. 2 is a schematic cross sectional view of a partially sputter filled opening in accordance with the prior art.
  • FIG. 3 is an X-ray diffraction study of tantalum/tantalum nitride sandwiched films.
  • X-ray diffraction results have shown that sputter deposited tantalum nitride has a highly amorphous structure that contributes to its excellent barrier properties.
  • the amorphous silicon oxide structure causes the initial tantalum layer to be amorphous as well. This provides an initial dense tantalum layer.
  • the structure of the layer changes so that a loose, columnar structure is formed. This structure is not as good a barrier because an overlying metal layer, such as of copper, can move or diffuse along the columnar pathways to the underlying substrate.
  • a layer of amorphous tantalum nitride is deposited over the amorphous tantalum layer by adding nitrogen gas to the sputtering chamber.
  • This tantalum nitride layer prevents formation of a columnar structure in the growing tantalum film.
  • a dense amorphous barrier layer that is adherent to the substrate is deposited. If a thicker barrier layer is required, the tantalum and tantalum nitride depositions can be repeated as many times as are necessary to form the barrier layer thickness required.
  • the tantalum nitride can also be deposited as the first layer, alternating with tantalum.
  • FIG. 3 is an X-ray diffraction study of tantalum (002 crystal orientation) versus the number of alternating tantalum and tantalum nitride layers. Deposition of tantalum alone (1000 ⁇ thick) becomes less crystalline when a tantalum nitride layer is sandwiched between two tantalum layers. The total tantalum thickness is fixed at 1000 ⁇ in the study. As the layering is repeated, the composite becomes still more amorphous and dense, and very little crystallinity is to be seen.
  • Another advantage to the present process and structure is that less nitrogen is used in the composite film than when tantalum nitride is deposited alone. This reduces the high film stress characteristic of tantalum nitride. High film stress contributes to a lack of adhesion between a barrier layer and a substrate, and results in barrier layer peeling, and the consequent formation of particles. Thus in accordance with the present process, particle reduction is also obtained.
  • the opening, now lined with a dense, wholly amorphous tantalum-containing layer, can be filled with copper, also by sputtering, to form a highly conductive via that has improved barrier properties that prevent diffusion of copper into an adjacent dielectric material during subsequent processing steps.

Abstract

An improved barrier layer of tantalum to prevent diffusion of copper into a dielectric layer or silicon substrate is made by alternately sputter depositing thin amorphous tantalum layers and tantalum nitride layers. The resultant wholly amorphous tantalum-containing layer leads to a stronger barrier and prevents formation of a columnar structure in thick tantalum layers. The sputter depositions of tantalum and tantalum nitride can be repeated until the desired thickness of the barrier is obtained.

Description

This invention relates to depositing improved tantalum barrier layers for overlying copper metal lines in the manufacture of semiconductor devices. More particularly, this invention relates to the deposition of tantalum-containing barrier layers having enhanced barrier performance.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor devices, conductive metal contacts and lines are deposited over dielectric layers, such as silicon oxide. The metal lines connect various devices to each other to form integrated circuits. Openings are made in the dielectric layer and filled with a conductive material so that contact between overlying lines and underlying devices can also be made.
As devices become smaller and more devices are made in a single semiconductor (silicon) wafer, the openings in the dielectric layer have a smaller diameter. These small diameter openings are difficult to fill, particularly using conventional sputter deposition processing.
FIG. 1 illustrates a conventional sputtering chamber. A vacuum chamber 10 includes a target 12 of the material to be sputtered and a substrate support 14. A source of DC power 13 is connected to the target 12. A pair of opposed magnets 16 and 18 are mounted on top of the target 12. A power source 20, such as a source of RF power, is connected to the substrate support 14. During sputter deposition, a substrate 22 is mounted on the substrate support 14. A gas inlet 19 permits gases to be passed into the chamber. Argon is generally used as a sputtering gas. The argon is ionized in the chamber and is attracted to the target 12 by the magnets 16, 18. The argon atoms strike the surface of the target and sputter off particles of target material which deposit on the substrate 22. If a material such as a nitride is to be formed on the substrate, nitrogen gas is also passed into the chamber where it is ionized and reacts with sputtered metal on the substrate.
Since sputtered particles are sputtered from a target in numerous random directions, comparatively few of the sputtered particles impact the target in a direction perpendicular to the substrate. Most of the sputtered particles thus impact the openings in the substrate at some other angle, causing the sputtered layer to build up along the sides and top of an opening rather than on the bottom. Further, as the aspect ratio of the opening becomes higher, it is even more difficult to cover the bottom of the opening. This top and side buildup creates an overhang over the opening, as shown in FIG. 2, which further prevents particles from depositing on the bottom of the opening. FIG. 2 illustrates an opening 100 partially filled with sputtered metal 110.
Aluminum has been widely used for the manufacture of conductive lines and contacts, but more recently copper has been tried. Copper is more conductive than aluminum, but has a similar problem as aluminum with respect to an underlying silicon substrate., i.e., at elevated temperatures the copper diffuses and reacts with other materials in the integrated circuit, and thus a barrier layer needs to be deposited between the conductive metal and the substrate.
Tantalum and tantalum nitride have been accepted as good barrier materials for copper to prevent the diffusion of copper into underlying layers. Tantalum can be deposited by sputtering, and, when sputtered in the presence of nitrogen, tantalum nitride is formed. Tantalum nitride is not as conductive as tantalum, and it has a tendency to peel off the underlying substrate, probably due to high stress in the tantalum nitride film. This peeling also has the disadvantage that it causes the formation of particles, which is always undesirable.
Tantalum is a better conductor and a better wetting agent, and thus is a good adhesive between copper and the underlying substrate. However, the use of tantalum alone has the disadvantage that it is not as good a barrier as tantalum nitride. Thus efforts to improve tantalum-containing barrier layers for copper have continued.
SUMMARY OF THE INVENTION
We have found that by alternately depositing layers of tantalum and tantalum nitride, improved barrier layers for copper metal conductors are obtained.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a schematic cross sectional view of a cnventional sputtering chamber.
FIG. 2 is a schematic cross sectional view of a partially sputter filled opening in accordance with the prior art.
FIG. 3 is an X-ray diffraction study of tantalum/tantalum nitride sandwiched films.
DETAILED DESCRIPTION OF THE INVENTION
X-ray diffraction results have shown that sputter deposited tantalum nitride has a highly amorphous structure that contributes to its excellent barrier properties. We have also found that when tantalum alone is deposited into an opening in silicon oxide, the amorphous silicon oxide structure causes the initial tantalum layer to be amorphous as well. This provides an initial dense tantalum layer. However, as the tantalum layer becomes thicker, the structure of the layer changes so that a loose, columnar structure is formed. This structure is not as good a barrier because an overlying metal layer, such as of copper, can move or diffuse along the columnar pathways to the underlying substrate.
Thus in accordance with the present process, after an initial dense amorphous tantalum layer is sputter deposited, a layer of amorphous tantalum nitride is deposited over the amorphous tantalum layer by adding nitrogen gas to the sputtering chamber. This tantalum nitride layer prevents formation of a columnar structure in the growing tantalum film. Thus by alternately depositing tantalum and tantalum nitride layers, a dense amorphous barrier layer that is adherent to the substrate is deposited. If a thicker barrier layer is required, the tantalum and tantalum nitride depositions can be repeated as many times as are necessary to form the barrier layer thickness required. The tantalum nitride can also be deposited as the first layer, alternating with tantalum.
FIG. 3 is an X-ray diffraction study of tantalum (002 crystal orientation) versus the number of alternating tantalum and tantalum nitride layers. Deposition of tantalum alone (1000 Å thick) becomes less crystalline when a tantalum nitride layer is sandwiched between two tantalum layers. The total tantalum thickness is fixed at 1000 Å in the study. As the layering is repeated, the composite becomes still more amorphous and dense, and very little crystallinity is to be seen.
Another advantage to the present process and structure is that less nitrogen is used in the composite film than when tantalum nitride is deposited alone. This reduces the high film stress characteristic of tantalum nitride. High film stress contributes to a lack of adhesion between a barrier layer and a substrate, and results in barrier layer peeling, and the consequent formation of particles. Thus in accordance with the present process, particle reduction is also obtained.
The opening, now lined with a dense, wholly amorphous tantalum-containing layer, can be filled with copper, also by sputtering, to form a highly conductive via that has improved barrier properties that prevent diffusion of copper into an adjacent dielectric material during subsequent processing steps.
Although the invention has been described in terms of specific embodiments, the invention is only meant to be limited by the scope of the appended claims.

Claims (4)

We claim:
1. A method of making amorphous barrier layers to line an opening to be filled with copper comprising
a) sputter depositing a first layer selected from the group consisting of tantalum and tantalum nitride in said opening;
b) sputter depositing a second layer of the other of tantalum and tantalum nitride to line the bottom and sidewalls of the opening; and
c) alternately repeating steps a) and b) until the layer is substantially amorphous.
2. A method according to claim 1 wherein the first layer is tantalum and the second layer is tantalum nitride.
3. A method according to claim 1 wherein the first layer is tantalum nitride and the second layer is tantalum.
4. A method of making a conductive via comprising
a) sputter depositing a first layer selected from the group consisting of tantalum and tantalum nitride in said opening,
b) sputter depositing a second layer of tantalum and tantalum nitride to line the bottom and sidewalls of the opening;
c) alternately repeating steps a) and b) until a preselected thickness of the liner is obtained and the liner is substantially amorphous, and
d) filling said opening with copper.
US08/841,058 1997-04-29 1997-04-29 Tantalum-containing barrier layers for copper Expired - Lifetime US6057237A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US08/841,058 US6057237A (en) 1997-04-29 1997-04-29 Tantalum-containing barrier layers for copper
EP98303338A EP0875924A3 (en) 1997-04-29 1998-04-29 Improved tantalum-containing barrier layers for copper
KR1019980015253A KR19980081819A (en) 1997-04-29 1998-04-29 Tantalum containing barrier layer for copper
JP10158286A JPH1174224A (en) 1997-04-29 1998-04-30 Improved tantalum-containing barrier layers for copper
TW087106617A TW565625B (en) 1997-04-29 1998-04-30 Improved tantalum-containing barrier layers for copper

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/841,058 US6057237A (en) 1997-04-29 1997-04-29 Tantalum-containing barrier layers for copper

Publications (1)

Publication Number Publication Date
US6057237A true US6057237A (en) 2000-05-02

Family

ID=25283915

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/841,058 Expired - Lifetime US6057237A (en) 1997-04-29 1997-04-29 Tantalum-containing barrier layers for copper

Country Status (5)

Country Link
US (1) US6057237A (en)
EP (1) EP0875924A3 (en)
JP (1) JPH1174224A (en)
KR (1) KR19980081819A (en)
TW (1) TW565625B (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232664B1 (en) * 1998-05-28 2001-05-15 Fujitsu Limited Semiconductor device having A1 alloy wiring
US20010023988A1 (en) * 2000-03-27 2001-09-27 Kabushiki Kaisha Toshiba Semiconductor device
US6365502B1 (en) 1998-12-22 2002-04-02 Cvc Products, Inc. Microelectronic interconnect material with adhesion promotion layer and fabrication method
US6380625B2 (en) 1999-01-13 2002-04-30 Advanced Micro Devices, Inc. Semiconductor interconnect barrier and manufacturing method thereof
US6444263B1 (en) 2000-09-15 2002-09-03 Cvc Products, Inc. Method of chemical-vapor deposition of a material
US6465867B1 (en) * 2001-02-21 2002-10-15 Advanced Micro Devices, Inc. Amorphous and gradated barrier layer for integrated circuit interconnects
US20030150898A1 (en) * 1997-06-10 2003-08-14 Agere Systems Inc. Micromagnetic device for power processing applications and method of manufacture therefor
US20030159922A1 (en) * 2000-02-25 2003-08-28 Miley George H. Electrical cells, components and methods
US6627995B2 (en) 2000-03-03 2003-09-30 Cvc Products, Inc. Microelectronic interconnect material with adhesion promotion layer and fabrication method
WO2003083965A2 (en) * 2002-03-26 2003-10-09 Lattice Energy, L.L.C. Electrode constructs, and related cells and methods
US6649422B2 (en) 1999-06-22 2003-11-18 Agere Systems Inc. Integrated circuit having a micromagnetic device and method of manufacture therefor
US6696744B2 (en) 1997-06-10 2004-02-24 Agere Systems, Inc. Integrated circuit having a micromagnetic device and method of manufacture therefor
US20050064708A1 (en) * 2003-03-26 2005-03-24 May Charles E. Via and metal line interface capable of reducing the incidence of electro-migration induced voids
US20050070097A1 (en) * 2003-09-29 2005-03-31 International Business Machines Corporation Atomic laminates for diffusion barrier applications
US20060220083A1 (en) * 2005-01-26 2006-10-05 Oki Electric Industry Co., Ltd. Semiconductor device
US20060292726A1 (en) * 2004-11-26 2006-12-28 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US20070280848A1 (en) * 2004-03-24 2007-12-06 Jagdish Narayan Methods Of Forming Alpha And Beta Tantalum Films With Controlled And New Microstructures
US20130078178A1 (en) * 2011-09-27 2013-03-28 Samsung Electronics Co., Ltd. Method and apparatus for fabrication of carbon nanotubes using an electrostatically charged substrate and liner
CN110970350A (en) * 2018-09-28 2020-04-07 长鑫存储技术有限公司 Method for preparing a diffusion barrier comprising an α -Ta layer and composite diffusion barrier
US20220139706A1 (en) * 2020-11-02 2022-05-05 Applied Materials, Inc. Methods and apparatus for processing a substrate

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3149846B2 (en) 1998-04-17 2001-03-26 日本電気株式会社 Semiconductor device and manufacturing method thereof
US6265311B1 (en) 1999-04-27 2001-07-24 Tokyo Electron Limited PECVD of TaN films from tantalum halide precursors
US6410433B1 (en) * 1999-04-27 2002-06-25 Tokyo Electron Limited Thermal CVD of TaN films from tantalum halide precursors
US6410432B1 (en) 1999-04-27 2002-06-25 Tokyo Electron Limited CVD of integrated Ta and TaNx films from tantalum halide precursors
US6413860B1 (en) * 1999-04-27 2002-07-02 Tokyo Electron Limited PECVD of Ta films from tanatalum halide precursors
US6727593B2 (en) 2001-03-01 2004-04-27 Kabushiki Kaisha Toshiba Semiconductor device with improved bonding
AU2003205895A1 (en) 2002-02-28 2003-09-09 Trikon Technologies Limited A method of depositing a barrier layer
DE102005023122A1 (en) * 2005-05-19 2006-11-23 Infineon Technologies Ag Integrated circuit arrangement with layer stack and method
TWI811037B (en) 2016-07-27 2023-08-01 美商應用材料股份有限公司 Extreme ultraviolet mask blank with multilayer absorber and method of manufacture
TW202028495A (en) * 2018-12-21 2020-08-01 美商應用材料股份有限公司 Extreme ultraviolet mask absorber and processes for manufacture
US11630385B2 (en) 2020-01-24 2023-04-18 Applied Materials, Inc. Extreme ultraviolet mask absorber materials
TW202131087A (en) 2020-01-27 2021-08-16 美商應用材料股份有限公司 Extreme ultraviolet mask absorber materials
TW202141165A (en) 2020-03-27 2021-11-01 美商應用材料股份有限公司 Extreme ultraviolet mask absorber materials
US11644741B2 (en) 2020-04-17 2023-05-09 Applied Materials, Inc. Extreme ultraviolet mask absorber materials
TW202202641A (en) 2020-07-13 2022-01-16 美商應用材料股份有限公司 Extreme ultraviolet mask absorber materials
US11609490B2 (en) 2020-10-06 2023-03-21 Applied Materials, Inc. Extreme ultraviolet mask absorber materials
US11513437B2 (en) 2021-01-11 2022-11-29 Applied Materials, Inc. Extreme ultraviolet mask absorber materials
US11592738B2 (en) 2021-01-28 2023-02-28 Applied Materials, Inc. Extreme ultraviolet mask absorber materials

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5676587A (en) * 1995-12-06 1997-10-14 International Business Machines Corporation Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211880A (en) * 1990-01-17 1991-09-17 Toshiba Corp Forming method for schottky junction
EP0751566A3 (en) * 1995-06-30 1997-02-26 Ibm A thin film metal barrier for electrical interconnections
US5962923A (en) * 1995-08-07 1999-10-05 Applied Materials, Inc. Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5676587A (en) * 1995-12-06 1997-10-14 International Business Machines Corporation Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030150898A1 (en) * 1997-06-10 2003-08-14 Agere Systems Inc. Micromagnetic device for power processing applications and method of manufacture therefor
US7021518B2 (en) 1997-06-10 2006-04-04 Agere Systems Inc. Micromagnetic device for power processing applications and method of manufacture therefor
US6696744B2 (en) 1997-06-10 2004-02-24 Agere Systems, Inc. Integrated circuit having a micromagnetic device and method of manufacture therefor
US6232664B1 (en) * 1998-05-28 2001-05-15 Fujitsu Limited Semiconductor device having A1 alloy wiring
US6812126B1 (en) 1998-12-22 2004-11-02 Cvc Products, Inc. Method for fabricating a semiconductor chip interconnect
US6365502B1 (en) 1998-12-22 2002-04-02 Cvc Products, Inc. Microelectronic interconnect material with adhesion promotion layer and fabrication method
US6645847B2 (en) 1998-12-22 2003-11-11 Cvc Products, Inc. Microelectronic interconnect material with adhesion promotion layer and fabrication method
US6380625B2 (en) 1999-01-13 2002-04-30 Advanced Micro Devices, Inc. Semiconductor interconnect barrier and manufacturing method thereof
US6649422B2 (en) 1999-06-22 2003-11-18 Agere Systems Inc. Integrated circuit having a micromagnetic device and method of manufacture therefor
US7244887B2 (en) 2000-02-25 2007-07-17 Lattice Energy Llc Electrical cells, components and methods
US20030159922A1 (en) * 2000-02-25 2003-08-28 Miley George H. Electrical cells, components and methods
US6627995B2 (en) 2000-03-03 2003-09-30 Cvc Products, Inc. Microelectronic interconnect material with adhesion promotion layer and fabrication method
US20010023988A1 (en) * 2000-03-27 2001-09-27 Kabushiki Kaisha Toshiba Semiconductor device
US6909191B2 (en) * 2000-03-27 2005-06-21 Kabushiki Kaisha Toshiba Semiconductor device
US6444263B1 (en) 2000-09-15 2002-09-03 Cvc Products, Inc. Method of chemical-vapor deposition of a material
US6465867B1 (en) * 2001-02-21 2002-10-15 Advanced Micro Devices, Inc. Amorphous and gradated barrier layer for integrated circuit interconnects
WO2003083965A3 (en) * 2002-03-26 2004-01-08 Lattice Energy L L C Electrode constructs, and related cells and methods
WO2003083965A2 (en) * 2002-03-26 2003-10-09 Lattice Energy, L.L.C. Electrode constructs, and related cells and methods
US20040108205A1 (en) * 2002-03-26 2004-06-10 Larsen Lewis G. Electrode constructs, and related cells and methods
US6921469B2 (en) 2002-03-26 2005-07-26 Lattice Energy Llc Electrode constructs, and related cells and methods
US20050064708A1 (en) * 2003-03-26 2005-03-24 May Charles E. Via and metal line interface capable of reducing the incidence of electro-migration induced voids
US20050070097A1 (en) * 2003-09-29 2005-03-31 International Business Machines Corporation Atomic laminates for diffusion barrier applications
US20070280848A1 (en) * 2004-03-24 2007-12-06 Jagdish Narayan Methods Of Forming Alpha And Beta Tantalum Films With Controlled And New Microstructures
US20060292726A1 (en) * 2004-11-26 2006-12-28 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US8003449B2 (en) * 2004-11-26 2011-08-23 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device having a reverse staggered thin film transistor
US8399313B2 (en) 2004-11-26 2013-03-19 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device having first conductive layer including aluminum
US20060220083A1 (en) * 2005-01-26 2006-10-05 Oki Electric Industry Co., Ltd. Semiconductor device
US7646050B2 (en) * 2005-01-26 2010-01-12 Oki Semiconductor Co., Ltd. Ferroelectric type semiconductor device having a barrier TiO and TiON type dielectric film
US20130078178A1 (en) * 2011-09-27 2013-03-28 Samsung Electronics Co., Ltd. Method and apparatus for fabrication of carbon nanotubes using an electrostatically charged substrate and liner
US8887663B2 (en) * 2011-09-27 2014-11-18 Samsung Austin Semiconductor, L.P. Method and apparatus for fabrication of carbon nanotubes using an electrostatically charged substrate and liner
CN110970350A (en) * 2018-09-28 2020-04-07 长鑫存储技术有限公司 Method for preparing a diffusion barrier comprising an α -Ta layer and composite diffusion barrier
US20220139706A1 (en) * 2020-11-02 2022-05-05 Applied Materials, Inc. Methods and apparatus for processing a substrate

Also Published As

Publication number Publication date
EP0875924A3 (en) 2000-05-10
KR19980081819A (en) 1998-11-25
JPH1174224A (en) 1999-03-16
TW565625B (en) 2003-12-11
EP0875924A2 (en) 1998-11-04

Similar Documents

Publication Publication Date Title
US6057237A (en) Tantalum-containing barrier layers for copper
US6538324B1 (en) Multi-layered wiring layer and method of fabricating the same
CN1111908C (en) Semiconductor device
US6238533B1 (en) Integrated PVD system for aluminum hole filling using ionized metal adhesion layer
US5081064A (en) Method of forming electrical contact between interconnection layers located at different layer levels
US20020068458A1 (en) Method for integrated in-situ cleaning and susequent atomic layer deposition within a single processing chamber
US6410986B1 (en) Multi-layered titanium nitride barrier structure
JPH1041247A (en) Blanket selective deposition of cvd al using self-aligned ultra-thin film and improvement of reflectivity
EP0811243A1 (en) A PROCESS FOR IN-SITU DEPOSITION OF A Ti/TiN/Ti ALUMINUM UNDERLAYER
US6048788A (en) Method of fabricating metal plug
EP0818817A2 (en) Aluminium hole filling using ionized metal adhesion layer
US6514848B1 (en) Method for forming an interconnection in a semiconductor element
US6077782A (en) Method to improve the texture of aluminum metallization
JP2000183064A (en) Semiconductor device and manufacture thereof
KR100365061B1 (en) Semiconductor device and semiconductor device manufacturing method
JP3315211B2 (en) Electronic components
US6120842A (en) TiN+Al films and processes
Wang et al. Ta and Ta–N diffusion barriers sputtered with various N 2/Ar ratios for Cu metallization
KR100560296B1 (en) Method for manufacturing multi-thin film metal layer
Joshi et al. Collimated sputtering of TiN/Ti liners into sub‐half‐micrometer high aspect ratio contacts/lines
KR20020009013A (en) Metal thin film of semiconductor device and method for forming the same
US20030214039A1 (en) Method for fabricating semiconductor device having tertiary diffusion barrier layer for copper line
US20050181600A1 (en) Method of forming a semiconductor device having a Ti/TiN/Ti<002>/a1<111> laminate
EP0839927A2 (en) Method of forming films comprising TiN and Al
KR0183772B1 (en) Forming method of titanium nitride thin film

Legal Events

Date Code Title Description
AS Assignment

Owner name: APPLIED MATERIALS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DING, PEIJUN;CHIANG, TONY PING-CHEN;REEL/FRAME:008532/0107;SIGNING DATES FROM 19970424 TO 19970425

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12