US6033943A - Dual gate oxide thickness integrated circuit and process for making same - Google Patents

Dual gate oxide thickness integrated circuit and process for making same Download PDF

Info

Publication number
US6033943A
US6033943A US08/702,270 US70227096A US6033943A US 6033943 A US6033943 A US 6033943A US 70227096 A US70227096 A US 70227096A US 6033943 A US6033943 A US 6033943A
Authority
US
United States
Prior art keywords
dielectric layer
region
semiconductor substrate
layer
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/702,270
Inventor
Mark I. Gardner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to US08/702,270 priority Critical patent/US6033943A/en
Assigned to ADVANCED MICRO DEVICES, INC. reassignment ADVANCED MICRO DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GARDNER, MARK I.
Priority to PCT/US1997/009424 priority patent/WO1998008253A1/en
Application granted granted Critical
Publication of US6033943A publication Critical patent/US6033943A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Definitions

  • the invention relates to the field of semiconductor processing and more particularly to a MOS integrated circuit in which select transistors are fabricated with a thinner gate oxide than the remaining transistors.
  • VLSI metal-oxide-semiconductor (“MOS”) circuits include a large number of interconnected transistors formed in a semiconductor substrate, typically comprised of silicon.
  • the gate electrode of the MOS transistor functions as the transistor's input.
  • the transistor is typically activated or turned on by driving the gate voltage (V G ) to a threshold value referred to as the threshold voltage (V T ).
  • the drain current (I D ) of an MOS transistor typically serves as the transistor's output. Because the gate electrode of each transistor has a small but finite capacitance associated with it, the gate electrode cannot instantaneously achieve a desired change in voltage. Instead, a finite amount of time is required to charge the small gate capacitor to the appropriate voltage level.
  • the amount of time required for a gate electrode to achieve a threshold level can be reduced by decreasing the capacitance of the gate electrode or increasing the drain current of transistors from preceding stages.
  • V D drain voltage
  • I D saturated drain current
  • I Dsat is the maximum drain current produced by an MOS transistor operating under normal biasing (i.e., V D ⁇ V CC ,
  • , and V SS 0 V) for a given gate voltage.
  • I Dsat is, therefore, a direct measure of the potential speed of an MOS circuit. Increasing I Dsat increases the integrated circuit's performance by enabling each transistor to drive subsequent stages of transistors to their threshold voltage in less time.
  • the capacitance, C OX of an MOS transistor is closely approximated by that of a parallel plate capacitor such that C OX ⁇ A.di-elect cons./t OX , where A is the area of the gate structure, .di-elect cons. is the permitivity of the dielectric, and t OX is the oxide thickness. Because it is undesirable to increase the area of the gate and difficult to alter the dielectric, increasing the capacitance C OX must be accomplished by decreasing the oxide thickness t OX .
  • CMOS complementary metal oxide semiconductor
  • the gate structures for the transistors are formed from heavily doped polysilicon.
  • CMOS complementary metal oxide semiconductor
  • the doping of the p-channel polysilicon gate with boron can become problematic for thin gate oxide structures due to the relatively rapid rate at which boron diffuses through silicon dioxide.
  • boron ions from the heavily doped p+ polysilicon can diffuse through the oxide into the silicon bulk, thereby shifting the threshold voltage V T of the p-channel devices.
  • This limitation on the thickness of the p-channel oxide has typically limited the oxide thickness of the n-channel devices as well because it is highly desirable from a manufacturing perspective to grow the capacitor or gate oxide non-selectively (i.e., grow the gate across the entire wafer rather than in selected or masked regions of the wafer).
  • the blanket oxide growth tends to result in oxide thicknesses that are uniform across the entire wafer.
  • conventional processing considerations teach away from multiple gate oxide thicknesses within a topography because of the asymmetry that would result from the use of such multiple thickness oxide topographies.
  • symmetry considerations have prohibited designs in which selected critical transistors could be designated as high-performance, thin-oxide transistors. It would, therefore, be desirable to achieve a semiconductor manufacturing process in which selected transistors incorporate a gate oxide having a first thickness while the remaining transistors have a second gate oxide thickness without unduly complicating the process flow.
  • a first gate dielectric is formed on an upper surface of a semiconductor substrate. Thereafter, a masking layer is deposited on the first dielectric layer and patterned such that the first dielectric layer is exposed above a second region of the semiconductor substrate. The semiconductor wafer is then subjected to a thermal oxidation process such that a second gate dielectric is formed within the exposed second region of the semiconductor substrate.
  • the second gate dielectric can have an oxide thickness that is unequal to the oxide thickness of the first gate dielectric layer.
  • gate structures and source/drain structures are fabricated such that the integrated circuit includes a first transistor having a first gate dielectric thickness and a second transistor having a second gate dielectric thickness. In this manner, the integrated circuit can include selected transistors having a thinner gate dielectric for improving the performance of these select transistors.
  • the n-channel transistors in a CMOS integrated circuit have a thinner gate oxide than the p-channel devices.
  • the present invention contemplates a semiconductor process in which a semiconductor wafer is provided.
  • the semiconductor wafer includes a semiconductor substrate comprising a first region and a second region. The first region is laterally displaced from the second region.
  • a first dielectric layer is then formed on an upper surface of the semiconductor substrate.
  • the first dielectric layer has a first thickness.
  • a masking layer is then deposited on the first dielectric layer and patterned to expose the first dielectric layer above the second region of the semiconductor substrate.
  • the wafer is then subjected to a oxygen-bearing ambient at a temperature of approximately 700-1000° C. such that a second dielectric layer is formed over the second region of the semiconductor substrate.
  • the second dielectric layer has a second thickness.
  • the time during which the wafer is subjected to the high temperature ambient is such that the first thickness is greater than the second thickness while in another embodiment, the second thickness is greater than the first thickness.
  • the masking layer is then removed from the upper surface of the first dielectric layer and gate structures are then formed on upper surfaces of the first and second dielectric layers, respectively.
  • the first and second gate structures are laterally aligned over first and second channel regions within the semiconductor substrate. Impurities are then introduced into a first and a second pair of source/drain regions laterally displaced on either side of the first and second channel regions to form first and second transistors.
  • the first dielectric layer serves as the gate dielectric for the first transistor while the second dielectric layer serves as the gate dielectric for the second transistor.
  • the first region of a semiconductor substrate comprises p-type silicon and the second region of the semiconductor substrate comprises n-type silicon.
  • the thickness of the first dielectric layer is preferably less than the thickness of the second dielectric layer.
  • the step of forming the first dielectric layer comprises subjecting the wafer to a first oxygen-bearing ambient at a temperature of approximately 700-1000° C. such that the first dielectric layer comprises a thermal oxide.
  • the first thickness is approximately 15-25 Angstroms.
  • the step of depositing the masking layer preferably comprises chemical vapor depositing silicon nitride or polysilicon onto the upper surface of the first and second dielectric layers.
  • the masking layer is preferably patterned by depositing a photoresist layer on the masking layer, selectively exposing the photoresist layer to an energy source to form exposed regions within the photoresist layer, and developing the photoresist layer by removing the exposed regions of the photoresist layer.
  • the first and second gate structures are formed by chemical vapor depositing a polysilicon layer on a surface cooperatively defined by an upper surface of the first dielectric layer and an upper surface of the second dielectric layer and patterning the polysilicon layer by doping the polysilicon layer with impurities such that a sheet resistivity of the first and second gate structures is less than approximately 500 ⁇ /sq, removing portions of the polysilicon layer exterior to a first channel region and a second channel region of the semiconductor substrate.
  • the patterning of the polysilicon layer is preferably performed with conventional photoresist, photolithography, and etch processing steps.
  • the step of doping the polysilicon layer preferably comprises doping portions of the polysilicon layer over the first region of semiconductor substrate with n-type impurities and doping the polysilicon layer over second regions of the semiconductor substrate with a p-type impurity such as boron.
  • the selective doping of the polysilicon layer can be accomplished with ion implantation steps in conjunction with conventional photoresist and photoresist masking steps.
  • the semiconductor process preferably further comprises forming an isolation dielectric structure laterally disposed between the first region and the second region of the semiconductor substrate prior to the forming of the first dielectric layer.
  • the isolation dielectric structure comprises a shallow trench isolation.
  • the step of introducing impurities into the source/drain regions comprises implanting ions selected from the group consisting of boron, arsenic, and phosphorus.
  • the implanting of ions comprises implanting phosphorus or arsenic ions into the first pair of source/drain regions and implanting boron ions into the second pair of source/drain regions.
  • the present invention further contemplates an MOS integrated circuit in which a semiconductor substrate comprises a first region and a second region which is laterally displaced from the first region.
  • a first transistor is formed within the first region of the semiconductor substrate.
  • the first gate dielectric of the first transistor has a first thickness.
  • a second transistor is formed in the second region of the semiconductor substrate.
  • the second gate dielectric of the second transistor has a second thickness.
  • the second thickness is greater than the first thickness such that the first transistor has a greater oxide capacitance, C OX , than the second transistor whereby the saturated drain current of transistors formed with the first gate dielectric is greater than similarly dimensioned transistors formed with the second gate dielectric.
  • the semiconductor substrate of the integrated circuit comprises single crystal silicon in which the first region of the semiconductor substrate comprises p-type silicon and the second region of the semiconductor substrate comprises n-type silicon.
  • the first transistor comprises an n-type polysilicon gate structure formed over the first gate dielectric and a pair of n-type source/drain regions formed within an upper surface of the semiconductor substrate. The n-type source/drain regions are laterally disposed on either side of a first channel region of the semiconductor substrate.
  • the second transistor comprises a p-type polysilicon gate structure formed over the second gate dielectric layer. A pair of p-type source/drain regions are formed within an upper surface of the semiconductor substrate.
  • the p-type source/drain regions are laterally disposed on either side of a second channel region of the semiconductor substrate. Still more preferably, the first thickness of the first gate dielectric is approximately 15-25 Angstroms while the second gate dielectric is approximately 30-50 Angstroms thick.
  • FIG. 1 is a partial cross-sectional view of a semiconductor wafer including a semiconductor substrate
  • FIG. 2 is a processing step subsequent to FIG. 1, in which an isolation dielectric structure has been formed within the semiconductor substrate and a first gate dielectric layer has been formed on an upper surface of the semiconductor substrate;
  • FIG. 3 is a processing step subsequent to FIG. 2, in which a masking layer has been formed on an upper surface of the first dielectric layer;
  • FIG. 4 is a processing step subsequent to FIG. 3, in which a photoresist layer has been formed on an upper surface of the masking layer and the masking layer and photoresist layer have been patterned to remove portions of those layers above a second region of the semiconductor substrate;
  • FIG. 5 is a processing step subsequent to FIG. 4, in which the semiconductor substrate is immersed in a high temperature oxygen-bearing ambient to form a second dielectric layer on an upper surface of the semiconductor substrate;
  • FIG. 6 is a processing step subsequent to FIG. 5, in which the masking layer has been removed from an upper surface of the first dielectric layer;
  • FIG. 7 is a processing step subsequent to FIG. 6, in which a conductive gate layer has been deposited on an upper surface of the first and second gate dielectric layers;
  • FIG. 8 is a processing step subsequent to FIG. 7, in which the conductive gate layer has been patterned to form first and second gate structures over the first and second regions of the semiconductor substrate, respectively;
  • FIG. 9 is a processing step subsequent to FIG. 8, in which first and second transistors have been formed by introducing source/drain impurities into source/drain regions laterally displaced on either side of first and second channel regions within the semiconductor substrate;
  • FIG. 10 is an alternative processing step subsequent to FIG. 4, in which the first oxide layer over the second substrate region has been removed.
  • FIG. 11 is a processing step subsequent to FIG. 10, in which a second gate dielectric layer has been formed over the second region of the semiconductor substrate such that the thickness of the second gate dielectric is less than the thickness of the first gate dielectric.
  • FIG. 1 shows a semiconductor wafer 100.
  • the wafer 100 comprises a semiconductor substrate 102.
  • the semiconductor substrate 102 includes a first region 104 laterally displaced from a second region 106.
  • the semiconductor substrate 102 comprises single crystal silicon.
  • first region 104 of semiconductor substrate 102 comprises p-type silicon while second region 106 comprises n-type silicon.
  • the p-type and n-type silicon shown in FIG. 1 may reside upon a silicon bulk (not shown in the drawing) preferably comprised of p-type silicon having a resistivity of approximately 12-15 ⁇ -cm.
  • Semiconductor substrate 102 further includes upper surface 101.
  • isolation dielectric structure 107 is formed laterally displaced between first region 104 and second region 106 of semiconductor substrate 102.
  • Isolation dielectric 107 is preferably comprised of an oxide such that first region and second region 106 of semiconductor substrate are electrically isolated from one another.
  • isolation dielectric structure 107 comprises a shallow trench isolation structure. Shallow trench isolation structures are formed by etching a trench shaped void into an upper surface of semiconductor substrate 102 such that the trench shaped void extends downward from upper surface 101. Thereafter, the trench shaped void is filled with a dielectric material, preferably a CVD oxide.
  • isolation dielectric structure 107 that is substantially coplanar with upper surface 101 of semiconductor substrate 102.
  • a planarization step such as a chemical-mechanical polish possibly in conjunction with photoresist masking steps and wet and dry etch steps to produce an upper surface of isolation dielectric structure 107 that is substantially coplanar with upper surface 101 of semiconductor substrate 102.
  • LOCOS structures are formed by selectively growing a thermal oxide in an upper surface of semiconductor substrate 102. The selective oxide growth is achieved by patterning a silicon nitride layer over the silicon substrate prior to the thermal oxidation step. While the LOCOS isolation process is well developed, it has the dual disadvantages of (1) producing a non-planar surface and (2) encroaching upon the active areas of the semiconductor substrate with the well-known bird's beak structure.
  • first dielectric layer 108 is formed on upper surface 101 of semiconductor substrate 102.
  • First dielectric layer 108 preferably comprises silicon dioxide formed with a conventional thermal oxidation step during which wafer 100 is subjected to a first high temperature, oxygen bearing ambient.
  • the first high temperature, oxygen bearing ambient is preferably between 700 to 1000° C.
  • First dielectric layer 108 can be formed in a batch process tube-type thermal oxidation furnace or, alternatively, with rapid thermal processing techniques. Rapid thermal processing involves rapidly heating a single wafer to a desired temperature and sustaining the wafer at the elevated temperature for a short duration, typically from a few seconds to a few minutes.
  • rapid thermal processing minimizes undesirable redistribution of any impurity concentrations that are present in the substrate such as the channel stop implant distribution or the well implant distributions in a CMOS process.
  • rapid thermal processing can result in the formation of an SiO 2 film, such as first dielectric layer 108, on the wafer surface.
  • the present invention contemplates an integrated circuit in which a first transistor has a gate oxide thickness that is different than the gate oxide thickness of a second transistor.
  • the gate oxide thickness of the first transistor formed within first region 104 of semiconductor substrate 102 is greater than the thickness of the gate oxide of the second transistor formed over the second region 106 of semiconductor substrate 102.
  • first dielectric layer 108 has a thickness of approximately 25-200 Angstroms.
  • the oxide thickness of the transistor formed in first region 104 may be less than the oxide thickness of the transistor formed over second substrate 106.
  • a thickness of first dielectric 108 is approximately 15-25 Angstroms.
  • a masking layer 110 is formed upon an upper surface of first dielectric layer 108.
  • masking layer 110 comprises CVD silicon nitride or polysilicon.
  • the thickness of the masking layer 110 is approximately 100-1000 Angstroms.
  • masking layer 110 may comprise polycrystalline silicon (polysilicon).
  • photoresist layer 112 is deposited upon masking layer 110 prior to patterning photoresist layer 112 and masking layer 110.
  • the patterning of photoresist layer 112 and masking layer 110 removes portions of the layers above second region 106 of semiconductor substrate 102.
  • the patterning of masking layer 110 with either a wet or dry etch process can result in some etching of first dielectric layer 108 such that a residual oxide 113 having a thickness that is less than a thickness of first dielectric layer 108 is left over second region 106 of semiconductor substrate 102.
  • the patterning of masking layer 110 may be performed such all of first dielectric layer 108 over second region 106 of semiconductor substrate 102 is removed.
  • FIG. 10 This alternative embodiment is shown in FIG. 10.
  • wafer 100 is immersed in a second high temperature, oxygen-bearing ambient 114 such that second dielectric layer 116 is formed over second region 106 of semiconductor substrate 102.
  • High temperature ambient 114 comprises an oxygen bearing species such as O 2 or H 2 O at a temperature of approximately 700-1000° C.
  • an ambient such as high temperature, oxygen-bearing ambient 114 will interact with semiconductor substrate 102 to form a dielectric such as SiO 2 .
  • second dielectric layer 116 may be grown from no initial oxide as shown in FIG. 10 or may comprise a re-oxidation of residual oxide 113. In the embodiment shown in FIGS.
  • second dielectric layer 116 has a thickness t 2 that is greater than a thickness t 1 of first dielectric 108.
  • second dielectric 116 has a thickness t 2 that is less than a thickness t 1 of first dielectric 108.
  • first dielectric thickness t 1 is preferably between 15-25 Angstroms while second dielectric thickness t 2 has a thickness that is preferably between 30-200 Angstroms.
  • second dielectric t 2 preferably has a thickness that is approximately 15-25 Angstroms and first dielectric thickness t 1 is approximately 30-200 Angstroms.
  • Second dielectric layer 116 like first dielectric layer 108 can be formed in a thermal oxidation furnace or in a rapid thermal processing apparatus.
  • FIGS. 7-9 show processing steps for forming transistors upon the dual oxide thicknesses.
  • FIGS. 7-9 disclose an embodiment in which second dielectric 116 has a thickness t 2 that is greater than a thickness t 1 of first dielectric 108, it is to be understood that the processing steps shown in FIGS. 7-9 are equally applicable to an embodiment in which second dielectric layer 116 is thinner than first dielectric layer 108.
  • a conductive gate layer 118 is deposited upon a topography cooperatively defined by an upper surface of first dielectric layer 108 and second dielectric layer 116.
  • conductive gate layer 118 comprises CVD polysilicon.
  • processing steps 119a and 119b are also shown in which impurities are introduced into conductive gate layer 118 to reduce the sheet resistivity of conductive gate layer 118.
  • processing steps 119a and 119b result in a sheet resistivity of conductive gate layer 118 that is less than approximately 500 ⁇ /sq.
  • Processing steps 119a and 119b may comprise separate processing steps such that the portion of conductive gate layer 118 over first substrate region 104 is selectively doped with respect to a portion of conductive gate layer 118 over second substrate region 106.
  • processing steps 119a and 119b contemplates a first implant 119a in which n-type impurities such as phosphorus or arsenic are introduced, preferably through an ion implantation, into conductive gate layer 118 over first region 104 of semiconductor substrate 102.
  • This embodiment further contemplates a second processing step 119b in which p-type impurities such as boron are introduced into conductive layer 118 over second region 106 of semiconductor substrate 102.
  • p-type impurities such as boron
  • the selective introduction of the impurities into their corresponding regions of conductive layer 118 is carried out through the use of a conventional photoresist masking step.
  • processing steps 119a and 119b may comprise a single processing step such as a single implant or a diffusion step subsequent to the deposition of first conductive layer 118.
  • FIG. 8 shows a processing step subsequent to FIG. 7 in which first and second gate structures 120a and 120b are formed over first and second channel regions 121a and 121b, respectively, of semiconductor substrate 102.
  • the formation of gate structures 120 is preferably accomplished with a photolithography step, and more preferably in conjunction with a dry etch process such that gate structures 120 are formed with substantially vertical sidewalls 123a and 123b.
  • first and second transistors 122a and 122b are formed over first substrate region 104 and second substrate region 106, respectively of semiconductor substrate 102.
  • transistors 122 are formed by introducing impurities into source/drain regions 124 within an upper region of the semiconductor substrate 102.
  • Source/drain regions 124 are laterally displaced on either side of channel regions 121 within semiconductor substrate 102.
  • source/drain regions 124 comprise LDD regions 126 and heavily implanted regions 130.
  • LDD regions 126 are used to reduce the maximum electric field within semiconductor substrate 102 to minimize the occurrence of hot electron injection.
  • LDD regions 126 are formed by implanting a first concentration of a first impurity type into an upper region of semiconductor substrate 102.
  • LDD spacers 128 are formed on sidewalls 123 of gate structures 120.
  • the formation of spacer structures 128 comprises depositing a conformal dielectric layer such as a CVD oxide formed from a TEOS source and anisotropically etching the dielectric layer with minimum overetch such that the dielectric layer is just cleared from the planar regions of the topography.
  • impurities are introduced into heavily doped regions 130 through a subsequent implantation step.
  • the peak doping concentration of LDD 126 is less than the peak doping concentration of heavily doped region 130.
  • LDD regions 126b and heavily doped regions 130b comprise a concentration of boron ions while the LDD region 126a and heavily doped region 130a of the n-channel transistor 122a formed over the thinner gate oxide comprise a concentration of n-type ions such as phosphorus or arsenic.
  • the selective introduction of impurities into first substrate region 104 versus second substrate region 106 can be accomplished through the use of conventional photoresist masking steps.
  • first transistor 122a and second transistor 122b are both n-channel devices, it will be appreciated that the formation of source/drain regions 124a and 124b can be accomplished simultaneously.
  • FIG. 9 depicts an integrated circuit 132 comprising first transistor 122a and second transistor 122b.
  • First transistor 122a is formed within first substrate region 104 of semiconductor substrate 102 and includes a first dielectric layer 108 having a first dielectric thickness t 1 .
  • Integrated circuit 132 further comprises second transistor 122b.
  • Second transistor 122b comprises second dielectric layer 116 having a second dielectric thickness t 2 .
  • second dielectric thickness t 2 is greater than first dielectric thickness t 1 .
  • the capacitance, C ox1 , of first transistor 122a is substantially greater than the capacitance, C ox2 , of second transistor 122b.
  • First transistor 122a will, therefore, demonstrate a higher saturated drain current I Dsat than a similarly dimensioned second transistor 122b.
  • first transistor 122a is an n-channel device such that first gate structure 120a comprises heavily doped n-type polysilicon and first source/drain regions 124a comprise an ion concentration of phosphorus or arsenic.
  • second transistor 122b is a p-channel device in which second gate structure 120b comprises heavily doped p-type polysilicon and second source/drain regions 124b comprise ion concentrations of boron.
  • the thicker gate oxide of second dielectric layer 116 is used in conjunction with the p-channel transistor 122b to prevent boron diffusion through second dielectric 116 while permitting the optimization of n-channel transistor 122a by allowing a thinner first dielectric layer 108.

Abstract

A semiconductor manufacturing process for producing MOS integrated circuits having two gate oxide thickness is provided. A first gate dielectric is formed on an upper surface of a semiconductor substrate. Thereafter, a masking layer is deposited on the first dielectric layer and patterned such that the first dielectric layer is exposed above a second region of the semiconductor substrate. The semiconductor wafer is then subjected to a thermal oxidation process such that a second gate dielectric is formed within the exposed second region of the semiconductor substrate. The second gate dielectric preferably has an oxide thickness that is unequal to the oxide thickness of the first gate dielectric layer. Thereafter, gate structures and source/drain structures are fabricated such that the integrated circuit includes a first transistor having a first gate dielectric thickness and a second transistor having a second gate dielectric thickness. In this manner, the integrated circuit can include selected transistors having a thinner gate dielectric for improving the performance of these selected transistors. In one embodiment, the n-channel transistors in a CMOS integrated circuit have a thinner gate oxide than the p-channel devices.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of semiconductor processing and more particularly to a MOS integrated circuit in which select transistors are fabricated with a thinner gate oxide than the remaining transistors.
2. Description of the Relevant Art
Very large scale integrated (VLSI) metal-oxide-semiconductor ("MOS") circuits include a large number of interconnected transistors formed in a semiconductor substrate, typically comprised of silicon. Conventionally, the gate electrode of the MOS transistor functions as the transistor's input. The transistor is typically activated or turned on by driving the gate voltage (VG) to a threshold value referred to as the threshold voltage (VT). The drain current (ID) of an MOS transistor typically serves as the transistor's output. Because the gate electrode of each transistor has a small but finite capacitance associated with it, the gate electrode cannot instantaneously achieve a desired change in voltage. Instead, a finite amount of time is required to charge the small gate capacitor to the appropriate voltage level. The amount of time required for a gate electrode to achieve a threshold level can be reduced by decreasing the capacitance of the gate electrode or increasing the drain current of transistors from preceding stages. Generally, for small values of drain voltage, VD, (i.e., VD <VG -VT), the drain current ID of an MOS transistor increases linearly with the drain voltage (assuming VG ≧VT). As VD is increased beyond this linear region, however, ID levels off and becomes substantially independent of VD. This value of ID is commonly referred to as the saturated drain current, IDsat. In other words, IDsat is the maximum drain current produced by an MOS transistor operating under normal biasing (i.e., VD ≅VCC, |VG |≧|VT |, and VSS =0 V) for a given gate voltage. IDsat is, therefore, a direct measure of the potential speed of an MOS circuit. Increasing IDsat increases the integrated circuit's performance by enabling each transistor to drive subsequent stages of transistors to their threshold voltage in less time.
In the linear region, ID =k(VG -VDS /2) VDS, where k=μCOX W/L. Inspection of this equation reveals that ID can be increased by increasing the oxide capacitance COX. In addition to increasing k, a larger oxide capacitance reduces the threshold voltages VT for the general case in which the total charge QTOT trapped within the oxide and trapped at the oxide-silicon interface is relatively small. The capacitance, COX, of an MOS transistor is closely approximated by that of a parallel plate capacitor such that COX ≅A.di-elect cons./tOX, where A is the area of the gate structure, .di-elect cons. is the permitivity of the dielectric, and tOX is the oxide thickness. Because it is undesirable to increase the area of the gate and difficult to alter the dielectric, increasing the capacitance COX must be accomplished by decreasing the oxide thickness tOX.
In many complementary metal oxide semiconductor (CMOS) processes, the gate structures for the transistors are formed from heavily doped polysilicon. To achieve a degree of symmetry between the p-channel and n-channel transistors, it is not uncommon to dope the gate structures of the n-channel devices with arsenic or phosphorous and the gate structures of the p-channel devices with boron. The doping of the p-channel polysilicon gate with boron can become problematic for thin gate oxide structures due to the relatively rapid rate at which boron diffuses through silicon dioxide.
In very thin oxide structures, (i.e., tOX ≦3 nm), boron ions from the heavily doped p+ polysilicon can diffuse through the oxide into the silicon bulk, thereby shifting the threshold voltage VT of the p-channel devices. This limitation on the thickness of the p-channel oxide has typically limited the oxide thickness of the n-channel devices as well because it is highly desirable from a manufacturing perspective to grow the capacitor or gate oxide non-selectively (i.e., grow the gate across the entire wafer rather than in selected or masked regions of the wafer). The blanket oxide growth tends to result in oxide thicknesses that are uniform across the entire wafer. Furthermore, conventional processing considerations teach away from multiple gate oxide thicknesses within a topography because of the asymmetry that would result from the use of such multiple thickness oxide topographies.
The desire to maintain symmetry has undesirably limited the potential performance of the n-channel devices in certain CMOS processes by restricting the minimum thickness of the gate oxide. More generally, symmetry considerations have prohibited designs in which selected critical transistors could be designated as high-performance, thin-oxide transistors. It would, therefore, be desirable to achieve a semiconductor manufacturing process in which selected transistors incorporate a gate oxide having a first thickness while the remaining transistors have a second gate oxide thickness without unduly complicating the process flow.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a manufacturing process for producing an integrated circuit having two gate oxide thicknesses. A first gate dielectric is formed on an upper surface of a semiconductor substrate. Thereafter, a masking layer is deposited on the first dielectric layer and patterned such that the first dielectric layer is exposed above a second region of the semiconductor substrate. The semiconductor wafer is then subjected to a thermal oxidation process such that a second gate dielectric is formed within the exposed second region of the semiconductor substrate. The second gate dielectric can have an oxide thickness that is unequal to the oxide thickness of the first gate dielectric layer. Thereafter, gate structures and source/drain structures are fabricated such that the integrated circuit includes a first transistor having a first gate dielectric thickness and a second transistor having a second gate dielectric thickness. In this manner, the integrated circuit can include selected transistors having a thinner gate dielectric for improving the performance of these select transistors. In one embodiment, the n-channel transistors in a CMOS integrated circuit have a thinner gate oxide than the p-channel devices.
Broadly speaking, the present invention contemplates a semiconductor process in which a semiconductor wafer is provided. The semiconductor wafer includes a semiconductor substrate comprising a first region and a second region. The first region is laterally displaced from the second region. A first dielectric layer is then formed on an upper surface of the semiconductor substrate. The first dielectric layer has a first thickness. A masking layer is then deposited on the first dielectric layer and patterned to expose the first dielectric layer above the second region of the semiconductor substrate. The wafer is then subjected to a oxygen-bearing ambient at a temperature of approximately 700-1000° C. such that a second dielectric layer is formed over the second region of the semiconductor substrate. The second dielectric layer has a second thickness. In one embodiment, the time during which the wafer is subjected to the high temperature ambient is such that the first thickness is greater than the second thickness while in another embodiment, the second thickness is greater than the first thickness. The masking layer is then removed from the upper surface of the first dielectric layer and gate structures are then formed on upper surfaces of the first and second dielectric layers, respectively. The first and second gate structures are laterally aligned over first and second channel regions within the semiconductor substrate. Impurities are then introduced into a first and a second pair of source/drain regions laterally displaced on either side of the first and second channel regions to form first and second transistors. The first dielectric layer serves as the gate dielectric for the first transistor while the second dielectric layer serves as the gate dielectric for the second transistor.
In a CMOS embodiment, the first region of a semiconductor substrate comprises p-type silicon and the second region of the semiconductor substrate comprises n-type silicon. In this embodiment, the thickness of the first dielectric layer is preferably less than the thickness of the second dielectric layer.
Preferably, the step of forming the first dielectric layer comprises subjecting the wafer to a first oxygen-bearing ambient at a temperature of approximately 700-1000° C. such that the first dielectric layer comprises a thermal oxide. In a presently preferred embodiment in which the first dielectric layer is thinner than the second dielectric layer, the first thickness is approximately 15-25 Angstroms. The step of depositing the masking layer preferably comprises chemical vapor depositing silicon nitride or polysilicon onto the upper surface of the first and second dielectric layers. The masking layer is preferably patterned by depositing a photoresist layer on the masking layer, selectively exposing the photoresist layer to an energy source to form exposed regions within the photoresist layer, and developing the photoresist layer by removing the exposed regions of the photoresist layer.
The first and second gate structures are formed by chemical vapor depositing a polysilicon layer on a surface cooperatively defined by an upper surface of the first dielectric layer and an upper surface of the second dielectric layer and patterning the polysilicon layer by doping the polysilicon layer with impurities such that a sheet resistivity of the first and second gate structures is less than approximately 500 Ω/sq, removing portions of the polysilicon layer exterior to a first channel region and a second channel region of the semiconductor substrate. The patterning of the polysilicon layer is preferably performed with conventional photoresist, photolithography, and etch processing steps. In a presently preferred CMOS embodiment in which the n-channel devices are formed over the first substrate region, the step of doping the polysilicon layer preferably comprises doping portions of the polysilicon layer over the first region of semiconductor substrate with n-type impurities and doping the polysilicon layer over second regions of the semiconductor substrate with a p-type impurity such as boron. The selective doping of the polysilicon layer can be accomplished with ion implantation steps in conjunction with conventional photoresist and photoresist masking steps.
The semiconductor process preferably further comprises forming an isolation dielectric structure laterally disposed between the first region and the second region of the semiconductor substrate prior to the forming of the first dielectric layer. In a presently preferred embodiment, the isolation dielectric structure comprises a shallow trench isolation.
Preferably, the step of introducing impurities into the source/drain regions comprises implanting ions selected from the group consisting of boron, arsenic, and phosphorus. Still more preferably, the implanting of ions comprises implanting phosphorus or arsenic ions into the first pair of source/drain regions and implanting boron ions into the second pair of source/drain regions.
The present invention further contemplates an MOS integrated circuit in which a semiconductor substrate comprises a first region and a second region which is laterally displaced from the first region. A first transistor is formed within the first region of the semiconductor substrate. The first gate dielectric of the first transistor has a first thickness. A second transistor is formed in the second region of the semiconductor substrate. The second gate dielectric of the second transistor has a second thickness. The second thickness is greater than the first thickness such that the first transistor has a greater oxide capacitance, COX, than the second transistor whereby the saturated drain current of transistors formed with the first gate dielectric is greater than similarly dimensioned transistors formed with the second gate dielectric.
Preferably, the semiconductor substrate of the integrated circuit comprises single crystal silicon in which the first region of the semiconductor substrate comprises p-type silicon and the second region of the semiconductor substrate comprises n-type silicon. In a presently preferred CMOS embodiment of the integrated circuit, the first transistor comprises an n-type polysilicon gate structure formed over the first gate dielectric and a pair of n-type source/drain regions formed within an upper surface of the semiconductor substrate. The n-type source/drain regions are laterally disposed on either side of a first channel region of the semiconductor substrate. The second transistor comprises a p-type polysilicon gate structure formed over the second gate dielectric layer. A pair of p-type source/drain regions are formed within an upper surface of the semiconductor substrate. The p-type source/drain regions are laterally disposed on either side of a second channel region of the semiconductor substrate. Still more preferably, the first thickness of the first gate dielectric is approximately 15-25 Angstroms while the second gate dielectric is approximately 30-50 Angstroms thick.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and advantages of the present invention may become apparent upon reading the following detailed description and upon reference to the drawings in which:
FIG. 1 is a partial cross-sectional view of a semiconductor wafer including a semiconductor substrate;
FIG. 2 is a processing step subsequent to FIG. 1, in which an isolation dielectric structure has been formed within the semiconductor substrate and a first gate dielectric layer has been formed on an upper surface of the semiconductor substrate;
FIG. 3 is a processing step subsequent to FIG. 2, in which a masking layer has been formed on an upper surface of the first dielectric layer;
FIG. 4 is a processing step subsequent to FIG. 3, in which a photoresist layer has been formed on an upper surface of the masking layer and the masking layer and photoresist layer have been patterned to remove portions of those layers above a second region of the semiconductor substrate;
FIG. 5 is a processing step subsequent to FIG. 4, in which the semiconductor substrate is immersed in a high temperature oxygen-bearing ambient to form a second dielectric layer on an upper surface of the semiconductor substrate;
FIG. 6 is a processing step subsequent to FIG. 5, in which the masking layer has been removed from an upper surface of the first dielectric layer;
FIG. 7 is a processing step subsequent to FIG. 6, in which a conductive gate layer has been deposited on an upper surface of the first and second gate dielectric layers;
FIG. 8 is a processing step subsequent to FIG. 7, in which the conductive gate layer has been patterned to form first and second gate structures over the first and second regions of the semiconductor substrate, respectively;
FIG. 9 is a processing step subsequent to FIG. 8, in which first and second transistors have been formed by introducing source/drain impurities into source/drain regions laterally displaced on either side of first and second channel regions within the semiconductor substrate;
FIG. 10 is an alternative processing step subsequent to FIG. 4, in which the first oxide layer over the second substrate region has been removed; and
FIG. 11 is a processing step subsequent to FIG. 10, in which a second gate dielectric layer has been formed over the second region of the semiconductor substrate such that the thickness of the second gate dielectric is less than the thickness of the first gate dielectric.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed descriptions thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
DETAILED DESCRIPTION OF THE DRAWINGS
Turning to the drawings, FIG. 1 shows a semiconductor wafer 100. The wafer 100 comprises a semiconductor substrate 102. The semiconductor substrate 102 includes a first region 104 laterally displaced from a second region 106. Preferably, the semiconductor substrate 102 comprises single crystal silicon. In a presently preferred CMOS embodiment, first region 104 of semiconductor substrate 102 comprises p-type silicon while second region 106 comprises n-type silicon. The p-type and n-type silicon shown in FIG. 1 may reside upon a silicon bulk (not shown in the drawing) preferably comprised of p-type silicon having a resistivity of approximately 12-15 Ω-cm. Semiconductor substrate 102 further includes upper surface 101.
Turning now to FIG. 2, isolation dielectric structure 107 is formed laterally displaced between first region 104 and second region 106 of semiconductor substrate 102. Isolation dielectric 107 is preferably comprised of an oxide such that first region and second region 106 of semiconductor substrate are electrically isolated from one another. In the presently preferred embodiment shown in FIG. 2, isolation dielectric structure 107 comprises a shallow trench isolation structure. Shallow trench isolation structures are formed by etching a trench shaped void into an upper surface of semiconductor substrate 102 such that the trench shaped void extends downward from upper surface 101. Thereafter, the trench shaped void is filled with a dielectric material, preferably a CVD oxide. Thereafter, portions of the dielectric material exterior to the trench are removed with a planarization step such as a chemical-mechanical polish possibly in conjunction with photoresist masking steps and wet and dry etch steps to produce an upper surface of isolation dielectric structure 107 that is substantially coplanar with upper surface 101 of semiconductor substrate 102. It should be understood, however, that alternative isolation structures are available. As an example, the shallow trench isolation structure 107 shown in FIG. 2 may be replaced with the well known local oxidation (LOCOS) structure. LOCOS structures are formed by selectively growing a thermal oxide in an upper surface of semiconductor substrate 102. The selective oxide growth is achieved by patterning a silicon nitride layer over the silicon substrate prior to the thermal oxidation step. While the LOCOS isolation process is well developed, it has the dual disadvantages of (1) producing a non-planar surface and (2) encroaching upon the active areas of the semiconductor substrate with the well-known bird's beak structure.
After the formation of isolation structure 107, first dielectric layer 108 is formed on upper surface 101 of semiconductor substrate 102. First dielectric layer 108 preferably comprises silicon dioxide formed with a conventional thermal oxidation step during which wafer 100 is subjected to a first high temperature, oxygen bearing ambient. The first high temperature, oxygen bearing ambient is preferably between 700 to 1000° C. First dielectric layer 108 can be formed in a batch process tube-type thermal oxidation furnace or, alternatively, with rapid thermal processing techniques. Rapid thermal processing involves rapidly heating a single wafer to a desired temperature and sustaining the wafer at the elevated temperature for a short duration, typically from a few seconds to a few minutes. By minimizing the time during which the wafer is heated, rapid thermal processing minimizes undesirable redistribution of any impurity concentrations that are present in the substrate such as the channel stop implant distribution or the well implant distributions in a CMOS process. When carried out in an oxygen bearing ambient, rapid thermal processing can result in the formation of an SiO2 film, such as first dielectric layer 108, on the wafer surface.
The present invention contemplates an integrated circuit in which a first transistor has a gate oxide thickness that is different than the gate oxide thickness of a second transistor. In one embodiment, the gate oxide thickness of the first transistor formed within first region 104 of semiconductor substrate 102 is greater than the thickness of the gate oxide of the second transistor formed over the second region 106 of semiconductor substrate 102. In this embodiment, first dielectric layer 108 has a thickness of approximately 25-200 Angstroms. Alternatively, the oxide thickness of the transistor formed in first region 104 may be less than the oxide thickness of the transistor formed over second substrate 106. In this embodiment, a thickness of first dielectric 108 is approximately 15-25 Angstroms.
Turning to FIG. 3, a masking layer 110 is formed upon an upper surface of first dielectric layer 108. Preferably, masking layer 110 comprises CVD silicon nitride or polysilicon. In a presently preferred embodiment, the thickness of the masking layer 110 is approximately 100-1000 Angstroms. As an alternative to silicon nitride, masking layer 110 may comprise polycrystalline silicon (polysilicon).
Turning now to FIG. 4, photoresist layer 112 is deposited upon masking layer 110 prior to patterning photoresist layer 112 and masking layer 110. The patterning of photoresist layer 112 and masking layer 110 removes portions of the layers above second region 106 of semiconductor substrate 102. As will be appreciated to those skilled in the art, the patterning of masking layer 110 with either a wet or dry etch process can result in some etching of first dielectric layer 108 such that a residual oxide 113 having a thickness that is less than a thickness of first dielectric layer 108 is left over second region 106 of semiconductor substrate 102. Alternatively, the patterning of masking layer 110 may be performed such all of first dielectric layer 108 over second region 106 of semiconductor substrate 102 is removed. This alternative embodiment is shown in FIG. 10. Turning to FIG. 5, wafer 100 is immersed in a second high temperature, oxygen-bearing ambient 114 such that second dielectric layer 116 is formed over second region 106 of semiconductor substrate 102. High temperature ambient 114 comprises an oxygen bearing species such as O2 or H2 O at a temperature of approximately 700-1000° C. As is well known, an ambient such as high temperature, oxygen-bearing ambient 114 will interact with semiconductor substrate 102 to form a dielectric such as SiO2. As discussed above with respect to FIG. 4 and FIG. 10, second dielectric layer 116 may be grown from no initial oxide as shown in FIG. 10 or may comprise a re-oxidation of residual oxide 113. In the embodiment shown in FIGS. 5 and 6, second dielectric layer 116 has a thickness t2 that is greater than a thickness t1 of first dielectric 108. In an alternative embodiment shown in FIG. 11, second dielectric 116 has a thickness t2 that is less than a thickness t1 of first dielectric 108. In the embodiment shown in FIG. 6 in which second dielectric 116 has a thickness that is greater than the thickness of first dielectric 108, first dielectric thickness t1 is preferably between 15-25 Angstroms while second dielectric thickness t2 has a thickness that is preferably between 30-200 Angstroms. In the embodiments shown in FIG. 11 in which second dielectric thickness t2 is less than first dielectric thickness t1, second dielectric t2 preferably has a thickness that is approximately 15-25 Angstroms and first dielectric thickness t1 is approximately 30-200 Angstroms. Second dielectric layer 116, like first dielectric layer 108 can be formed in a thermal oxidation furnace or in a rapid thermal processing apparatus.
FIGS. 7-9 show processing steps for forming transistors upon the dual oxide thicknesses. Although FIGS. 7-9 disclose an embodiment in which second dielectric 116 has a thickness t2 that is greater than a thickness t1 of first dielectric 108, it is to be understood that the processing steps shown in FIGS. 7-9 are equally applicable to an embodiment in which second dielectric layer 116 is thinner than first dielectric layer 108. Turning to FIG. 7, a conductive gate layer 118 is deposited upon a topography cooperatively defined by an upper surface of first dielectric layer 108 and second dielectric layer 116. Preferably, conductive gate layer 118 comprises CVD polysilicon. Also shown in FIG. 7 are processing steps 119a and 119b in which impurities are introduced into conductive gate layer 118 to reduce the sheet resistivity of conductive gate layer 118.
In an embodiment in which conductive gate layer 118 comprises CVD polysilicon, processing steps 119a and 119b result in a sheet resistivity of conductive gate layer 118 that is less than approximately 500 Ω/sq. Processing steps 119a and 119b may comprise separate processing steps such that the portion of conductive gate layer 118 over first substrate region 104 is selectively doped with respect to a portion of conductive gate layer 118 over second substrate region 106. In a CMOS embodiment, for example, it is preferable to introduce p-type impurities into the gate structures of the p-channel devices and to introduce n-type impurities into the gate structures of the n-channel devices to minimize the asymmetry in the work functions of the p-channel and n-channel devices. Because the most prevalent p-type impurity is boron, which tends to diffuse through silicon dioxide at a much faster rate than either arsenic or phosphorus (the common n-type impurities), it is also desirable to utilize a slightly thicker gate oxide for the p-channel devices to minimize the threshold shifting of the p-channel devices due to boron diffusion through the gate dielectric. Accordingly, one embodiment of processing steps 119a and 119b contemplates a first implant 119a in which n-type impurities such as phosphorus or arsenic are introduced, preferably through an ion implantation, into conductive gate layer 118 over first region 104 of semiconductor substrate 102. This embodiment further contemplates a second processing step 119b in which p-type impurities such as boron are introduced into conductive layer 118 over second region 106 of semiconductor substrate 102. The selective introduction of the impurities into their corresponding regions of conductive layer 118 is carried out through the use of a conventional photoresist masking step.
It will be further understood, that in a CMOS embodiment in which second dielectric layer 116 is thinner than first dielectric layer 108, the p-type impurity will be introduced into the region of conductive gate layer 118 over first region 104 of semiconductor substrate 102. In other words, it is understood that the boron doping of conductive gate layer 118 is carried out over the thicker gate dielectric to minimize the threshold shifting as described above. It should also be understood that the present invention can be implemented in an NMOS process to produce an integrated circuit in which selected n-channel devices have a thinner gate oxide than the remaining n-channel devices. In such an embodiment, processing steps 119a and 119b may comprise a single processing step such as a single implant or a diffusion step subsequent to the deposition of first conductive layer 118.
FIG. 8 shows a processing step subsequent to FIG. 7 in which first and second gate structures 120a and 120b are formed over first and second channel regions 121a and 121b, respectively, of semiconductor substrate 102. The formation of gate structures 120 is preferably accomplished with a photolithography step, and more preferably in conjunction with a dry etch process such that gate structures 120 are formed with substantially vertical sidewalls 123a and 123b. Turning to FIG. 9, first and second transistors 122a and 122b are formed over first substrate region 104 and second substrate region 106, respectively of semiconductor substrate 102. Following the formation of gate structures 120, transistors 122 are formed by introducing impurities into source/drain regions 124 within an upper region of the semiconductor substrate 102. Source/drain regions 124 are laterally displaced on either side of channel regions 121 within semiconductor substrate 102. In the preferred embodiment shown in FIG. 9, source/drain regions 124 comprise LDD regions 126 and heavily implanted regions 130.
LDD regions 126 are used to reduce the maximum electric field within semiconductor substrate 102 to minimize the occurrence of hot electron injection. LDD regions 126 are formed by implanting a first concentration of a first impurity type into an upper region of semiconductor substrate 102. Thereafter, LDD spacers 128 are formed on sidewalls 123 of gate structures 120. The formation of spacer structures 128 comprises depositing a conformal dielectric layer such as a CVD oxide formed from a TEOS source and anisotropically etching the dielectric layer with minimum overetch such that the dielectric layer is just cleared from the planar regions of the topography. After spacer structures 128 have been formed, impurities are introduced into heavily doped regions 130 through a subsequent implantation step.
Generally, the peak doping concentration of LDD 126 is less than the peak doping concentration of heavily doped region 130. In a CMOS embodiment of the present invention, it will be appreciated that in the p-channel device which is formed over the thicker gate dielectric (second transistor 122b in the embodiment shown), LDD regions 126b and heavily doped regions 130b comprise a concentration of boron ions while the LDD region 126a and heavily doped region 130a of the n-channel transistor 122a formed over the thinner gate oxide comprise a concentration of n-type ions such as phosphorus or arsenic. The selective introduction of impurities into first substrate region 104 versus second substrate region 106 can be accomplished through the use of conventional photoresist masking steps. In an embodiment of the present invention in which first transistor 122a and second transistor 122b are both n-channel devices, it will be appreciated that the formation of source/drain regions 124a and 124b can be accomplished simultaneously.
Thus, FIG. 9 depicts an integrated circuit 132 comprising first transistor 122a and second transistor 122b. First transistor 122a is formed within first substrate region 104 of semiconductor substrate 102 and includes a first dielectric layer 108 having a first dielectric thickness t1. Integrated circuit 132 further comprises second transistor 122b. Second transistor 122b comprises second dielectric layer 116 having a second dielectric thickness t2. In the embodiment shown, second dielectric thickness t2 is greater than first dielectric thickness t1. In this manner, the capacitance, Cox1, of first transistor 122a is substantially greater than the capacitance, Cox2, of second transistor 122b. First transistor 122a will, therefore, demonstrate a higher saturated drain current IDsat than a similarly dimensioned second transistor 122b. In a CMOS embodiment, first transistor 122a is an n-channel device such that first gate structure 120a comprises heavily doped n-type polysilicon and first source/drain regions 124a comprise an ion concentration of phosphorus or arsenic. In the CMOS embodiment, second transistor 122b is a p-channel device in which second gate structure 120b comprises heavily doped p-type polysilicon and second source/drain regions 124b comprise ion concentrations of boron. The thicker gate oxide of second dielectric layer 116 is used in conjunction with the p-channel transistor 122b to prevent boron diffusion through second dielectric 116 while permitting the optimization of n-channel transistor 122a by allowing a thinner first dielectric layer 108.
It will, therefore, be appreciated to those skilled in the art having the benefit of this disclosure that this invention is capable of producing an integrated circuit including dual oxide thicknesses for selective formation of high performance transistors within the integrated circuit. Furthermore, it is to be understood that the form of the invention shown and described is to be taken as presently preferred embodiments. Various modifications and changes may be made to each and every processing step as would be obvious to a person skilled in the art having the benefit of this disclosure. It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims (17)

What is claimed is:
1. A semiconductor process, comprising:
providing a semiconductor wafer, wherein said semiconductor wafer includes a semiconductor substrate comprising a first region and a second region laterally displaced from said first region;
forming a first dielectric layer on an upper surface of said semiconductor substrate, wherein said first dielectric layer has a first thickness;
depositing a masking layer on said first dielectric layer;
patterning said masking layer to expose said first dielectric layer above said second region of said semiconductor substrate;
while retaining at least a portion of said first dielectric layer above the entirety of said second region, subjecting said semiconductor wafer to an oxygen bearing ambient at a temperature of approximately 700 to 1000° C. such that a second dielectric layer is formed over said second region of said semiconductor substrate, wherein said second layer has a second thickness, and further wherein said second thickness is unequal to said first thickness;
removing said masking layer from said upper surface of said first dielectric layer, subsequent to said subjecting;
forming a first gate structure and a second gate structure on upper surfaces of said first dielectric layer and said second dielectric layer respectively; and
introducing impurities into a first and second pair of source/drain regions laterally displaced on either side of said first and second channel regions respectively whereby first and second transistors are formed, wherein said first dielectric layer serves as a gate dielectric for said first transistor and said second dielectric layer serves as a gate dielectric for said second transistor.
2. The process of claim 1 wherein said first region of said semiconductor substrate comprises p-type silicon and said second region of said semiconductor substrate comprises n-type silicon.
3. The process of claim 1, wherein the step of forming said first dielectric layer comprises subjecting said semiconductor wafer to an additional oxygen bearing ambient at a temperature of approximately 700 to 1000° C. such that said first dielectric layer comprises a thermal oxide.
4. The process of claim 3, wherein said first thickness is approximately 15 to 25 angstroms.
5. The process of claim 1 wherein the step of depositing said masking layer comprises chemical vapor depositing a material selected from the group consisting of silicon nitride and polysilicon on said first dielectric layer.
6. The process of claim 1 wherein the step of patterning said masking layer, comprises:
depositing a photoresist layer on said masking layer;
selectively exposing said photoresist layer to an energy source to form exposed regions of said photoresist layer; and
developing said photoresist layer such that said exposed regions of said photoresist layer are removed.
7. The process of claim 1, wherein the step of forming said first and second gate structures comprises:
chemical vapor depositing a polysilicon layer on a surface cooperatively defined by an upper surface of said first dielectric layer and an upper surface of said second dielectric layer;
patterning said polysilicon layer to remove portions of said polysilicon layer exterior to a first channel region and a second channel region of said semiconductor substrate such that said first and second gate structures are formed; and
doping said first and second gate structures with impurities such that a sheet resistivity of said first and second gate structures is less than 500 Ω/sq.
8. The process of claim 7, wherein the step of doping said first and second gate structures comprises doping said first gate structure with a first impurity chosen from the group consisting of phosphorous and arsenic and doping said second gate structure with boron.
9. The process of claim 1, further comprising, prior to the step of forming said first dielectric layer, forming an isolation dielectric structure laterally disposed between said first region and said second region of said semiconductor substrate.
10. The process of claim 9, wherein the step of forming said isolation dielectric structure comprises:
etching a trench shaped void into said semiconductor substrate, said trench-shaped void extending downward from said upper surface of said semiconductor substrate;
filling said trench shaped void with a fill dielectric layer; and
removing said fill dielectric layer from regions exterior to said trench shaped dielectric such that an upper surface of said fill dielectric layer is substantially planar with said upper surface of said semiconductor substrate.
11. The process of claim 1 wherein said the step of introducing impurities into said source/drain regions comprises implanting ions selected from the group consisting of boron, arsenic, and phosphorous.
12. The process of claim 11 wherein the step of implanting ions comprises implanting ions selected from the group consisting of phosphorous and arsenic into said first pair of source/drain regions and implanting boron ions into said second pair of source/drain regions.
13. The process of claim 1, wherein said first thickness is less than said second thickness.
14. The process of claim 1, wherein said first thickness is greater than said second thickness.
15. The method of claim 5, wherein said chemical vapor depositing a material comprises chemical vapor depositing polysilicon.
16. A semiconductor process, comprising:
providing a semiconductor wafer, wherein said semiconductor wafer includes a semiconductor substrate comprising a first region and a second region laterally displaced from said first region;
forming a first dielectric layer on an upper surface of said semiconductor substrate, wherein said first dielectric layer has a first thickness;
depositing a polysilicon masking layer on said first dielectric layer;
patterning said masking layer to expose said first dielectric layer above said second region of said semiconductor substrate;
while retaining at least a portion of said first dielectric layer above the entirety of said second region, subjecting said semiconductor wafer to an oxygen bearing ambient at a temperature of approximately 700 to 1000° C. such that a second dielectric layer is formed over said second region of said semiconductor substrate, wherein said second layer has a second thickness, and further wherein said second thickness is unequal to said first thickness;
removing said masking layer from said upper surface of said first dielectric layer;
forming a first gate structure and a second gate structure on upper surfaces of said first dielectric layer and said second dielectric layer respectively; and
introducing impurities into a first and second pair of source/drain regions laterally displaced on either side of said first and second channel regions respectively whereby first and second transistors are formed, wherein said first dielectric layer serves as a gate dielectric for said first transistor and said second dielectric layer serves as a gate dielectric for said second transistor.
17. The process of claim 16, wherein said first region of said semiconductor substrate comprises p-type silicon and said second region of said semiconductor substrate comprises n-type silicon.
US08/702,270 1996-08-23 1996-08-23 Dual gate oxide thickness integrated circuit and process for making same Expired - Lifetime US6033943A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US08/702,270 US6033943A (en) 1996-08-23 1996-08-23 Dual gate oxide thickness integrated circuit and process for making same
PCT/US1997/009424 WO1998008253A1 (en) 1996-08-23 1997-05-29 Dual gate oxide thickness integrated circuit and process for making same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/702,270 US6033943A (en) 1996-08-23 1996-08-23 Dual gate oxide thickness integrated circuit and process for making same

Publications (1)

Publication Number Publication Date
US6033943A true US6033943A (en) 2000-03-07

Family

ID=24820519

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/702,270 Expired - Lifetime US6033943A (en) 1996-08-23 1996-08-23 Dual gate oxide thickness integrated circuit and process for making same

Country Status (2)

Country Link
US (1) US6033943A (en)
WO (1) WO1998008253A1 (en)

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6171911B1 (en) * 1999-09-13 2001-01-09 Taiwan Semiconductor Manufacturing Company Method for forming dual gate oxides on integrated circuits with advanced logic devices
US6207584B1 (en) * 2000-01-05 2001-03-27 International Business Machines Corp. High dielectric constant material deposition to achieve high capacitance
US6248618B1 (en) * 1999-10-12 2001-06-19 Chartered Semiconductor Manufacturing Ltd. Method of fabrication of dual gate oxides for CMOS devices
US6297082B1 (en) * 1999-08-25 2001-10-02 United Microelectronics Corp. Method of fabricating a MOS transistor with local channel ion implantation regions
US6403425B1 (en) 2001-11-27 2002-06-11 Chartered Semiconductor Manufacturing Ltd. Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide
US6417052B1 (en) * 1999-11-15 2002-07-09 Hitachi, Ltd. Fabrication process for semiconductor device
US6468851B1 (en) 2002-01-02 2002-10-22 Chartered Semiconductor Manufacturing Ltd. Method of fabricating CMOS device with dual gate electrode
US6500715B2 (en) * 1996-04-08 2002-12-31 Hitachi, Ltd. Method of forming a CMOS structure having gate insulation films of different thicknesses
US6573192B1 (en) * 2000-09-21 2003-06-03 Infineon Technologies Ag Dual thickness gate oxide fabrication method using plasma surface treatment
US6579766B1 (en) 2002-02-15 2003-06-17 Infineon Technologies Ag Dual gate oxide process without critical resist and without N2 implant
US6597046B1 (en) * 1998-11-24 2003-07-22 Intel Corporation Integrated circuit with multiple gate dielectric structures
WO2003073491A1 (en) * 2002-02-20 2003-09-04 Advanced Micro Devices, Inc. Method of forming layers of oxide of different thicknesses on a surface of a substrate
US20030201474A1 (en) * 2001-04-24 2003-10-30 Hynix Semiconductor Inc. Semiconductor device with multiple source/drain regions of different depths
US6661044B2 (en) * 2001-10-22 2003-12-09 Winbond Electronics Corp. Method of manufacturing MOSEFT and structure thereof
US6661061B1 (en) * 1996-08-19 2003-12-09 Advanced Micro Devices, Inc. Integrated circuit with differing gate oxide thickness
US6703278B2 (en) 2002-02-20 2004-03-09 Advanced Micro Devices, Inc. Method of forming layers of oxide on a surface of a substrate
US20040048483A1 (en) * 2000-06-19 2004-03-11 Heon Lee Method to etch poly Si gate stacks with raised STI structure
US6759699B1 (en) * 2003-04-22 2004-07-06 Taiwan Semiconductor Manufacturing Company Storage element and SRAM cell structures using vertical FETS controlled by adjacent junction bias through shallow trench isolation
US20040135198A1 (en) * 2002-07-23 2004-07-15 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same, nonvolatile semiconductor memory and method of fabricating the same, and electronic apparatus including nonvolatile semiconductor memory
US20040224451A1 (en) * 2003-05-08 2004-11-11 International Business Machines Corporation Dual gate material process for cmos technologies
US20050118764A1 (en) * 2003-11-28 2005-06-02 Chou Anthony I. Forming gate oxides having multiple thicknesses
US20060003511A1 (en) * 2004-07-01 2006-01-05 Linear Technology Corporation Method of fabricating a semiconductor device with multiple gate oxide thicknesses
US20060281289A1 (en) * 2005-06-09 2006-12-14 Samsung Electronics Co., Ltd. Method of forming polycide layer and method of manufacturing semiconductor device having polycide layer
US20070187764A1 (en) * 2001-11-15 2007-08-16 Ryoichi Furukawa Method for manufacturing semiconductor integrated circuit device
CN100446273C (en) * 2005-12-13 2008-12-24 上海华虹Nec电子有限公司 MOS field effect pipe and its production
US20100025770A1 (en) * 2008-07-31 2010-02-04 Martin Trentzsch Gate dielectrics of different thickness in pmos and nmos transistors
US20110117709A1 (en) * 2009-11-13 2011-05-19 Vanguard International Semiconductor Corporation Semiconductor device fabricating method
US20160172190A1 (en) * 2014-12-15 2016-06-16 United Microelectronics Corp. Gate oxide formation process
US20170025536A1 (en) * 2015-07-24 2017-01-26 Taiwan Semiconductor Manufacturing Company Semiconductor device and manufacturing method thereof
US10361289B1 (en) 2018-03-22 2019-07-23 Globalfoundries Inc. Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same
US11094792B2 (en) * 2019-04-11 2021-08-17 Mosel Vitelic Inc. Manufacturing method of split gate structure and split gate structure
US20210375666A1 (en) * 2020-05-28 2021-12-02 Taiwan Semiconductor Manufacturing Company Limited Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same
US11239346B2 (en) * 2019-05-30 2022-02-01 Texas Instruments Incorporated Split gate memory cell fabrication and system
US20220223412A1 (en) * 2021-01-14 2022-07-14 Changxin Memory Technologies, Inc. Method for preparing semiconductor structure and semiconductor structure
US20220285403A1 (en) * 2020-04-17 2022-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer with devices having different top layer thicknesses

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6096664A (en) * 1998-08-06 2000-08-01 Siemens Aktiengesellschaft Method of manufacturing semiconductor structures including a pair of MOSFETs
US20160284595A1 (en) * 2015-03-26 2016-09-29 Qualcomm Incorporated Selective analog and radio frequency performance modification

Citations (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4098618A (en) * 1977-06-03 1978-07-04 International Business Machines Corporation Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation
DE3032608A1 (en) * 1979-09-05 1981-03-12 Mitsubishi Denki K.K., Tokyo Semiconductor device prodn. by ion implantation and oxidn. - to give thick and thin oxide films simultaneously on defect and untreated zones
US4352117A (en) * 1980-06-02 1982-09-28 International Business Machines Corporation Electron source
US4551910A (en) * 1984-11-27 1985-11-12 Intel Corporation MOS Isolation processing
US4578128A (en) * 1984-12-03 1986-03-25 Ncr Corporation Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants
EP0216246A1 (en) * 1985-09-09 1987-04-01 Fujitsu Limited Semiconductor programmable memory device
US4682407A (en) * 1986-01-21 1987-07-28 Motorola, Inc. Means and method for stabilizing polycrystalline semiconductor layers
US4707721A (en) * 1986-02-20 1987-11-17 Texas Instruments Incorporated Passivated dual dielectric gate system and method for fabricating same
US4729009A (en) * 1986-02-20 1988-03-01 Texas Instruments Incorporated Gate dielectric including undoped amorphous silicon
US4743566A (en) * 1985-06-14 1988-05-10 U.S. Philips Corp. Method of manufacturing a semiconductor device, in which a silicon slice is locally provided with field oxide with a channel stopper
US4774197A (en) * 1986-06-17 1988-09-27 Advanced Micro Devices, Inc. Method of improving silicon dioxide
US4776925A (en) * 1987-04-30 1988-10-11 The Trustees Of Columbia University In The City Of New York Method of forming dielectric thin films on silicon by low energy ion beam bombardment
US4808261A (en) * 1986-04-29 1989-02-28 Sgs Microelettronica S.P.A. Fabrication process for EPROM cells with oxide-nitride-oxide dielectric
US4851257A (en) * 1987-03-13 1989-07-25 Harris Corporation Process for the fabrication of a vertical contact
US4866002A (en) * 1985-11-26 1989-09-12 Fuji Photo Film Co., Ltd. Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof
US4897365A (en) * 1984-10-23 1990-01-30 Sgs Microelecttronica S.P.A. Reduced-beak planox process for the formation of integrated electronic components
US5043780A (en) * 1990-01-03 1991-08-27 Micron Technology, Inc. DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance
US5066995A (en) * 1987-03-13 1991-11-19 Harris Corporation Double level conductor structure
US5082797A (en) * 1991-01-22 1992-01-21 Micron Technology, Inc. Method of making stacked textured container capacitor
US5102832A (en) * 1991-02-11 1992-04-07 Micron Technology, Inc. Methods for texturizing polysilicon
US5138411A (en) * 1991-05-06 1992-08-11 Micron Technology, Inc. Anodized polysilicon layer lower capacitor plate of a dram to increase capacitance
US5141882A (en) * 1989-04-05 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor
US5158463A (en) * 1991-04-09 1992-10-27 Samsung Electronics Co., Ltd. Method of manufacturing both low and high voltage BiCMOS transistors in the same semiconductor substrate
US5172200A (en) * 1990-01-12 1992-12-15 Mitsubishi Denki Kabushiki Kaisha MOS memory device having a LDD structure and a visor-like insulating layer
US5191509A (en) * 1991-12-11 1993-03-02 International Business Machines Corporation Textured polysilicon stacked trench capacitor
EP0532260A1 (en) * 1991-09-13 1993-03-17 STMicroelectronics, Inc. A method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby
US5208176A (en) * 1990-01-16 1993-05-04 Micron Technology, Inc. Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization
US5254489A (en) * 1990-10-18 1993-10-19 Nec Corporation Method of manufacturing semiconductor device by forming first and second oxide films by use of nitridation
JPH05283678A (en) * 1992-03-31 1993-10-29 Matsushita Electron Corp Mis-type semiconductor device
US5296411A (en) * 1993-04-28 1994-03-22 Advanced Micro Devices, Inc. Method for achieving an ultra-reliable thin oxide using a nitrogen anneal
US5308787A (en) * 1993-10-22 1994-05-03 United Microelectronics Corporation Uniform field oxidation for locos isolation
US5316981A (en) * 1992-10-09 1994-05-31 Advanced Micro Devices, Inc. Method for achieving a high quality thin oxide using a sacrificial oxide anneal
US5316965A (en) * 1993-07-29 1994-05-31 Digital Equipment Corporation Method of decreasing the field oxide etch rate in isolation technology
US5330935A (en) * 1990-10-24 1994-07-19 International Business Machines Corporation Low temperature plasma oxidation process
US5330920A (en) * 1993-06-15 1994-07-19 Digital Equipment Corporation Method of controlling gate oxide thickness in the fabrication of semiconductor devices
US5340764A (en) * 1993-02-19 1994-08-23 Atmel Corporation Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer
US5358894A (en) * 1992-02-06 1994-10-25 Micron Technology, Inc. Oxidation enhancement in narrow masked field regions of a semiconductor wafer
US5362685A (en) * 1992-10-29 1994-11-08 Advanced Micro Devices, Inc. Method for achieving a high quality thin oxide in integrated circuit devices
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit
US5391907A (en) * 1991-04-15 1995-02-21 Gold Star Electron Co., Ltd. Semiconductor device with buried inverse T-type field region
US5432114A (en) * 1994-10-24 1995-07-11 Analog Devices, Inc. Process for integration of gate dielectric layers having different parameters in an IGFET integrated circuit
JPH07297298A (en) * 1994-04-21 1995-11-10 Lg Semicon Co Ltd Manufacture of memory device
US5480828A (en) * 1994-09-30 1996-01-02 Taiwan Semiconductor Manufacturing Corp. Ltd. Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process
US5498577A (en) * 1994-07-26 1996-03-12 Advanced Micro Devices, Inc. Method for fabricating thin oxides for a semiconductor technology
US5502009A (en) * 1995-02-16 1996-03-26 United Microelectronics Corp. Method for fabricating gate oxide layers of different thicknesses
US5576570A (en) * 1993-08-19 1996-11-19 Sony Corporation Semiconductor device having CMOS circuit
US5576266A (en) * 1996-02-12 1996-11-19 Eastman Kodak Company Magnetic layer in dye-donor element for thermal dye transfer
US5591681A (en) * 1994-06-03 1997-01-07 Advanced Micro Devices, Inc. Method for achieving a highly reliable oxide film
US5604159A (en) * 1994-01-31 1997-02-18 Motorola, Inc. Method of making a contact structure
US5637520A (en) * 1993-02-11 1997-06-10 Sgs-Thomson Microelectronics S.R.L. Process for fabricating integrated devices including flash-EEPROM memories and transistors
US5672521A (en) * 1995-11-21 1997-09-30 Advanced Micro Devices, Inc. Method of forming multiple gate oxide thicknesses on a wafer substrate
US5683925A (en) * 1996-06-13 1997-11-04 Waferscale Integration Inc. Manufacturing method for ROM array with minimal band-to-band tunneling
US5786256A (en) * 1996-07-19 1998-07-28 Advanced Micro Devices, Inc. Method of reducing MOS transistor gate beyond photolithographically patterned dimension
US5789305A (en) * 1997-01-27 1998-08-04 Chartered Semiconductor Manufacturing Ltd. Locos with bird's beak suppression by a nitrogen implantation
US5851893A (en) * 1997-07-18 1998-12-22 Advanced Micro Devices, Inc. Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection
US5861347A (en) * 1997-07-03 1999-01-19 Motorola Inc. Method for forming a high voltage gate dielectric for use in integrated circuit
US5872376A (en) * 1997-03-06 1999-02-16 Advanced Micro Devices, Inc. Oxide formation technique using thin film silicon deposition
US5882993A (en) * 1996-08-19 1999-03-16 Advanced Micro Devices, Inc. Integrated circuit with differing gate oxide thickness and process for making same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01183844A (en) * 1988-01-19 1989-07-21 Toshiba Corp Semiconductor device

Patent Citations (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4098618A (en) * 1977-06-03 1978-07-04 International Business Machines Corporation Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation
DE3032608A1 (en) * 1979-09-05 1981-03-12 Mitsubishi Denki K.K., Tokyo Semiconductor device prodn. by ion implantation and oxidn. - to give thick and thin oxide films simultaneously on defect and untreated zones
US4352117A (en) * 1980-06-02 1982-09-28 International Business Machines Corporation Electron source
US4897365A (en) * 1984-10-23 1990-01-30 Sgs Microelecttronica S.P.A. Reduced-beak planox process for the formation of integrated electronic components
US4551910A (en) * 1984-11-27 1985-11-12 Intel Corporation MOS Isolation processing
US4578128A (en) * 1984-12-03 1986-03-25 Ncr Corporation Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants
US4743566A (en) * 1985-06-14 1988-05-10 U.S. Philips Corp. Method of manufacturing a semiconductor device, in which a silicon slice is locally provided with field oxide with a channel stopper
EP0216246A1 (en) * 1985-09-09 1987-04-01 Fujitsu Limited Semiconductor programmable memory device
US4922319A (en) * 1985-09-09 1990-05-01 Fujitsu Limited Semiconductor programmable memory device
US4866002A (en) * 1985-11-26 1989-09-12 Fuji Photo Film Co., Ltd. Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof
US4682407A (en) * 1986-01-21 1987-07-28 Motorola, Inc. Means and method for stabilizing polycrystalline semiconductor layers
US4729009A (en) * 1986-02-20 1988-03-01 Texas Instruments Incorporated Gate dielectric including undoped amorphous silicon
US4707721A (en) * 1986-02-20 1987-11-17 Texas Instruments Incorporated Passivated dual dielectric gate system and method for fabricating same
US4808261A (en) * 1986-04-29 1989-02-28 Sgs Microelettronica S.P.A. Fabrication process for EPROM cells with oxide-nitride-oxide dielectric
US4774197A (en) * 1986-06-17 1988-09-27 Advanced Micro Devices, Inc. Method of improving silicon dioxide
US4851257A (en) * 1987-03-13 1989-07-25 Harris Corporation Process for the fabrication of a vertical contact
US5066995A (en) * 1987-03-13 1991-11-19 Harris Corporation Double level conductor structure
US4776925A (en) * 1987-04-30 1988-10-11 The Trustees Of Columbia University In The City Of New York Method of forming dielectric thin films on silicon by low energy ion beam bombardment
US5141882A (en) * 1989-04-05 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor
US5043780A (en) * 1990-01-03 1991-08-27 Micron Technology, Inc. DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance
US5172200A (en) * 1990-01-12 1992-12-15 Mitsubishi Denki Kabushiki Kaisha MOS memory device having a LDD structure and a visor-like insulating layer
US5208176A (en) * 1990-01-16 1993-05-04 Micron Technology, Inc. Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization
US5254489A (en) * 1990-10-18 1993-10-19 Nec Corporation Method of manufacturing semiconductor device by forming first and second oxide films by use of nitridation
US5330935A (en) * 1990-10-24 1994-07-19 International Business Machines Corporation Low temperature plasma oxidation process
US5082797A (en) * 1991-01-22 1992-01-21 Micron Technology, Inc. Method of making stacked textured container capacitor
US5102832A (en) * 1991-02-11 1992-04-07 Micron Technology, Inc. Methods for texturizing polysilicon
US5158463A (en) * 1991-04-09 1992-10-27 Samsung Electronics Co., Ltd. Method of manufacturing both low and high voltage BiCMOS transistors in the same semiconductor substrate
US5391907A (en) * 1991-04-15 1995-02-21 Gold Star Electron Co., Ltd. Semiconductor device with buried inverse T-type field region
US5138411A (en) * 1991-05-06 1992-08-11 Micron Technology, Inc. Anodized polysilicon layer lower capacitor plate of a dram to increase capacitance
EP0532260A1 (en) * 1991-09-13 1993-03-17 STMicroelectronics, Inc. A method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby
US5250456A (en) * 1991-09-13 1993-10-05 Sgs-Thomson Microelectronics, Inc. Method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby
US5191509A (en) * 1991-12-11 1993-03-02 International Business Machines Corporation Textured polysilicon stacked trench capacitor
US5358894A (en) * 1992-02-06 1994-10-25 Micron Technology, Inc. Oxidation enhancement in narrow masked field regions of a semiconductor wafer
JPH05283678A (en) * 1992-03-31 1993-10-29 Matsushita Electron Corp Mis-type semiconductor device
US5316981A (en) * 1992-10-09 1994-05-31 Advanced Micro Devices, Inc. Method for achieving a high quality thin oxide using a sacrificial oxide anneal
US5362685A (en) * 1992-10-29 1994-11-08 Advanced Micro Devices, Inc. Method for achieving a high quality thin oxide in integrated circuit devices
US5637520A (en) * 1993-02-11 1997-06-10 Sgs-Thomson Microelectronics S.R.L. Process for fabricating integrated devices including flash-EEPROM memories and transistors
US5340764A (en) * 1993-02-19 1994-08-23 Atmel Corporation Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer
US5296411A (en) * 1993-04-28 1994-03-22 Advanced Micro Devices, Inc. Method for achieving an ultra-reliable thin oxide using a nitrogen anneal
US5330920A (en) * 1993-06-15 1994-07-19 Digital Equipment Corporation Method of controlling gate oxide thickness in the fabrication of semiconductor devices
US5316965A (en) * 1993-07-29 1994-05-31 Digital Equipment Corporation Method of decreasing the field oxide etch rate in isolation technology
US5576570A (en) * 1993-08-19 1996-11-19 Sony Corporation Semiconductor device having CMOS circuit
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit
US5308787A (en) * 1993-10-22 1994-05-03 United Microelectronics Corporation Uniform field oxidation for locos isolation
US5604159A (en) * 1994-01-31 1997-02-18 Motorola, Inc. Method of making a contact structure
JPH07297298A (en) * 1994-04-21 1995-11-10 Lg Semicon Co Ltd Manufacture of memory device
US5576226A (en) * 1994-04-21 1996-11-19 Lg Semicon Co., Ltd. Method of fabricating memory device using a halogen implant
US5591681A (en) * 1994-06-03 1997-01-07 Advanced Micro Devices, Inc. Method for achieving a highly reliable oxide film
US5498577A (en) * 1994-07-26 1996-03-12 Advanced Micro Devices, Inc. Method for fabricating thin oxides for a semiconductor technology
US5480828A (en) * 1994-09-30 1996-01-02 Taiwan Semiconductor Manufacturing Corp. Ltd. Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process
US5432114A (en) * 1994-10-24 1995-07-11 Analog Devices, Inc. Process for integration of gate dielectric layers having different parameters in an IGFET integrated circuit
US5502009A (en) * 1995-02-16 1996-03-26 United Microelectronics Corp. Method for fabricating gate oxide layers of different thicknesses
US5672521A (en) * 1995-11-21 1997-09-30 Advanced Micro Devices, Inc. Method of forming multiple gate oxide thicknesses on a wafer substrate
US5576266A (en) * 1996-02-12 1996-11-19 Eastman Kodak Company Magnetic layer in dye-donor element for thermal dye transfer
US5683925A (en) * 1996-06-13 1997-11-04 Waferscale Integration Inc. Manufacturing method for ROM array with minimal band-to-band tunneling
US5786256A (en) * 1996-07-19 1998-07-28 Advanced Micro Devices, Inc. Method of reducing MOS transistor gate beyond photolithographically patterned dimension
US5882993A (en) * 1996-08-19 1999-03-16 Advanced Micro Devices, Inc. Integrated circuit with differing gate oxide thickness and process for making same
US5789305A (en) * 1997-01-27 1998-08-04 Chartered Semiconductor Manufacturing Ltd. Locos with bird's beak suppression by a nitrogen implantation
US5872376A (en) * 1997-03-06 1999-02-16 Advanced Micro Devices, Inc. Oxide formation technique using thin film silicon deposition
US5861347A (en) * 1997-07-03 1999-01-19 Motorola Inc. Method for forming a high voltage gate dielectric for use in integrated circuit
US5851893A (en) * 1997-07-18 1998-12-22 Advanced Micro Devices, Inc. Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection

Non-Patent Citations (32)

* Cited by examiner, † Cited by third party
Title
Abbas et al., "Improvement of the Gate-Region Integrity in FET Devices," IBM Technical Disclosure Bulletin, vol. 14, No. 11, Apr. 1972, pp. 3348-3350.
Abbas et al., Improvement of the Gate Region Integrity in FET Devices, IBM Technical Disclosure Bulletin , vol. 14, No. 11, Apr. 1972, pp. 3348 3350. *
Ahn, J. et al., "High Quality Ultrathin Gate Dieletrics Formation by Thermal Oxidation of Si in N20," J. Electrochem. Soc. V. 139, No. 9, Sep. 1991, pp. L39-41.
Ahn, J. et al., High Quality Ultrathin Gate Dieletrics Formation by Thermal Oxidation of Si in N20, J. Electrochem. Soc. V. 139, No. 9, Sep. 1991, pp. L39 41. *
Cheung, "Plasma Immersion Ion Implantation for ULSI Processing," Trends & Applications, 1991, pp. 811-820.
Cheung, Plasma Immersion Ion Implantation for ULSI Processing, Trends & Applications , 1991, pp. 811 820. *
Doyle, B. et al., "Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing," IEEE Electron Device Letters, vol. 16, No. 7, Jul. 1995, pp. 301-302.
Doyle, B. et al., Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing, IEEE Electron Device Letters, vol. 16, No. 7, Jul. 1995, pp. 301 302. *
International Search Report for International Application No. PCT/US 97/09424 mailed Sep. 16, 1997. *
Kuroi, et al "Novel NICE Structure For High Reliability and High Performance 0.25 micron Dual Gate CMOS", IEDM, pgs. 325-328. No month/y.
Kuroi, et al Novel NICE Structure For High Reliability and High Performance 0.25 micron Dual Gate CMOS , IEDM, pgs. 325 328. No month/y. *
Molle, P. et al., "Nitrogen Implantation for Local Oxidation of Silicon," Nuclear Instruments & Methods in Physics Research, Section--B: Beam Interactions with Materials and Atoms, vol. B55, No. 1 / 04, Apr. 2, 1991, pp. 860-865.
Molle, P. et al., Nitrogen Implantation for Local Oxidation of Silicon, Nuclear Instruments & Methods in Physics Research, Section B: Beam Interactions with Materials and Atoms, vol. B55, No. 1 / 04, Apr. 2, 1991, pp. 860 865. *
Naito et al., "Effect of Bottom Oxide on the Integrity of Interpolysilicon Ultrathin ONO Films," Journal of the Electrochemical Society, vol. 137, No. 2, Feb. 1, 1990, pp. 635-638.
Naito et al., Effect of Bottom Oxide on the Integrity of Interpolysilicon Ultrathin ONO Films, Journal of the Electrochemical Society , vol. 137, No. 2, Feb. 1, 1990, pp. 635 638. *
Patent Abstracts of Japan, Publication No. 01183844; Publication Date: Jul. 21, 1989; Application Date: Jan. 19, 1988; Application No. 63008901. *
Philipossian, A. et al., "Kinetics of Oxide Growth During Reoxidation of Lightly Nitrided Oxides," J. Electrochem. Soc. V. 139, No. 9, Sep. 1992, pp. L82-3.
Philipossian, A. et al., Kinetics of Oxide Growth During Reoxidation of Lightly Nitrided Oxides, J. Electrochem. Soc. V. 139, No. 9, Sep. 1992, pp. L82 3. *
Schott, K. et al., "Blocking of Silicon Oxidation by Low-Dose Nitrogen Implantation," Applied Physics A. Solids and Surfaces, vol. A45, No. 1, Jan. 1, 1988, pp. 73-76.
Schott, K. et al., Blocking of Silicon Oxidation by Low Dose Nitrogen Implantation, Applied Physics A. Solids and Surfaces, vol. A45, No. 1, Jan. 1, 1988, pp. 73 76. *
Wolf et al., "Silicon Processing for the VLSI Era, vol. 1, Process Technology," p. 321.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1, Process Technology, p. 321. *
Wolf, "Silicon Processing For the VLSI Era", vol. 1, Process Technology, pp. 198-218. 1986 No Month.
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, p.p. 429 446, No Month Given 1986. *
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, p.p. 429-446, No Month Given 1986.
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 3: The Submicron MOSFET, Sunset Beach, CA, p.p. 429 446, No Month Given 1995. *
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 3: The Submicron MOSFET, Sunset Beach, CA, p.p. 429-446, No Month Given 1995.
Wolf, Silicon Processing For the VLSI Era , vol. 1, Process Technology, pp. 198 218. 1986 No Month. *
Wolfe, S., "Silicon Processing For The VLSI Era," vol. 3, The Submicron Mosfet, Lattice Press, CA, 1995, pp. 495-496.
Wolfe, S., Silicon Processing For The VLSI Era, vol. 3, The Submicron Mosfet, Lattice Press, CA, 1995, pp. 495 496. *
Yoshikawa et al., "An EPROM Cell Structure for EPLD's Compatible with Single Poly-Si Gate Process," IEEE Transactions on Electron Devices, vol. 37, No. 3, Mar. 1990, pp. 675-679.
Yoshikawa et al., An EPROM Cell Structure for EPLD s Compatible with Single Poly Si Gate Process, IEEE Transactions on Electron Devices, vol. 37, No. 3, Mar. 1990, pp. 675 679. *

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110012180A1 (en) * 1996-04-08 2011-01-20 Renesas Technology Corp. Method of forming a cmos structure having gate insulation films of different thicknesses
US7781814B2 (en) 1996-04-08 2010-08-24 Renesas Technology Corp. Method of forming a CMOS structure having gate insulation films of different thicknesses
US9111909B2 (en) 1996-04-08 2015-08-18 Tessera Advanced Technologies, Inc. Method of forming a CMOS structure having gate insulation films of different thicknesses
US7427791B2 (en) 1996-04-08 2008-09-23 Renesas Technology Corporation Method of forming a CMOS structure having gate insulation films of different thicknesses
US20050190608A1 (en) * 1996-04-08 2005-09-01 Renesas Technology Corp. Method of forming a CMOS structure having gate insulation films of different thicknesses
US20080297220A1 (en) * 1996-04-08 2008-12-04 Nozomu Matsuzaki Method of forming a CMOS structure having gate insulation films of different thicknesses
US8674419B2 (en) 1996-04-08 2014-03-18 Renesas Electronics Corporation Method of forming a CMOS structure having gate insulation films of different thicknesses
US6500715B2 (en) * 1996-04-08 2002-12-31 Hitachi, Ltd. Method of forming a CMOS structure having gate insulation films of different thicknesses
US20030052371A1 (en) * 1996-04-08 2003-03-20 Hitachi, Ltd. Semiconductor integrated circuit device
US6661061B1 (en) * 1996-08-19 2003-12-09 Advanced Micro Devices, Inc. Integrated circuit with differing gate oxide thickness
US6597046B1 (en) * 1998-11-24 2003-07-22 Intel Corporation Integrated circuit with multiple gate dielectric structures
US6297082B1 (en) * 1999-08-25 2001-10-02 United Microelectronics Corp. Method of fabricating a MOS transistor with local channel ion implantation regions
US6171911B1 (en) * 1999-09-13 2001-01-09 Taiwan Semiconductor Manufacturing Company Method for forming dual gate oxides on integrated circuits with advanced logic devices
US6248618B1 (en) * 1999-10-12 2001-06-19 Chartered Semiconductor Manufacturing Ltd. Method of fabrication of dual gate oxides for CMOS devices
US6417052B1 (en) * 1999-11-15 2002-07-09 Hitachi, Ltd. Fabrication process for semiconductor device
US6207584B1 (en) * 2000-01-05 2001-03-27 International Business Machines Corp. High dielectric constant material deposition to achieve high capacitance
US7153781B2 (en) * 2000-06-19 2006-12-26 Infineon Technologies Ag Method to etch poly Si gate stacks with raised STI structure
US20040048483A1 (en) * 2000-06-19 2004-03-11 Heon Lee Method to etch poly Si gate stacks with raised STI structure
US6573192B1 (en) * 2000-09-21 2003-06-03 Infineon Technologies Ag Dual thickness gate oxide fabrication method using plasma surface treatment
US20030201474A1 (en) * 2001-04-24 2003-10-30 Hynix Semiconductor Inc. Semiconductor device with multiple source/drain regions of different depths
US6661044B2 (en) * 2001-10-22 2003-12-09 Winbond Electronics Corp. Method of manufacturing MOSEFT and structure thereof
US7655993B2 (en) * 2001-11-15 2010-02-02 Renesas Technology Corporation Method for manufacturing semiconductor integrated circuit device
US20070187764A1 (en) * 2001-11-15 2007-08-16 Ryoichi Furukawa Method for manufacturing semiconductor integrated circuit device
US6403425B1 (en) 2001-11-27 2002-06-11 Chartered Semiconductor Manufacturing Ltd. Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide
US6468851B1 (en) 2002-01-02 2002-10-22 Chartered Semiconductor Manufacturing Ltd. Method of fabricating CMOS device with dual gate electrode
US6579766B1 (en) 2002-02-15 2003-06-17 Infineon Technologies Ag Dual gate oxide process without critical resist and without N2 implant
CN1315162C (en) * 2002-02-20 2007-05-09 先进微装置公司 Method of forming layers of oxide of different thicknesses on a surface of a substrate
WO2003073491A1 (en) * 2002-02-20 2003-09-04 Advanced Micro Devices, Inc. Method of forming layers of oxide of different thicknesses on a surface of a substrate
US6703278B2 (en) 2002-02-20 2004-03-09 Advanced Micro Devices, Inc. Method of forming layers of oxide on a surface of a substrate
US20040135198A1 (en) * 2002-07-23 2004-07-15 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same, nonvolatile semiconductor memory and method of fabricating the same, and electronic apparatus including nonvolatile semiconductor memory
US6759699B1 (en) * 2003-04-22 2004-07-06 Taiwan Semiconductor Manufacturing Company Storage element and SRAM cell structures using vertical FETS controlled by adjacent junction bias through shallow trench isolation
US20040224451A1 (en) * 2003-05-08 2004-11-11 International Business Machines Corporation Dual gate material process for cmos technologies
US20050118764A1 (en) * 2003-11-28 2005-06-02 Chou Anthony I. Forming gate oxides having multiple thicknesses
US7160771B2 (en) 2003-11-28 2007-01-09 International Business Machines Corporation Forming gate oxides having multiple thicknesses
US20060003511A1 (en) * 2004-07-01 2006-01-05 Linear Technology Corporation Method of fabricating a semiconductor device with multiple gate oxide thicknesses
US7402480B2 (en) 2004-07-01 2008-07-22 Linear Technology Corporation Method of fabricating a semiconductor device with multiple gate oxide thicknesses
US20060281289A1 (en) * 2005-06-09 2006-12-14 Samsung Electronics Co., Ltd. Method of forming polycide layer and method of manufacturing semiconductor device having polycide layer
CN100446273C (en) * 2005-12-13 2008-12-24 上海华虹Nec电子有限公司 MOS field effect pipe and its production
US20100025770A1 (en) * 2008-07-31 2010-02-04 Martin Trentzsch Gate dielectrics of different thickness in pmos and nmos transistors
US7994037B2 (en) * 2008-07-31 2011-08-09 Advanced Micro Devices, Inc. Gate dielectrics of different thickness in PMOS and NMOS transistors
US20110117709A1 (en) * 2009-11-13 2011-05-19 Vanguard International Semiconductor Corporation Semiconductor device fabricating method
US8067283B2 (en) * 2009-11-13 2011-11-29 Vanguard International Semiconductor Corporation Semiconductor device fabricating method
US20160172190A1 (en) * 2014-12-15 2016-06-16 United Microelectronics Corp. Gate oxide formation process
US20170025536A1 (en) * 2015-07-24 2017-01-26 Taiwan Semiconductor Manufacturing Company Semiconductor device and manufacturing method thereof
US20210328058A1 (en) * 2015-07-24 2021-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US20190006517A1 (en) * 2015-07-24 2019-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US11735662B2 (en) * 2015-07-24 2023-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US11049970B2 (en) * 2015-07-24 2021-06-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10050147B2 (en) * 2015-07-24 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10361289B1 (en) 2018-03-22 2019-07-23 Globalfoundries Inc. Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same
TWI739087B (en) * 2019-04-11 2021-09-11 台灣茂矽電子股份有限公司 Manufacturing method of split gate structure and split gate structure
US11094792B2 (en) * 2019-04-11 2021-08-17 Mosel Vitelic Inc. Manufacturing method of split gate structure and split gate structure
US11239346B2 (en) * 2019-05-30 2022-02-01 Texas Instruments Incorporated Split gate memory cell fabrication and system
US20220285403A1 (en) * 2020-04-17 2022-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer with devices having different top layer thicknesses
US11887987B2 (en) * 2020-04-17 2024-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer with devices having different top layer thicknesses
US20210375666A1 (en) * 2020-05-28 2021-12-02 Taiwan Semiconductor Manufacturing Company Limited Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same
US11398403B2 (en) * 2020-05-28 2022-07-26 Taiwan Semiconductor Manufacturing Company Limited Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same
US11817345B2 (en) 2020-05-28 2023-11-14 Taiwan Semiconductor Manufacturing Company Limited Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same
US20220223412A1 (en) * 2021-01-14 2022-07-14 Changxin Memory Technologies, Inc. Method for preparing semiconductor structure and semiconductor structure

Also Published As

Publication number Publication date
WO1998008253A1 (en) 1998-02-26

Similar Documents

Publication Publication Date Title
US6033943A (en) Dual gate oxide thickness integrated circuit and process for making same
US5882993A (en) Integrated circuit with differing gate oxide thickness and process for making same
JP3604818B2 (en) Method for manufacturing semiconductor device
US5406111A (en) Protection device for an intergrated circuit and method of formation
US5926703A (en) LDD device having a high concentration region under the channel
EP1192655B1 (en) Method for eliminating stress induced dislocation in cmos devices
US6624032B2 (en) Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US5102816A (en) Staircase sidewall spacer for improved source/drain architecture
US20030211713A1 (en) Semiconductor device and method for manufacturing
US6083778A (en) Localized semiconductor substrate for multilevel for transistors
US5849621A (en) Method and structure for isolating semiconductor devices after transistor formation
JP2000340791A (en) Manufacturing method of semiconductor device
US6033958A (en) Method of fabricating dual voltage MOS transistors
EP1026738A2 (en) Novel mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps
US6724049B2 (en) SOI semiconductor device with insulating film having different properties relative to the buried insulating film
US6074904A (en) Method and structure for isolating semiconductor devices after transistor formation
US6075258A (en) Elevated transistor fabrication technique
US7598549B2 (en) Semiconductor device having a silicon layer in a gate electrode
JP2001156290A (en) Semiconductor device
US6261885B1 (en) Method for forming integrated circuit gate conductors from dual layers of polysilicon
US5950082A (en) Transistor formation for multilevel transistors
US5804497A (en) Selectively doped channel region for increased IDsat and method for making same
US6110788A (en) Surface channel MOS transistors, methods for making the same, and semiconductor devices containing the same
US6245638B1 (en) Trench and gate dielectric formation for semiconductor devices
US5994190A (en) Semiconductor device with impurity layer as channel stopper immediately under silicon oxide film

Legal Events

Date Code Title Description
AS Assignment

Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GARDNER, MARK I.;REEL/FRAME:008199/0763

Effective date: 19960823

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12