US6011306A - Semiconductor device and method for fabricating same - Google Patents
Semiconductor device and method for fabricating same Download PDFInfo
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- US6011306A US6011306A US09/157,474 US15747498A US6011306A US 6011306 A US6011306 A US 6011306A US 15747498 A US15747498 A US 15747498A US 6011306 A US6011306 A US 6011306A
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- semiconductor chip
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Definitions
- the invention relates to a semiconductor device and a method for fabricating the same, and especially to a molded ball grid array (BGA) semiconductor device of a lead on chip (LOC) type and a method for fabricating the same.
- BGA molded ball grid array
- LOC lead on chip
- leads are stuck to a semiconductor chip via insulative adhesive tapes, and the leads and pads formed on the semiconductor chip are connected by bonding wires.
- the semiconductor chip is miniaturized or provided with many pins, spacing between the adjacent leads become narrow, so that it becomes impossible to connect the leads and the pads by a wire-bonding apparatus. Accordingly, it is extremely desirable to develop a semiconductor device, in which the leads and pads can be connected without using the leads, which have been an obstacle to miniaturization of the semiconductor device.
- a semiconductor device comprises:
- a method for fabricating a semiconductor device comprises the steps of:
- FIG. 1 is a perspective view for showing a conventional semiconductor device
- FIGS. 2A and 2B are respectively a top view and a cross-sectional view for explaining the first preferred embodiment of the invention
- FIGS. 3A to 3E are side views for explaining a process of fabrication of an insulative resin shaft used in the first preferred embodiment of the invention
- FIGS. 4A and 4B are respectively a top view and a cross-sectional view for explaining a process of fabrication of the first preferred embodiment of the invention
- FIGS. 5A to 5D are cross-sectional views for explaining a process of fabrication of the first preferred embodiment of the invention.
- FIGS. 6A to 6B are respectively a perspective view and a cross-sectional view for explaining the second preferred embodiment of the innovation.
- FIG.7 is a cross-sectional view for explaining the third preferred embodiment of the invention.
- a lead 19 is joined with the top surface of a semiconductor chip 1 by an adhesive insulative tape 17, and both the ends of a bonding wire 3 are bonded with a pad 2 formed on the semiconductor chip 1 and the end of the lead 19.
- solder balls 10 are set on the leads 19, and the semiconductor device is completed in this way.
- the bonding wire 3 starts from the pad 2, is bent upward, and its end is bonded with the lead 19 obliquely.
- FIGS. 2A and 2B respectively show the top and cross-sectional views of a semiconductor device according to the first preferred embodiment of the invention, in which an insulative resin shaft is used instead of leads, the surface of the insulative resin shaft 7 is covered with plural solder-plated layers (conductive parts) 8 with a low melting point.
- a semiconductor chip 1 is joined with the island 5 by silver paste 6, which serves as an adhesive.
- a bonding wire 3 starting from a pad 2 formed on the semiconductor chip 1 is joined with the solder-plated layer 8, and thereafter the semiconductor chip 1 is sealed by sealing resin 4.
- a solder ball 10 is set on a portion corresponding to the solder-plated layer 8 on the insulative shaft 7 and joined therewith.
- the insulative resin shaft with the solder-plated layers is fabricated as shown in cross-sectional views FIGS. 3A to 3E, which are shown following the sequence of process.
- insulative resin is formed into a shaft 7 with cylindrical configuration.
- the cross-section of the shaft may be square.
- resists 11 are applied to parts, where the solder-plated layers are not to be formed.
- Pd which serves as base metal of plating, is coated on base metal-coated parts 12 by evaporation.
- the solder-plated layer 13 are formed by electroless plating, and as shown in FIG. 3E, the resists 11 are removed. Then, the solder-plated layers 13 are left behind.
- suspending leads 14 which are on both the sides (left and light) of an island 5 of a lead frame 20, are respectively provided with supporting plates 15, which are vertical to the suspending leads 14.
- a semiconductor chip 1 is joined with the island 5 by silver paste 6.
- a bonding wire 3 is from a pad 2 on the semiconductor chip 1 to the supporting plate 15 via the insulative resin shaft 7, and the pad 2 and a solder-plated layer 13 are connected with the bonding wire 3.
- the bonding wire 3 is cut at the edge of the solder-plated layer 13, and the supporting plate 15 is taken off.
- the semiconductor chip 1 having the bonding wires 3 connected therewith is sealed by resin 4, the solder ball 10 is set at a portion corresponding to the solder-plated layer 13 and joined therewith.
- the embodiment of the invention it becomes possible to interconnect the pad 2 with the solder ball 10 via bonding wire 3, without using the lead, by making the insulative resin shaft 7 provided with the solder-plated layers 13 lie between the pad 2 and the solder ball 10, and miniaturize the semiconductor device.
- FIGS. 6A and 6B respectively show a perspective view and a cross-sectional view of the second preferred embodiment of the invention, in which an insulative tape is used instead of the leads.
- an insulative tape 17 to which conductive tape pads 18 are stuck, is used instead of the insulative resin shaft 7 shown in FIGS. 2A and 2B.
- the insulative tape 17 is stuck to the semiconductor chip 1, and a bonding wire 3 is bond with the tape pad 18 stuck to the insulative tape 17.
- a remaining part of a bonding wire 3 is formed into a pin 16, which is nearly vertical to the tape pad 18.
- the semiconductor chip 1 having the pins 16 and the bonding wires 3 is sealed by sealing resin 4 except the circumferences of the pins 16.
- solder balls 10 are set at portions corresponding to the pins 16, and joined therewith.
- FIG. 7 shows a cross-sectional view of the third preferred embodiment of the invention, in which a tape pad is used instead of the leads.
- pins 16, which are shown in FIGS. 6A and 6B, are not used, and solder balls 10 are directly set on a tape bad 18 and joined therewith.
- the second and third embodiments it becomes possible to directly connect the bonding wire 3 with the solder ball 10, which serves as an external terminal, without using the lead, by making the insulating tape 17 provided with the tape pad 18 lie between the pad and the solder ball, and miniaturize the semiconductor device.
- the degree of freedom of bonding increases and the semiconductor device can be miniaturized.
Abstract
Description
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP9256988A JP2954108B2 (en) | 1997-09-22 | 1997-09-22 | Semiconductor device and manufacturing method thereof |
JP9-256988 | 1997-09-22 |
Publications (1)
Publication Number | Publication Date |
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US6011306A true US6011306A (en) | 2000-01-04 |
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Application Number | Title | Priority Date | Filing Date |
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US09/157,474 Expired - Fee Related US6011306A (en) | 1997-09-22 | 1998-09-21 | Semiconductor device and method for fabricating same |
Country Status (3)
Country | Link |
---|---|
US (1) | US6011306A (en) |
JP (1) | JP2954108B2 (en) |
CN (1) | CN1213176A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6303992B1 (en) * | 1999-07-06 | 2001-10-16 | Visteon Global Technologies, Inc. | Interposer for mounting semiconductor dice on substrates |
US6888256B2 (en) * | 2001-10-31 | 2005-05-03 | Infineon Technologies Ag | Compliant relief wafer level packaging |
US11373979B2 (en) * | 2003-08-29 | 2022-06-28 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
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US5521435A (en) * | 1993-12-13 | 1996-05-28 | Fujitsu Limited | Semiconductor device and a fabrication process thereof |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
US5674785A (en) * | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
US5770479A (en) * | 1996-01-11 | 1998-06-23 | Micron Technology, Inc. | Bonding support for leads-over-chip process |
US5834339A (en) * | 1996-03-07 | 1998-11-10 | Tessera, Inc. | Methods for providing void-free layers for semiconductor assemblies |
-
1997
- 1997-09-22 JP JP9256988A patent/JP2954108B2/en not_active Expired - Fee Related
-
1998
- 1998-09-21 US US09/157,474 patent/US6011306A/en not_active Expired - Fee Related
- 1998-09-22 CN CN98120024A patent/CN1213176A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
US5521435A (en) * | 1993-12-13 | 1996-05-28 | Fujitsu Limited | Semiconductor device and a fabrication process thereof |
US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
US5674785A (en) * | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
US5770479A (en) * | 1996-01-11 | 1998-06-23 | Micron Technology, Inc. | Bonding support for leads-over-chip process |
US5834339A (en) * | 1996-03-07 | 1998-11-10 | Tessera, Inc. | Methods for providing void-free layers for semiconductor assemblies |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6303992B1 (en) * | 1999-07-06 | 2001-10-16 | Visteon Global Technologies, Inc. | Interposer for mounting semiconductor dice on substrates |
US6888256B2 (en) * | 2001-10-31 | 2005-05-03 | Infineon Technologies Ag | Compliant relief wafer level packaging |
US11373979B2 (en) * | 2003-08-29 | 2022-06-28 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
US11887970B2 (en) | 2003-08-29 | 2024-01-30 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
Also Published As
Publication number | Publication date |
---|---|
CN1213176A (en) | 1999-04-07 |
JP2954108B2 (en) | 1999-09-27 |
JPH1197472A (en) | 1999-04-09 |
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