Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5963788 A
Publication typeGrant
Application numberUS 08/974,586
Publication date5 Oct 1999
Filing date19 Nov 1997
Priority date6 Sep 1995
Fee statusPaid
Publication number08974586, 974586, US 5963788 A, US 5963788A, US-A-5963788, US5963788 A, US5963788A
InventorsCarole C. Barron, James G. Fleming, Stephen Montague
Original AssigneeSandia Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for integrating microelectromechanical devices with electronic circuitry
US 5963788 A
Abstract
A method is disclosed for integrating one or more microelectromechanical (MEM) devices with electronic circuitry on a common substrate. The MEM device can be fabricated within a substrate cavity and encapsulated with a sacrificial material. This allows the MEM device to be annealed and the substrate planarized prior to forming electronic circuitry on the substrate using a series of standard processing steps. After fabrication of the electronic circuitry, the electronic circuitry can be protected by a two-ply protection layer of titanium nitride (TiN) and tungsten (W) during an etch release process whereby the MEM device is released for operation by etching away a portion of a sacrificial material (e.g. silicon dioxide or a silicate glass) that encapsulates the MEM device. The etch release process is preferably performed using a mixture of hydrofluoric acid (HF) and hydrochloric acid (HCI) which reduces the time for releasing the MEM device compared to use of a buffered oxide etchant. After release of the MEM device, the TiN:W protection layer can be removed with a peroxide-based etchant without damaging the electronic circuitry.
Images(13)
Previous page
Next page
Claims(43)
What is claimed is:
1. A method for integrating a microelectromechanical (MEM) device with electronic circuitry on a substrate comprising steps for:
(a) etching a cavity within a first portion of the substrate;
(b) fabricating the MEM device within the cavity, and filling the cavity with a sacrificial material;
(c) fabricating the electronic circuitry comprising a plurality of transistors within a second portion of the substrate proximate to the first portion, and interconnecting the electronic circuitry to the MEM device;
(d) protecting the electronic circuitry by depositing a layer of tungsten to blanket the second portion of the substrate and cover the electronic circuitry; and
(e) releasing the MEM device for operation thereof by removing at least a portion of the sacrificial material filling the cavity by etching the sacrificial material with a first wet etchant which does not substantially remove the layer of tungsten protecting the electronic circuitry.
2. The method of claim 1 wherein the step for etching the cavity within the first portion of the substrate comprises etching the cavity into at least one semiconductor layer formed on the substrate.
3. The method of claim 1 wherein the substrate comprises silicon.
4. The method of claim 1 wherein the step for fabricating the MEM device within the cavity comprises steps for depositing and patterning by etching at least one layer of a micromachineable material selected from the group consisting of polysilicon, silicon dioxide, silicon nitride, silicate glass, metals and metal alloys.
5. The method of claim 4 wherein the step for filling the cavity with a sacrificial material comprises depositing a sacrificial material selected from the group consisting of silicon dioxide and a silicate glass within the cavity to fill the cavity.
6. The method of claim 1 wherein the step for fabricating the MEM device includes a step for annealing the MEM device, thereby relieving stress therein.
7. The method of claim 1 further including a step for planarizing the substrate prior to the step for fabricating the electronic circuitry.
8. The method of claim 1 wherein the step for fabricating the electronic circuitry comprises steps for fabricating a plurality of transistors selected from the group consisting of CMOS transistors, BiCMOS transistors, and bipolar transistors.
9. The method of claim 1 wherein the step for depositing the layer of tungsten comprises depositing the layer of tungsten by chemical vapor deposition.
10. The method of claim 1 wherein the layer of tungsten is deposited to a layer thickness of about 0.1-1 microns.
11. The method of claim 1 wherein the step for protecting the electronic circuitry further comprises a step for depositing an adhesion layer over the second portion of the substrate prior to the step for depositing the layer of tungsten.
12. The method of claim 11 wherein the adhesion layer comprises a layer of titanium nitride.
13. The method of claim 12 wherein the titanium nitride layer is deposited to a layer thickness of about 50 nanometers.
14. The method of claim 12 further including a step for removing the layers of tungsten and titanium nitride after the step for releasing the MEM device.
15. The method of claim 1 wherein the first wet etchant comprises hydrofluoric acid (HF).
16. The method of claim 15 wherein the first wet etchant further comprises hydrochloric acid (HCI).
17. The method of claim 1 further including a step for removing the layer of tungsten after the step for releasing the MEM device.
18. The method of claim 17 wherein the step for removing the layer of tungsten comprises exposing the layer of tungsten to a second wet etchant having a chemical composition different from the chemical composition of the first wet etchant.
19. The method of claim 18 wherein the second wet etchant comprises hydrogen peroxide.
20. A method for integrating a microelectromechanical (MEM) device with electronic circuitry on a substrate comprising steps for:
(a) fabricating the MEM device at least in part within or from a cavity formed in a first portion of the substrate and encapsulating the MEM device with a sacrificial material;
(b) fabricating the electronic circuitry in a second portion of the substrate, and interconnecting the electronic circuitry to the MEM device;
(c) depositing layers of titanium nitride and tungsten over the electronic circuitry for protecting the electronic circuitry from exposure to a first wet etchant comprising, at least in part, hydrofluoric acid; and
(d) releasing the MEM device for operation by etching away at least a portion of the sacrificial material encapsulating the MEM device with the first wet etchant.
21. The method of claim 20 wherein the substrate comprises silicon.
22. The method of claim 20 further including a step for annealing the encapsulated MEM device for relieving stress therein.
23. The method of claim 20 further including a step for planarizing the substrate prior to the step for fabricating the electronic circuitry.
24. The method of claim 20 wherein the step for fabricating the MEM device comprises steps for etching a cavity into the substrate, depositing a plurality of material layers into the cavity, and patterning by etching at least one of the material layers.
25. The method of claim 24 wherein the material layers comprise micromachineable materials selected from the group consisting of polysilicon, silicon dioxide, silicon nitride, silicate glass, metals and metal alloys.
26. The method of claim 20 wherein the step for fabricating the MEM device comprises steps for etching a cavity into a semiconductor layer formed above the substrate, depositing a plurality of material layers into the cavity, and patterning by etching at least one of the material layers.
27. The method of claim 26 wherein the material layers comprise micromachineable materials selected from the group consisting of polysilicon, silicon dioxide, silicon nitride, silicate glass, metals and metal alloys.
28. The method of claim 20 wherein the sacrificial material comprises silicon dioxide or a silicate glass.
29. The method of claim 20 wherein the step for fabricating the electronic circuitry comprises steps for fabricating a plurality of transistors selected from the group consisting of CMOS transistors, BiCMOS transistors, and bipolar transistors.
30. The method of claim 20 wherein the step for depositing layers of titanium nitride and tungsten over the electronic circuitry comprises depositing the layers of titanium nitride and tungsten by deposition processes selected from the group consisting of sputter deposition and chemical vapor deposition.
31. The method of claim 20 wherein the layer of titanium nitride is about 50 nanometers thick.
32. The method of claim 20 wherein the layer of tungsten is about 0.1-1 microns thick.
33. The method of claim 20 further including a step for removing the layers of titanium nitride and tungsten after the step for releasing the encapsulated MEM device.
34. The method of claim 33 wherein the step for removing the layers of titanium nitride and tungsten comprises exposing the layers of titanium nitride and tungsten to a second wet etchant having a chemical composition different from the chemical composition of the first wet etchant.
35. The method of claim 34 wherein the second wet etchant comprises, at least in part, hydrogen peroxide.
36. A method for integrating a microelectromechanical (MEM) device with electronic circuitry on a substrate comprising steps for:
(a) fabricating the MEM device at least in part within or from a cavity formed in a first portion of the substrate and encapsulating the MEM device with a sacrificial material;
(b) planarizing the substrate to remove any of the sacrificial material extending upward beyond the cavity thereby providing a substantially planar upper surface for the substrate;
(c) fabricating the electronic circuitry in a second portion of the substrate, and interconnecting the electronic circuitry to the MEM device;
(d) protecting the electronic circuitry by depositing layers of titanium nitride and tungsten over the electronic circuitry in the second portion of the substrate;
(e) releasing the MEM device by exposing the MEM device to a first wet etching comprising, at least in part, hydrofluoric acid for sufficient time to remove a portion of the sacrificial material encapsulating the MEM device; and
(f) removing the deposited layers of titanium nitride and tungsten protecting the electronic circuitry.
37. The method of claim 36 wherein the step for fabricating the MEM device comprises steps for etching a cavity into the substrate, depositing a plurality of material layers into the cavity, and patterning by etching at least one of the material layers.
38. The method of claim 37 wherein the substrate comprises silicon, and the material layers comprise micromachineable materials selected from the group consisting of polysilicon, silicon dioxide, silicon nitride, silicate glass, metals and metal alloys.
39. The method of claim 36 further including a step for annealing the MEM device for relieving stress therein.
40. The method of claim 36 wherein the electronic circuitry comprises a plurality of transistors.
41. The method of claim 40 wherein the transistors are selected from the group consisting of CMOS transistors, BiCMOS transistors, and bipolar transistors.
42. The method of claim 36 wherein the step for removing the deposited layers of titanium nitride and tungsten comprises exposing the layers of titanium nitride and tungsten to a second wet etchant having a chemical composition different from the chemical composition of the first wet etchant.
43. The method of claim 42 wherein the second wet etchant comprises, at least in part, hydrogen peroxide.
Description
GOVERNMENT RIGHTS

This invention was made with Government support under Contract No. DE-AC04-94AL85000 awarded by the U.S. Department of Energy. The Government has certain rights in the invention.

DETAILED DESCRIPTION OF THE INVENTION

The fabrication method of the present invention combines processes for fabricating one or more microelectromechanical (MEM) devices with processes for fabricating electronic circuitry in a mutually compatible manner. The electronic circuitry can comprise complementary metal-oxide semiconductor (CMOS) transistors, bipolar complementary metal-oxide semiconductor (BiCMOS) transistors, or bipolar transistors. The integration of the MEM devices with electronic circuitry provides added functionality for driving and control of microactuators (i.e. MEM devices providing some form of actuation, including linear and rotary motors, gears, levers, linkages and the like) and provides a means for amplifying and/or processing (including compensation, linearization, and control) of sensory signals generated by microsensors (i.e. MEM devices responding to some form of external applied stimuli, including accelerometers, pressure sensors, flow sensors, chemical sensors, optical sensors, resonant oscillators and the like). Such integration provides advantages in terms of increased functionality and sensitivity, and reduced size and cost as compared to MEM devices being formed on a separate chip from the electronic circuitry.

Referring to FIG. 1, there is shown a schematic cross-section representation of an example of an integrated device 10 comprising at least one microelectromechanical (MEM) device 12 fabricated on a first portion of a common substrate 14 and electrically connected to electronic circuitry 16 fabricated on a second portion on the substrate proximate to the first portion. In the example of FIG. 1, the first portion of the substrate 14 lies below the bracket and label "Microelectromechanical Device 12"; whereas the second portion lies below the bracket and label "Electronic Circuitry 16".

The process steps for forming such an integrated device 10 in the example of FIG. 1 are shown in FIGS. 2-13, and described hereinafter. Although the example of the MEM device 12 is described in FIGS. 1-13 as being formed within a cavity 20, it will be understood by those skilled in the art that, in some embodiments of the present invention, the completed MEM device 12 can extend upward beyond the cavity 20. In particular, for forming pressure sensors, a moveable pressure sensing diaphragm can be formed over the cavity 20 to cover and seal the cavity 20, with polysilicon piezoresistors then being formed above the pressure diaphragm for measuring changes in pressure or vacuum. Thus, although the MEM device 12 is generally described as being located within the cavity 20, in some instances, the cavity 20 itself can form a part of the MEM device 12, as in the case of a pressure sensor.

In FIG. 2, a substrate 14 is provided for formation of the integrated device 10. The substrate 14 preferably comprises a monocrystalline silicon wafer or a portion thereof. The substrate 14 can be undoped, or n- or p-type doped depending on a predetermined set of standard processes (and including design rules) to be used for forming the electronic circuitry 16. As an example, an n-type doped substrate 14 can be preferred for forming electronic circuitry 16 by a set of standard CMOS process steps having 2-micron (μm) design rules (i.e. a 2-μm minimum feature size). As another example, a p-type doped substrate can be preferred for forming electronic circuitry 16 by another set of standard CMOS processing steps having 0.5-μm design rules. The substrate 14 can further include one or more semiconductor layers formed or epitaxially deposited thereon (including doped layers) with a total layer thickness of about 2-10 μm or more for providing a smooth low-defect-density device surface 18 for formation of the electronic circuitry 16. (A buried doped epitaxial layer can be provided for forming BiCMOS or bipolar transistors for forming the electronic circuitry 16.)

In FIG. 2, one or more open cavities 20 are etched into the device surface 18 of the substrate at predetermined locations (i.e. the first portion of the substrate) wherein each MEM device 12 is to be fabricated. The size of each cavity 20 including its length, width and depth, will in general depend on the particular type of MEM device 12 to be formed. The length and width can each be on the order of one millimeter, for example, and the depth can be in the range of about 2-20 μm.

Each cavity 20 is preferably formed by a bulk micromachining process after providing a patterned first masking layer (e.g. about 500 nanometers of a silicate glass deposited from the decomposition of tetraethylortho silicate, also termed TEOS, that has been densified by heating to a high temperature for a specified period of time) covering the device surface 18 with openings at the locations of each cavity to be formed. Each cavity 20 is then etched into the substrate using a wet and/or dry etching process. A preferred etching process uses an anisotropic wet etchant such as potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH) or ethylenediamine pyrocatechol (EDP) to form one or more cavities 20 that can be, for example, about 2-20 μm or more deep with a substantially planar bottom surface and sloping inner sidewalls formed by selective etching along preferred (111) crystallographic planes as shown in FIG. 2. The use of an anisotropic etchant can be advantageous for providing improved optical access to the bottom surface of each cavity thereby providing an increased latitude for subsequent photolithography steps for forming elements of the MEM structure within each cavity (including providing alignment marks on the bottom surface of the cavity). After formation of one or more cavities on the substrate, the patterned first masking layer can be removed with a wet etchant comprising HF.

In FIG. 3, a first silicon nitride layer 22 is deposited to blanket the device surface 18 and each cavity 20 after first forming a thin blanket layer of a thermal oxide (approximately 60 nanometers of silicon dioxide formed by a thermal diffusion process) to protect the bare silicon from exposure to the first silicon nitride layer 22. The first silicon nitride layer 22 can be up to about 200-300 nanometers thick, and is preferably formed by a low-pressure chemical vapor deposition (CVD) process that produces low residual stress in the first silicon nitride layer 22. The portion of the first silicon nitride layer 22 extending above the device surface 18 can later be used as a stop for a chemical-mechanical polishing process for planarizing a top side of the substrate; and the remainder of the first silicon nitride layer 22 covering the inner surfaces of each cavity 20 serves as a dielectric isolation layer, and also as an etch stop during an etching step for releasing the MEM device 12 after fabrication of the electronic circuitry.

In FIG. 4, one or more MEM devices 12 are formed within each cavity 20 in the first portion of the substrate 14, with the MEM devices 12 preferably being located substantially below the device surface 18 of the substrate 14. Formation of the MEM devices can include surface and bulk micromachining processes as known to the art. In surface micromachining processes, for example, one or more thin films (up to a few microns thick) of micromachineable materials such as polysilicon, silicon nitride (also termed nitride), silicon dioxide (also termed oxide), metals (e.g. tungsten, gold, copper, platinum, nickel, palladium), metal alloys (including metal silicides) and the like can be deposited within the cavity through patterned masking layers and anisotropically etched to form the MEM devices 12. One or more sacrificial layers comprising a sacrificial material such as silicon dioxide or one or more silicate glasses as can be deposited by a CVD process. After formation of the electronic circuitry 16 on the second portion of the substrate 14, the sacrificial material can be removed, at least in part, from each cavity 20 for releasing the MEM devices 12 for movement or operation. Bulk micromachining processes including LIGA (a German acronym taken from words referring to lithography, electroplating and injection molding) can be used to form MEM devices 12 having larger vertical dimensions (up to 300 μm or more), and with minimum feature sizes down to about 2 μm.

FIG. 4 shows an example of a MEM device 12 comprising a first-deposited polysilicon layer 24 that is preferably doped (e.g. by an ion implantation and/or thermal diffusion step, or in-situ by chemical vapor deposition) and patterned for forming a voltage reference plane and for providing electrical interconnections between elements of the MEM device. In FIG. 4, additional polysilicon layers can be deposited and patterned by any conventional method to form one or more fixed support beams 26, moveable support beams (not shown), electrical interconnection studs 28, or the like having predetermined forms or shapes depending on a particular MEM device 12 to be fabricated. A single additional polysilicon layer can be provided above the first polysilicon layer 24 when simple MEM devices 12 such as accelerometers based on capacitively-coupled cantilevered beams are to be formed according to the present invention.

For more complex MEM devices, however, further polysilicon layers are generally required. For example, a preferred process for forming complex, interconnected, interactive, microactuated MEM devices 12 having springs, linkages, mass elements, joints and the like generally requires the deposition and patterning of three additional layers of polysilicon above the first polysilicon layer 24, with each of the polysilicon layers being separated by a sacrificial layer (e.g. a thin oxide or silicate glass layer) and/or by a friction-reduction nitride layer (e.g. for forming bearing surfaces for moveable elements such as gears, rotors, levers, linkages etc.). This preferred three-layer process is advantageous for mechanically interconnecting elements of a MEM device 12 by hard linkages for actuation, or for coupling mechanical energy via micromachined gears, levers, linkages or the like. Furthermore, since each polysilicon layer can be selectively doped for use as an electrical conductor, this preferred three-layer process provides additional flexibility for electrical interconnections and/or electrodes. The additional polysilicon layers can be deposited, at least in part, through one or more patterned sacrificial layers 30 for defining a shape of the MEM elements, and for forming anchor portions for mechanical and electrical connection to the first-deposited polysilicon layer 24.

In FIG. 5, after formation of the MEM devices 12 (with the polysilicon layers being formed into their final shapes to define elements of the MEM devices), one or more additional sacrificial layers 32 (comprising the same or different sacrificial materials such as silicon dioxide or silicate glasses that can be later removed by selective etching) can be deposited to fill the cavity 20 and completely bury or encapsulate the MEM devices 12. The steps for depositing the sacrificial material to fill the cavity 20 provide for protection of the MEM devices 12 within the cavity and/or for planarization of the cavity 20 and the substrate 14. The sacrificial layers 30 and 32 can be grown or deposited in a conventional manner (e.g. by CVD wherein an oxide or silicate glass layer-forming gas is decomposed to form the layers 30; or by plasma-enhanced CVD, also termed PECVD, wherein applied rf power is provided to assist the decomposition for deposition at a low temperature of about 600 or less), with each layer thickness being tailored to particular requirements of the MEM devices 12 being formed.

The additional sacrificial layers 32 are preferably deposited so as to extend upward beyond the device surface 18 and most preferably beyond the first silicon nitride layer 22 as shown in FIG. 5, thereby allowing a step for planarizing the substrate. In FIG. 6, the substrate planarization step is preferably performed by chemical-mechanical polishing a top side of the substrate. To reduce the time required for chemical-mechanical polishing of the substrate, a preferable method for planarizing the substrate is to mask the first region of the substrate 14 above the cavity 20 with a mask layer (e.g. a patterned photoresist layer) and to remove the sacrificial layers 30 and 32 covering the remainder of the substrate 14 by a dry etching step. During the substrate planarization step, the first silicon nitride layer 22 is preferably used as a polishing stop to limit a downward extent of the chemical-mechanical polishing, thereby providing a substantially planar upper surface for the substrate. After the chemical-mechanical polishing step, the silicon nitride layer 22 in acting as a polishing stop can be reduced to about 100-300 nanometers thickness.

After planarization of the substrate 14, a second silicon nitride layer (i.e. a cap layer) 34 can be deposited over the planar upper surface of the substrate covering the remaining portion of the first silicon nitride layer 22 and any exposed portions of the sacrificial layers 30 and 32, thereby forming a nitride-to-nitride seal for sealing the encapsulated MEM devices 12. After this sealing step has been performed, the electronic circuitry 16 can be fabricated within the second portion of the substrate 14 according to conventional methods (i.e. standard process steps with little if any modification thereof as known to the art for forming CMOS, BiCMOS, or bipolar transistors). The sealed substrate can even be shipped to a foundry or other entity for fabrication of the electronic circuitry 16 by a set of standard process steps.

Since any stress within elements of the MEM devices 12 (e.g. polysilicon cantilevered beams) can be detrimental to operation of the device, an annealing step for relieving the stress is preferably performed. This annealing step can be performed before fabrication of the electronic circuitry 16 by heating the substrate and encapsulated MEM devices to a preselected temperature in the range of about 700-1300 time period of up to about three hours or more depending upon the level of stress to be relieved. Alternately, the annealing step can be performed during a thermal cycle used for fabricating the electronic circuitry 16 (e.g one or more thermal diffusion steps for forming transistors).

In some cases, the formation of the electronic circuitry 16 can begin immediately after planarizing the substrate 14, with the second silicon nitride layer 34 being deposited during a standard process step for forming the electronic circuitry 16. In this case shown schematically in FIGS. 7-13 and described hereinafter with reference to a preferred process for forming CMOS circuitry 16 (i.e. circuitry comprising a plurality of complementary metal-oxide semiconductor transistors), the first silicon nitride layer 22 and the underlying thermal oxide are preferably removed by etching in the second portion of the substrate (see FIG. 7) to provide a bare portion of the substrate 14 upon which new thermal oxide and silicon nitride layers can be formed with precise thicknesses for carrying out a set of standard processes for forming the CMOS circuitry 16. For certain interconnect metallization schemes, this process of removing the first silicon nitride layer 22 and the underlying oxide and forming the new thermal oxide and silicon nitride layers is to be preferred for reducing or eliminating metallization step coverage problems. During these standard process steps for forming the electronic circuitry 16, openings can also be made to each polysilicon stud 28 as shown in FIG. 7 for later use in forming electrical interconnections between the electronic circuitry 16 and each MEM device 12.

In FIG. 8, after formation of a new thermal oxide layer (about 30-40 nanometers thick) on the exposed device surface 18, a second silicon nitride layer 34 (i.e. the new silicon nitride layer which is also termed a cap layer) can then be deposited over the entire upper surface of the wafer 14 to a layer thickness of about 120 nanometers, for example, for use in forming the CMOS circuitry 16 and also for use in sealing the cavity 20 containing the encapsulated MEM device 12. In FIG. 9, openings can be formed through the second silicon nitride layer 34 for forming n-type and p-type isolation wells (also termed tubs) by ion implantation and thermal diffusion steps. Subsequent standard CMOS process steps can be used for forming n-type transistors 36 within the p-type wells, and for forming p-type transistors 38 within the n-type wells. Such standard CMOS process steps can include the deposition and patterning of one or more polysilicon layers for forming transistor gates and resistors 40; and the deposition and patterning of a plurality of passivation layers 42 (including, for example, a field oxide layer of CVD silicon dioxide and overlying layers of one or more silicate glasses such as TEOS; phosphorous silicate glass, also termed PSG; or borophosphorous silicate glass, also termed BPSG deposited by CVD or PECVD).

In FIG. 10, one or more layers of an interconnect metallization 44 are provided by standard deposition and patterning steps to interconnect elements (e.g. transistors, resistors, capacitors) forming the electronic circuitry 16, to provide electrical interconnections to the MEM device 12 via the polysilicon studs 28, and to provide a plurality of bonding or contact pads (not shown) for providing electrical connections to form a packaged integrated device 10. The interconnect metallization 44 is considered herein to form a part of the electronic circuitry 16.

Aluminum or an alloy thereof is preferred for use as the interconnect metallization 44, although other metals (e.g tungsten, gold, copper, platinum, nickel, palladium), metal alloys (including metal silicides) and even doped polysilicon can be used for the electrical interconnections depending upon operating requirements for the integrated devices 10, and a particular set of standard process steps to be used for practice of the present invention. Additional passivation layers (e.g. about 200 nanometers of a silicate glass such as plasma-enhanced TEOS, also termed PETEOS) can be provided to separate a plurality of layers of the interconnect metallization 44 (not shown in FIG. 10), and to blanket the electronic circuitry 16 and interconnect metallization for environmental protection and stress relief.

After fabrication of the electronic circuitry is substantially completed, a protection layer 46 preferably comprising tungsten is deposited to blanket the second portion of the substrate 14 and cover the electronic circuitry 16 for protection of the electronic circuitry 16 during an etch release process step whereby the MEM device 12 is exposed to an etchant for removing the sacrificial material, at least in part, and releasing the MEM device 12 into its final suspended state for movement or operation. As shown in FIG. 11, the protection layer 46 can also be deposited to blanket the first portion of the substrate 14 containing the MEMS device 12, with one or more etch channels 48 being formed (e.g. by photolithographic patterning and etching) through the protection layer 46 and the second silicon nitride layer 34 to expose the sacrificial material for removal by etching.

The use of a tungsten protection layer 46 is especially preferred when an wet etchant comprising, at least in part, hydrofluoric acid (HF). Particular etchant compositions that can be used according to the present invention for releasing the MEMS device 12 include mixtures of hydrofluoric acid (HF) and hydrochloric acid (HCI), and mixtures of HF and water (H.sub.2 O). The exact proportions of the constituents in each mixture will depend upon a predetermined etching rate for the sacrificial material which can be determined from practice of the present invention. Such HF:HCI or HF:H.sub.2 O wet etchants are advantageous for etching the sacrificial material at a much faster rate as compared with a buffered oxide etchant, thereby substantially reducing the time required for releasing the MEM devices 12. However, use of the HF:HCI or HF:H.sub.2 O wet etchants require more substantial protection for the electronic circuitry 16 than is provided by a photoresist protection layer 46 which is generally sufficient for the buffered oxide etchant.

A preferred method for forming the protection layer 46 according to the present invention is to initially deposit (e.g. by sputtering or CVD) a thin layer (e.g. about 50 nanometers thick) of titanium nitride (TiN) over the substrate 14 as an adhesion layer, and then to deposit a thicker layer (e.g. about 0.1-1 microns thick) of tungsten (W) over the titanium nitride layer (e.g. by CVD using WF.sub.6 as a source gas). This forms a two-ply protection layer 46 which has a substantial chemical resistance to the HF:HCI or HF:H.sub.2 O wet etchants, thereby protecting the electronic circuitry 16 from exposure to the wet etchants which could damage the electronic circuitry 16. The TiN:W protection layer 46 can be removed after the etch release step described hereinafter without damaging the electronic circuitry 16 by exposing the tungsten and titanium nitride layers to another wet etchant having a chemical composition different from the chemical composition of the wet etchant used for releasing the MEM device 12. This wet etchant for removing the TiN:W protection layer 46 can comprise hydrogen peroxide, for example.

FIG. 12 shows the substrate 14 with integrated MEM device 12 and electronic circuitry 16 after the etch release step in which the sacrificial material (e.g. sacrificial layers 30 and 32) is removed at least in part by the HF:HCI wet etchant or by the HF:H.sub.2 O wet etchant. These wet etchant compositions dissolve the sacrificial material, but preferably do not substantially affect (i.e. attack) any other materials (e.g. polysilicon, silicon nitride or metals) used to form the MEM device 12. In order to remove all of the sacrificial material, the etch release step can proceed for up to an hour or longer, depending upon the size, number and location of etch channels 48 provided.

Alternately, the wet etching process step can be limited in time duration so that some of the sacrificial material is left to support the polysilicon studs 28 and/or other fixed structural elements of the MEM devices. In this latter case, factors of the etch release process including the position, number and size of the etch channels 48; the chemical composition of the etchant; and the time for etching can be selected to limit a lateral extent of etching of the sacrificial material, thereby leaving portions of the sacrificial material surrounding the polysilicon studs 28 or the other fixed structural elements of the MEM devices 12.

After this etch release step, the substrate is then preferably washed in a rinse fluid for cleansing thereof, and is dried preferably using one of the stiction-free drying methods known to the art. Additionally, the released MEM devices 12 can be exposed to a stiction-prevention agent as known to the art for reducing possibility for stiction of moveable elements (e.g. cantilevered beams) of the MEM devices 12 during the drying step or afterwards.

The etch channels 48 in FIGS. 11 and 12 can range in size from about 1-1000 μm diameter depending on the particular type of MEM device 12 to be formed and also on whether one or more of the etch channels 48 will later be plugged by a deposition step for forming a sealed cavity (e.g. for providing a predetermined level of pressure or vacuum therein, or for forming a pressure sensing diaphragm above the cavity for sensing an ambient or applied pressure or vacuum); or for providing a protected enclosure for the MEM devices, thereby simplifying packaging. This process step for plugging one or more of the etch channels according to some embodiments of the present invention is shown in FIG. 13. By plugging the etch channels 48 with plugs 50 of a deposited material such as PECVD silicon nitride, the MEM devices can be sealed under a near-vacuum condition (about 200 Torr pressure). Alternately, the step of plugging the etch channels 48 can be carried out by sputtering or evaporating a metal (e.g. aluminum), or by low-temperature deposition of a plasma-enhanced oxide or silicate glass.

In some embodiments of the present invention, polysilicon piezoresistors can be formed over a pressure diaphragm formed above the MEM devices by the plugged nitride layer 34 for measuring changes in pressure or vacuum. These process steps for sealing the MEM devices 12 can also be advantageous for packaging the integrated device 10 since the sealed MEM device 12 (with or without plugs 50) is protected from the environment outside the cavity 20, thereby preventing the possibility of damage from dust, and also minimizing possible damage from handling, testing and packaging. The completed device 10 with one or more sealed MEM devices 12 integrated with electronic circuitry 16 can be packaged by any means known to the art including the use of relatively inexpensive molded packages formed of plastics, epoxy or the like.

The matter set forth in the foregoing description and accompanying drawings is offered by way of illustration only and not as a limitation. Other applications and variations of the method for integrating microelectromechanical devices with electronic circuitry will become evident to those skilled in the art. The actual scope of the invention is intended to be defined in the following claims when viewed in their proper perspective based on the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated into and form a part of the specification, illustrate several aspects of the present invention and, together with the description, serve to explain the principles of the invention. The drawings are only for the purpose of illustrating preferred embodiments of the invention and are not to be construed as limiting the invention. In the drawings:

FIG. 1 shows a schematic cross-sectional representation of an integrated device 10 having one or more MEM devices integrated with electronic circuitry according to the method of the present invention.

FIGS. 2-13 show schematic cross-section representations of the integrated device of FIG. 1 during various process steps for forming the integrated device.

FIELD OF THE INVENTION

The present invention relates to methods for fabricating microelectromechanical devices. In particular, the invention is directed to a method for integrating microelectromechanical devices with electronic circuitry on a substrate.

BACKGROUND OF THE INVENTION

Microelectromechanical (MEM) devices have applications for forming many and varied types of microsensors and microactuators. The monolithic integration of MEM devices with electronic circuitry offers the possibility for increasing performance (e.g. forming "smart sensors" having driving, control, and signal processing circuitry formed therewith on a substrate, also termed a wafer or chip) and reliability as well as significantly reducing size and cost. Furthermore, the sensitivity of many types of microsensors (e.g. accelerometers) can be improved by a reduced noise level provided by on-chip circuitry.

U.S. Pat. No. 5,326,726 to Tsang et al discloses an interleaved or merged process approach for fabricating a monolithic chip containing integrated circuitry interconnected to a microstructure (i.e. a MEM device). The approach of Tsang et al requires that the separate steps for forming the MEM device and the integrated circuit be interleaved for compatibility, with the electronic circuitry being formed at least in part prior to the MEM device, and electrical interconnections between the circuitry and the MEM device being formed thereafter. While Tsang et al use some essentially standard process steps, other process steps must be modified due to conflicting requirements between the circuitry and MEM devices.

These modified process steps are primarily dictated by thermal cycles and topography during processing which are largely responsible for determining a strategy for developing a merged or interleaved approach for integrating MEM devices with electronic circuitry. As an example, "islands" of severe topography can be formed by MEM devices extending upward several microns above the substrate, requiring modifications to photolithography and etching processes for forming electrical interconnections between the MEM devices and circuitry. Such modification of process steps to the extent that it deviates from standard processing steps is disadvantageous and costly in requiring that the modified process steps be adapted to a particular type of MEM device, and altered for fabrication of other types of MEM devices. The development of non-standard process steps for forming electronic circuitry that are dictated by requirements of a particular MEM device is disadvantageous in requiring a lengthy period of time for process modification or re-engineering, thereby preventing rapid prototyping of different MEM technologies or MEM development work. Furthermore, since process steps for forming electronic circuitry (e.g. comprising CMOS transistors) are well established and standardized, any modification of the process steps can significantly decrease the circuit performance and the overall process yield.

What is needed is a method for integrating MEM devices with electronic circuitry that substantially separates the process steps for fabricating the MEM devices from the process steps for fabricating the electronic circuitry, thereby allowing the use of standard process steps as known to the art, especially for fabricating the electronic circuitry.

Heretofore, such a separation of steps for fabricating MEM devices and steps for fabricating electronic circuitry has been based on a method of fabricating the electronic circuitry prior to fabrication of the MEM devices in a circuitry-first approach. This approach has been primarily motivated by concerns about contamination and a rough topography that is generally thought to be inevitable if the MEM devices were fabricated first. A rough topography places severe demands on subsequent lithography and etching processes for forming the electronic circuitry. The use of a circuitry-first approach, however, is disadvantageous in requiring deviations from standard processing steps (i.e. process modifications), especially in requiring the use of tungsten instead of aluminum for the interconnect metallization to withstand a high-temperature annealing step required to at least partially relieve stress in polysilicon elements (e.g. cantilevered beams) of MEM devices. However, the use of tungsten as an interconnect metallization is not altogether satisfactory, resulting in additional problems including a high contact resistance and hillock formation that can lead to inadequate protection of the electronic circuitry during release of the MEM devices. Additional problems known to occur with this circuitry-first approach include an undesirable formation of tungsten silicides, and poor adhesion of the tungsten interconnect metallization.

An advantage of the method of the present invention is that microelectromechanical (MEM) devices can be integrated with electronic circuitry on a substrate while using standard process steps with little if any modification for fabricating the electronic circuitry, including the use of an aluminum interconnect metallization in preferred embodiments of the present invention.

Another advantage of the present invention is that one or more MEM devices can be fabricated prior to fabrication of electronic circuitry, with the MEM devices being encapsulated to prevent contamination of a device surface of the substrate.

A further advantage of the present invention is that the substrate can be planarized prior to formation of the electronic circuitry thereby providing a substantially smooth and planar surface topography for subsequent process steps for fabricating the electronic circuitry.

Still another advantage of the present invention is that the encapsulated MEM devices can be annealed under temperature and time conditions sufficient to relieve strain in elements of the MEM devices prior to formation of the electronic circuitry including the interconnect metallization.

Yet another advantage is that by providing one or more encapsulated MEM devices formed within a cavity below a device surface of a planarized substrate, the substrate can be handled and processed thereafter using substantially standard process steps with little if any modification for forming the electronic circuitry (including the interconnect metallization).

Another advantage of the present invention is that the electronic circuitry can be protected during an etching step for releasing the encapsulated MEM device by covering the electronic circuitry with a layer of deposited tungsten that can be removed without damaging the underlying electronic circuitry after the MEM device is released.

Yet another advantage of the method of the present invention is that packaging of both MEM and integrated devices (i.e. MEM devices integrated with electronic circuitry) can be simplified and cost reduced by forming one or more of the MEM devices below a device surface of a substrate with an overlying layer forming at least a part of an enclosure for packaging the devices.

These and other advantages of the method of the present invention will become evident to those skilled in the art.

SUMMARY OF THE INVENTION

The present invention relates to a method for integrating one or more microelectromechanical (MEM) devices with electronic circuitry on a common substrate. The method comprises steps for etching a cavity within a first portion of the substrate; fabricating the MEM device within the cavity, and filling the cavity with one or more layers of a sacrificial material; fabricating the electronic circuitry comprising a plurality of transistors within a second portion of the substrate proximate to the first portion, and interconnecting the electronic circuitry to the MEM device; protecting the electronic circuitry by depositing a layer of tungsten to blanket the second portion of the substrate and to cover the electronic circuitry; and releasing the MEM device for operation thereof by removing at least a portion of the sacrificial material filling the cavity by etching the sacrificial material with a first wet etchant which does not substantially remove the layer of tungsten protecting the electronic circuitry. In preferred embodiments of the present invention, the step for protecting the electronic circuitry further comprises a step for depositing an adhesion layer (e.g. comprising titanium nitride) over the second portion of the substrate prior to the step for depositing the layer of tungsten. The method of the present invention can further comprise a step for removing the layer of tungsten (and the adhesion layer, if present) after the step for releasing the MEM device.

The substrate preferably comprises silicon; and the step for etching the cavity within the first portion of the substrate can comprise either etching the cavity into the substrate, or etching the cavity into one or more semiconductor layers formed on the substrate. The step for fabricating the MEM device can comprise steps for depositing, patterning and etching layers of one or more micromachineable materials selected from the group consisting of polycrystalline silicon (also termed polysilicon), silicon dioxide, silicon nitride, silicate glass, metals and metal alloys. The step for filling the cavity with a sacrificial material preferably comprises depositing a silicate glass within the cavity.

In preferred embodiments of the present invention, the step for fabricating the MEM device can include a step for annealing the MEM device, thereby relieving stress in the MEM device. The step for fabricating the MEM device can further include a step for planarizing the substrate (e.g. by a chemical-mechanical polishing step) prior to the step for fabricating the electronic circuitry.

Additional advantages and novel features of the invention will become apparent to those skilled in the art upon examination of the following detailed description thereof when considered in conjunction with the accompanying drawings. The advantages of the invention can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation-in-part of application Ser. No. 08/524,700, filed Sep. 6, 1995, now U.S. Pat. No. 5,798,283. This invention is further related to applications Ser. No. 08/903,985, filed on Jul. 31, 1997, now U.S. Pat. No. 5,783,340 and Ser. No. 08/915,071, filed on Aug. 20, 1997, pending, both of which are incorporated herein by reference.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4562092 *30 Oct 198431 Dec 1985Fine Particle Technology CorporationMethod of fabricating complex microcircuit boards, substrates and microcircuits and the substrates and microcircuits
US4859629 *14 Dec 198722 Aug 1989M/A-Com, Inc.Method of fabricating a semiconductor beam lead device
US5095401 *21 May 199010 Mar 1992Kopin CorporationSOI diaphragm sensor
US5227335 *30 Apr 199013 Jul 1993At&T Bell LaboratoriesTungsten metallization
US5242839 *25 Nov 19927 Sep 1993Electronics And Telecommunications Research InstituteMethod of manufacturing an integrated photoelectric receiving device
US5260596 *8 Apr 19919 Nov 1993Motorola, Inc.Monolithic circuit with integrated bulk structure resonator
US5314572 *22 Apr 199224 May 1994Analog Devices, Inc.Method for fabricating microstructures
US5326726 *21 Jun 19935 Jul 1994Analog Devices, Inc.Method for fabricating monolithic chip containing integrated circuitry and suspended microstructure
US5345824 *4 Mar 199313 Sep 1994Analog Devices, Inc.Monolithic accelerometer
US5399415 *4 Jun 199321 Mar 1995Cornell Research Foundation, Inc.Isolated tungsten microelectromechanical structures
US5412265 *5 Apr 19932 May 1995Ford Motor CompanyPlanar micro-motor and method of fabrication
US5417111 *10 Jun 199323 May 1995Analog Devices, Inc.Monolithic chip containing integrated circuitry and suspended microstructure
US5427975 *10 May 199327 Jun 1995Delco Electronics CorporationMethod of micromachining an integrated sensor on the surface of a silicon wafer
US5431051 *29 Mar 199411 Jul 1995Siemens AktiengesellschaftTunnel effect acceleration sensor
US5431057 *18 Feb 199411 Jul 1995Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V.Integratable capacitative pressure sensor
US5455203 *11 Feb 19933 Oct 1995Seiko Instruments Inc.Method of adjusting the pressure detection value of semiconductor pressure switches
US5493177 *26 Oct 199320 Feb 1996The Regents Of The University Of CaliforniaSealed micromachined vacuum and gas filled devices
US5504026 *14 Apr 19952 Apr 1996Analog Devices, Inc.Methods for planarization and encapsulation of micromechanical devices in semiconductor processes
US5550090 *5 Sep 199527 Aug 1996Motorola Inc.Method for fabricating a monolithic semiconductor device with integrated surface micromachined structures
US5798283 *6 Sep 199525 Aug 1998Sandia CorporationMethod for integrating microelectromechanical devices with electronic circuitry
US5814554 *21 Nov 199529 Sep 1998U.S. Philips CorporationSemiconductor device provided with a microcomponent having a fixed and a movable electrode
JPH04357854A * Title not available
Non-Patent Citations
Reference
1P. J. Ireland, "High Aspect Ratio Contacts: A Review of the Current Tungsten Plug Process," Thin Solid Films, vol. 304, pp. 1-12, 1997.
2 *P. J. Ireland, High Aspect Ratio Contacts: A Review of the Current Tungsten Plug Process, Thin Solid Films , vol. 304, pp. 1 12, 1997.
3R. T. Howe, "Polysilicon Integrated Microsystems: Technologies and Applications," Digest of Technical Papers for the 8th International Conference on Solid-State Sensors and Actuators and Eurosensors IX, Stockholm, Sweden, Jun. 25-29, 1995, vol. 1, pp. 43-46, 1995.
4 *R. T. Howe, Polysilicon Integrated Microsystems: Technologies and Applications, Digest of Technical Papers for the 8th International Conference on Solid State Sensors and Actuators and Eurosensors IX , Stockholm, Sweden, Jun. 25 29, 1995, vol. 1, pp. 43 46, 1995.
5 *S. Wolf, Silicon Processing fro the VLSI Era, vol. 2, pp. 247 251, 1990.
6S. Wolf, Silicon Processing fro the VLSI Era, vol. 2, pp. 247-251, 1990.
7W. Kuehnel and S. Sherman, "A Surface Micromachined Silicon Accelerometer with On-Chip Detection Circuitry," Sensors and Acuators A, vol. 45, pp. 7-16, 1994.
8 *W. Kuehnel and S. Sherman, A Surface Micromachined Silicon Accelerometer with On Chip Detection Circuitry, Sensors and Acuators A, vol. 45, pp. 7 16, 1994.
9W. Riethmuller, W. Benecke, U. Schnakenberg, and B. Wagner, "A Smart Accererometer with On-Chip Electronics Fabricated by a Commercial CMOS Process," Sensors and Actuators A, vol. 31, pp. 121-124, 1992.
10 *W. Riethmuller, W. Benecke, U. Schnakenberg, and B. Wagner, A Smart Accererometer with On Chip Electronics Fabricated by a Commercial CMOS Process, Sensors and Actuators A, vol. 31, pp. 121 124, 1992.
11 *W. Yun, CMOS Metallization for Integration with Micromachining Processes, Thesis for Master of Science Degree in Electrical Engineering from the University of California, Berkley, May 19, 1989.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6077784 *11 Aug 199820 Jun 2000United Microelectronics Corp.Chemical-mechanical polishing method
US6136630 *3 Jun 199924 Oct 2000The Regents Of The University Of MichiganMethod of making a micromechanical device from a single crystal semiconductor substrate and monolithic sensor formed thereby
US6174820 *16 Feb 199916 Jan 2001Sandia CorporationUse of silicon oxynitride as a sacrificial material for microelectromechanical devices
US6184054 *27 Nov 19986 Feb 2001Miracle Technology Co., Ltd.Optical electronic IC capable of photo detection and its process
US627105219 Oct 20007 Aug 2001Axsun Technologies, Inc.Process for integrating dielectric optical coatings into micro-electromechanical devices
US630196514 Dec 199916 Oct 2001Sandia CorporationMicroelectromechanical accelerometer with resonance-cancelling control circuit including an idle state
US633522416 May 20001 Jan 2002Sandia CorporationProtection of microelectronic devices during packaging
US635001524 Nov 200026 Feb 2002Xerox CorporationMagnetic drive systems and methods for a micromachined fluid ejector
US6355534 *26 Jan 200012 Mar 2002Intel CorporationVariable tunable range MEMS capacitor
US636791528 Nov 20009 Apr 2002Xerox CorporationMicromachined fluid ejector systems and methods
US63921441 Mar 200021 May 2002Sandia CorporationMicromechanical die attachment surcharge
US640613020 Feb 200118 Jun 2002Xerox CorporationFluid ejection systems and methods with secondary dielectric fluid
US640931124 Nov 200025 Jun 2002Xerox CorporationBi-directional fluid ejection systems and methods
US641616924 Nov 20009 Jul 2002Xerox CorporationMicromachined fluid ejector systems and methods having improved response characteristics
US641933524 Nov 200016 Jul 2002Xerox CorporationElectronic drive systems and methods
US6429458 *31 Jul 20006 Aug 2002The Regents Of The University Of MichiganMethod of making a micromechanical device from a single crystal semiconductor substrate and monolithic sensor formed thereby
US643796528 Nov 200020 Aug 2002Harris CorporationElectronic device including multiple capacitance value MEMS capacitor and associated methods
US64407667 Jul 200027 Aug 2002Analog Devices Imi, Inc.Microfabrication using germanium-based release masks
US6448103 *30 May 200110 Sep 2002Stmicroelectronics, Inc.Method for making an accurate miniature semiconductor resonator
US647233228 Nov 200029 Oct 2002Xerox CorporationSurface micromachined structure fabrication methods for a fluid ejection device
US6503775 *21 Sep 20017 Jan 2003Aisin Seiki Kabushiki KaishaProduction method of a micromachine
US651185910 Mar 200028 Jan 2003California Institute Of TechnologyIC-compatible parylene MEMS technology and its application in integrated sensors
US6513898 *23 Jun 19984 Feb 2003Stmicroelectronics S.R.L.Integrated inkjet print head and manufacturing process thereof
US6521965 *12 Sep 200018 Feb 2003Robert Bosch GmbhIntegrated pressure sensor
US65288871 Mar 20014 Mar 2003Onix MicrosystemsConductive equipotential landing pads formed on the underside of a MEMS device
US653133116 Jul 200211 Mar 2003Sandia CorporationMonolithic integration of a MOSFET with a MEMS device
US6534413 *27 Oct 200018 Mar 2003Air Products And Chemicals, Inc.Method to remove metal and silicon oxide during gas-phase sacrificial oxide etch
US658684110 Apr 20001 Jul 2003Onix Microsystems, Inc.Mechanical landing pad formed on the underside of a MEMS device
US660058723 Apr 200129 Jul 2003Memx, Inc.Surface micromachined optical system with reinforced mirror microstructure
US661103312 Apr 200126 Aug 2003Ibm CorporationMicromachined electromechanical (MEM) random access memory array and method of making same
US6696364 *8 Aug 200224 Feb 2004Stmicroelectronics S.R.L.Method for manipulating MEMS devices, integrated on a wafer semiconductor and intended to be diced one from the other, and relevant support
US672743615 Mar 200227 Apr 2004Memx, Inc.Interconnect bus crossover for MEMS
US673151315 Mar 20024 May 2004Memx, Inc.Shielded multi-conductor interconnect bus for MEMS
US674734015 Mar 20028 Jun 2004Memx, Inc.Multi-level shielded multi-conductor interconnect bus for MEMS
US675631723 Apr 200129 Jun 2004Memx, Inc.Method for making a microstructure by surface micromachining
US6762116 *12 Jun 200213 Jul 2004Zyvex CorporationSystem and method for fabricating microcomponent parts on a substrate having pre-fabricated electronic circuitry thereon
US676493623 Jul 200120 Jul 2004Onix Microsystems, Inc.Mechanical landing pad formed on the underside of a MEMS device
US67783058 Apr 200317 Aug 2004Memx, Inc.Surface micromachined optical system with reinforced mirror microstructure
US67783065 May 200317 Aug 2004Memx, Inc.Surface micromachined optical system with reinforced mirror microstructure
US67812089 Aug 200224 Aug 2004Nec CorporationFunctional device, method of manufacturing therefor and driver circuit
US67873843 Sep 20037 Sep 2004Nec CorporationFunctional device, method of manufacturing therefor and driver circuit
US678852028 Nov 20007 Sep 2004Behrang BehinCapacitive sensing scheme for digital control state detection in optical switches
US679069818 Sep 200114 Sep 2004Axsun Technologies, Inc.Process for integrating dielectric optical coatings into micro-electromechanical devices
US67917308 Apr 200314 Sep 2004Memx, Inc.Surface micromachined optical system with reinforced mirror microstructure
US6794213 *5 Aug 200321 Sep 2004The United States Of America As Represented By The Administrator Of The National Aeronautics And Space AdministrationMethod of assembling a silicon carbide high temperature anemometer
US681305727 Sep 20012 Nov 2004Memx, Inc.Configurations for an optical crossconnect switch
US681982018 Aug 200116 Nov 2004Analog Devices, Inc.Use of applied force to improve MEMS switch performance
US682427815 Mar 200230 Nov 2004Memx, Inc.Self-shadowing MEM structures
US6838228 *14 May 20014 Jan 2005Fairchild Semiconductor CorporationSystem to enable photolithography on severe structure topologies
US684146430 Apr 200311 Jan 2005Memx, Inc.Multi-level shielded multi-conductor interconnect bus for MEMS
US685644910 Jul 200315 Feb 2005Evans & Sutherland Computer CorporationUltra-high resolution light modulation control system and method
US688897912 Apr 20013 May 2005Analog Devices, Inc.MEMS mirrors with precision clamping mechanism
US691399320 Nov 20015 Jul 2005United Microelectronics Corp.Chemical-mechanical polishing method
US6923669 *13 Feb 20042 Aug 2005Zyvex CorporationMicroconnectors and non-powered microassembly therewith
US6930364 *13 Sep 200116 Aug 2005Silicon Light Machines CorporationMicroelectronic mechanical system and methods
US693713112 Nov 200430 Aug 2005Memx, Inc.Self-shadowing MEM structures
US695621912 Nov 200418 Oct 2005Zyvex CorporationMEMS based charged particle deflector design
US695828527 Mar 200225 Oct 2005Tru-Si Technologies, Inc.Methods of manufacturing devices having substrates with opening passing through the substrates and conductors in the openings
US69804125 Nov 200127 Dec 2005Intel CorporationVariable tunable range MEMS capacitor
US7002436 *19 Aug 200421 Feb 2006Intel CorporationVacuum-cavity MEMS resonator
US700531427 Jun 200128 Feb 2006Intel CorporationSacrificial layer technique to make gaps in MEMS applications
US7021151 *29 Oct 20044 Apr 2006National Semiconductor CorporationMEMS pressure sensing array with leaking sensor
US70256198 Mar 200511 Apr 2006Zyvex CorporationSockets for microassembly
US702669811 May 200411 Apr 2006Denso CorporationFunctional device, method of manufacturing therefor and driver circuit
US702982916 Apr 200318 Apr 2006The Regents Of The University Of MichiganLow temperature method for forming a microcavity on a substrate and article having same
US704545919 Feb 200216 May 2006Northrop Grumman CorporationThin film encapsulation of MEMS devices
US7049164 *9 Oct 200223 May 2006Silicon Light Machines CorporationMicroelectronic mechanical system and methods
US70526228 Oct 200230 May 2006Applied Materials, Inc.Method for measuring etch rates during a release process
US7054052 *4 Sep 200330 May 2006Frank NiklausAdhesive sacrificial bonding of spatial light modulators
US70605227 Nov 200113 Jun 2006Xerox CorporationMembrane structures for micro-devices, micro-devices including same and methods for making same
US708163012 Mar 200425 Jul 2006Zyvex CorporationCompact microcolumn for automated assembly
US709656810 Jul 200329 Aug 2006Zyvex CorporationMethod of manufacturing a microcomponent assembly
US71051315 Sep 200212 Sep 2006Xerox CorporationSystems and methods for microelectromechanical system based fluid ejection
US7109051 *15 Nov 200419 Sep 2006Freescale Semiconductor, Inc.Method of integrating optical devices and electronic devices on an integrated circuit
US712114629 Oct 200417 Oct 2006National Semiconductor CorporationMEMS pressure sensing device
US71418123 Dec 200228 Nov 2006Mikro Systems, Inc.Devices, methods, and systems involving castings
US71701417 Mar 200330 Jan 2007Cornell Research Foundation, Inc.Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry
US71836331 Mar 200227 Feb 2007Analog Devices Inc.Optical cross-connect system
US7183637 *13 May 200527 Feb 2007Silicon Light Machines CorporationMicroelectronic mechanical system and methods
US722103330 Jun 200522 May 2007Robert Bosch GmbhAnti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
US724813114 Mar 200524 Jul 2007Avago Technologies Wireless Ip (Singapore) Pte. Ltd.Monolithic vertical integration of an acoustic resonator and electronic circuitry
US728846411 Apr 200530 Oct 2007Hewlett-Packard Development Company, L.P.MEMS packaging structure and methods
US731438218 May 20051 Jan 2008Zyvex Labs, LlcApparatus and methods of manufacturing and assembling microscale and nanoscale components and assemblies
US732860929 Oct 200412 Feb 2008National Semiconductor CorporationWireless pressure sensing Schrader valve
US733559819 Apr 200526 Feb 2008United Microelectronics Corp.Chemical-mechanical polishing method
US7352039 *24 Mar 20051 Apr 2008Intel CorporationMethods and apparatuses for microelectronic assembly having a material with a variable viscosity around a MEMS device
US735858030 Sep 200515 Apr 2008Intel CorporationSacrificial layer technique to make gaps in MEMS applications
US73738339 Aug 200620 May 2008National Semiconductor CorporationMEMS pressure sensing device
US74106065 Jun 200212 Aug 2008Appleby Michael PMethods for manufacturing three-dimensional devices and devices created thereby
US7411204 *21 Nov 200612 Aug 2008Michael ApplebyDevices, methods, and systems involving castings
US7443002 *18 Dec 200328 Oct 2008Commissariat A L'energie AtomiqueEncapsulated microstructure and method of producing one such microstructure
US744935527 Apr 200511 Nov 2008Robert Bosch GmbhAnti-stiction technique for electromechanical systems and electromechanical device employing same
US760537717 Oct 200620 Oct 2009Zyvex CorporationOn-chip reflectron and ion optics
US761578829 Jan 200710 Nov 2009Cornell Research Foundation, Inc.Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry
US763336027 Sep 200615 Dec 2009Analog Devices, Inc.MEMS resonator having an inner element and an outer element that flex
US763842912 Apr 200629 Dec 2009Northrop Grumman CorporationThin film encapsulation of MEMS devices
US7750420 *24 Mar 20056 Jul 2010Cypress Semiconductor CorporationIntegrated circuit having one or more conductive devices formed over a SAW and/or MEMS device
US775739328 Sep 200720 Jul 2010Georgia Tech Research CorporationCapacitive microaccelerometers and fabrication methods
US776748430 May 20073 Aug 2010Georgia Tech Research CorporationMethod for sealing and backside releasing of microelectromechanical systems
US778509814 Dec 200731 Aug 2010Mikro Systems, Inc.Systems for large area micro mechanical systems
US7863069 *27 Sep 20064 Jan 2011Analog Devices, Inc.Method of forming an integrated MEMS resonator
US788941517 Apr 200915 Feb 2011Qualcomm Mems Technologies, Inc.Device having a conductive light absorbing mask and method for fabricating same
US790635329 Jun 200915 Mar 2011Qualcomm Mems Technologies, Inc.Method of fabricating interferometric devices using lift-off processing techniques
US792919710 Jun 201019 Apr 2011Qualcomm Mems Technologies, Inc.System and method for a MEMS device
US7935556 *27 Aug 20073 May 2011Memsmart Semiconductor Corp.Microelectromechanical system and process of making the same
US794760328 Dec 200724 May 2011United Microelectronics Corp.Chemical-mechanical polishing method
US802316725 Jun 200820 Sep 2011Qualcomm Mems Technologies, Inc.Backlight displays
US803588320 Jan 201111 Oct 2011Qualcomm Mems Technologies, Inc.Device having a conductive light absorbing mask and method for fabricating same
US8071411 *22 Dec 20086 Dec 2011The Royal Institution For The Advancement Of Learning/Mcgill UniversityLow temperature ceramic microelectromechanical structures
US8105496 *14 Feb 200831 Jan 2012Qualcomm Mems Technologies, Inc.Method of fabricating MEMS devices (such as IMod) comprising using a gas phase etchant to remove a layer
US8115266 *28 Jun 201114 Feb 2012Seiko Epson CorporationMEMS device having a movable electrode
US8217473 *29 Jul 200510 Jul 2012Hewlett-Packard Development Company, L.P.Micro electro-mechanical system packaging and interconnect
US823192419 Aug 200531 Jul 2012Cargill, IncorporatedIngredient systems comprising trehalose, food products containing trehalose, and methods of making same
US824336030 Sep 201114 Aug 2012Qualcomm Mems Technologies, Inc.Device having a conductive light absorbing mask and method for fabricating same
US8330323 *9 Nov 201111 Dec 2012Cornell Research Foundation, Inc.Thermal-mechanical signal processing
US83726778 May 201212 Feb 2013Qualtre, Inc.Three-axis accelerometers and fabrication methods
US838941014 Apr 20115 Mar 2013United Microelectronics Corp.Chemical mechanical polishing method
US83905477 Jun 20115 Mar 2013Qualcomm Mems Technologies, Inc.Conductive bus structure for interferometric modulator array
US83952276 Jan 201212 Mar 2013Seiko Epson CorporationMEMS device having a movable electrode
US8593811 *23 Sep 201126 Nov 2013Dunan Microstaq, Inc.Method and structure for optimizing heat exchanger performance
US8629517 *10 Dec 201214 Jan 2014Taiwan Semiconductor Manufacturing Company, Ltd.Wafer level packaging
US20100109104 *30 Oct 20086 May 2010Radi Medical Systems AbPressure sensor and wire guide assembly
US20100248484 *26 Mar 201030 Sep 2010Christopher BowerMethods of Forming Printable Integrated Circuit Devices and Devices Formed Thereby
US20120058741 *9 Nov 20118 Mar 2012Cornell Research Foundation, Inc.Thermal-mechanical signal processing
US20120140416 *23 Sep 20117 Jun 2012Dunan Microstaq, Inc.Method and structure for optimizing heat exchanger performance
EP1339101A2 *21 Feb 200327 Aug 2003Xerox CorporationSystems and methods for integration of heterogeneous circuit devices
EP1352877A2 *9 Apr 200315 Oct 2003Dalsa Semiconductor Inc.Wafer-level MEMS packaging
EP1366518A1 *6 Mar 20023 Dec 2003Analog Devices, Inc.In-situ cap and method of fabricating same for an integrated circuit device
EP1683199A2 *15 Jun 200426 Jul 2006Robert Bosch GmbhAnti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
EP2036132A2 *24 May 200718 Mar 2009Akustica Inc.An integrated circuit device having barrier and method of fabricating the same
EP2559533A224 Sep 200920 Feb 2013Mikro Systems Inc.Systems, devices, and/or methods for manufacturing castings
EP2559534A224 Sep 200920 Feb 2013Mikro Systems Inc.Systems, devices, and/or methods for manufacturing castings
EP2559535A224 Sep 200920 Feb 2013Mikro Systems Inc.Systems, devices, and/or methods for manufacturing castings
WO2000054312A1 *10 Mar 200014 Sep 2000California Inst Of TechnIc-compatible parylene mems technology and its application in integrated sensors
WO2003002450A2 *27 Jun 20029 Jan 2003Intel CorpSacrificial layer technique to make gaps in mems applications
WO2003063223A1 *19 Dec 200231 Jul 2003Ball Semiconductor IncMethod for making a gas permeable enclosure for micromachine devices
WO2003070625A2 *19 Feb 200328 Aug 2003Carl B FreidhoffThin film encapsulation of mems devices
WO2003082732A2 *5 Feb 20039 Oct 2003Intel CorpPackaging microelectromechanical systems
WO2003083932A1 *11 Oct 20029 Oct 2003Applied Materials IncA method for measuring etch rtes during a release process
WO2003089368A2 *17 Apr 200330 Oct 2003Khalil NajafiLow temperature method for forming a microcavity on a substrate and article having same
WO2003090281A2 *15 Apr 200330 Oct 2003Jones Kevin SSingle crystal silicon membranes for microelectromechanical applications
WO2004058628A218 Dec 200315 Jul 2004Commissariat Energie AtomiqueEncapsulated microstructure and method of producing one such microstructure
WO2006055476A2 *14 Nov 200526 May 2006Nigel G CaveMethod of integrating optical devices and electronic devices on an integrated circuit
WO2006115592A1 *10 Mar 20062 Nov 2006Gmbh Robert BoschAnti-stiction technique for electromechanical systems and electromechanical device employing same
Classifications
U.S. Classification438/48, 438/50, 438/53, 148/DIG.105
International ClassificationG03F9/00, G03F7/09, B81B7/00, B81B7/02, G03F7/207, B81B3/00
Cooperative ClassificationY10S148/105, G03F9/70, B81C1/00246, G03F7/094, B81C2203/0728
European ClassificationG03F9/70, G03F7/09M, B81C1/00C12F
Legal Events
DateCodeEventDescription
15 Sep 2011SULPSurcharge for late payment
Year of fee payment: 11
15 Sep 2011FPAYFee payment
Year of fee payment: 12
9 May 2011REMIMaintenance fee reminder mailed
12 Oct 2006FPAYFee payment
Year of fee payment: 8
29 Jun 2005ASAssignment
Owner name: ENERGY, U.S. DEPARTMENT OF, DISTRICT OF COLUMBIA
Free format text: CONFIRMATORY LICENSE;ASSIGNOR:SANDIA CORPORATION;REEL/FRAME:016427/0762
Effective date: 19971217
22 Jan 2003FPAYFee payment
Year of fee payment: 4
22 Dec 1997ASAssignment
Owner name: SANDIA CORPORATION, NEW MEXICO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BARRON, CAROLE C.;FLEMING, JAMES G.;MONTAGUE, STEPHEN;REEL/FRAME:008860/0227;SIGNING DATES FROM 19971104 TO 19971119