|Publication number||US5963788 A|
|Application number||US 08/974,586|
|Publication date||5 Oct 1999|
|Filing date||19 Nov 1997|
|Priority date||6 Sep 1995|
|Publication number||08974586, 974586, US 5963788 A, US 5963788A, US-A-5963788, US5963788 A, US5963788A|
|Inventors||Carole C. Barron, James G. Fleming, Stephen Montague|
|Original Assignee||Sandia Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (22), Non-Patent Citations (11), Referenced by (272), Classifications (21), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention was made with Government support under Contract No. DE-AC04-94AL85000 awarded by the U.S. Department of Energy. The Government has certain rights in the invention.
This is a continuation-in-part of application Ser. No. 08/524,700, filed Sep. 6, 1995, now U.S. Pat. No. 5,798,283. This invention is further related to applications Ser. No. 08/903,985, filed on Jul. 31, 1997, now U.S. Pat. No. 5,783,340 and Ser. No. 08/915,071, filed on Aug. 20, 1997, pending, both of which are incorporated herein by reference.
The present invention relates to methods for fabricating microelectromechanical devices. In particular, the invention is directed to a method for integrating microelectromechanical devices with electronic circuitry on a substrate.
Microelectromechanical (MEM) devices have applications for forming many and varied types of microsensors and microactuators. The monolithic integration of MEM devices with electronic circuitry offers the possibility for increasing performance (e.g. forming "smart sensors" having driving, control, and signal processing circuitry formed therewith on a substrate, also termed a wafer or chip) and reliability as well as significantly reducing size and cost. Furthermore, the sensitivity of many types of microsensors (e.g. accelerometers) can be improved by a reduced noise level provided by on-chip circuitry.
U.S. Pat. No. 5,326,726 to Tsang et al discloses an interleaved or merged process approach for fabricating a monolithic chip containing integrated circuitry interconnected to a microstructure (i.e. a MEM device). The approach of Tsang et al requires that the separate steps for forming the MEM device and the integrated circuit be interleaved for compatibility, with the electronic circuitry being formed at least in part prior to the MEM device, and electrical interconnections between the circuitry and the MEM device being formed thereafter. While Tsang et al use some essentially standard process steps, other process steps must be modified due to conflicting requirements between the circuitry and MEM devices.
These modified process steps are primarily dictated by thermal cycles and topography during processing which are largely responsible for determining a strategy for developing a merged or interleaved approach for integrating MEM devices with electronic circuitry. As an example, "islands" of severe topography can be formed by MEM devices extending upward several microns above the substrate, requiring modifications to photolithography and etching processes for forming electrical interconnections between the MEM devices and circuitry. Such modification of process steps to the extent that it deviates from standard processing steps is disadvantageous and costly in requiring that the modified process steps be adapted to a particular type of MEM device, and altered for fabrication of other types of MEM devices. The development of non-standard process steps for forming electronic circuitry that are dictated by requirements of a particular MEM device is disadvantageous in requiring a lengthy period of time for process modification or re-engineering, thereby preventing rapid prototyping of different MEM technologies or MEM development work. Furthermore, since process steps for forming electronic circuitry (e.g. comprising CMOS transistors) are well established and standardized, any modification of the process steps can significantly decrease the circuit performance and the overall process yield.
What is needed is a method for integrating MEM devices with electronic circuitry that substantially separates the process steps for fabricating the MEM devices from the process steps for fabricating the electronic circuitry, thereby allowing the use of standard process steps as known to the art, especially for fabricating the electronic circuitry.
Heretofore, such a separation of steps for fabricating MEM devices and steps for fabricating electronic circuitry has been based on a method of fabricating the electronic circuitry prior to fabrication of the MEM devices in a circuitry-first approach. This approach has been primarily motivated by concerns about contamination and a rough topography that is generally thought to be inevitable if the MEM devices were fabricated first. A rough topography places severe demands on subsequent lithography and etching processes for forming the electronic circuitry. The use of a circuitry-first approach, however, is disadvantageous in requiring deviations from standard processing steps (i.e. process modifications), especially in requiring the use of tungsten instead of aluminum for the interconnect metallization to withstand a high-temperature annealing step required to at least partially relieve stress in polysilicon elements (e.g. cantilevered beams) of MEM devices. However, the use of tungsten as an interconnect metallization is not altogether satisfactory, resulting in additional problems including a high contact resistance and hillock formation that can lead to inadequate protection of the electronic circuitry during release of the MEM devices. Additional problems known to occur with this circuitry-first approach include an undesirable formation of tungsten silicides, and poor adhesion of the tungsten interconnect metallization.
An advantage of the method of the present invention is that microelectromechanical (MEM) devices can be integrated with electronic circuitry on a substrate while using standard process steps with little if any modification for fabricating the electronic circuitry, including the use of an aluminum interconnect metallization in preferred embodiments of the present invention.
Another advantage of the present invention is that one or more MEM devices can be fabricated prior to fabrication of electronic circuitry, with the MEM devices being encapsulated to prevent contamination of a device surface of the substrate.
A further advantage of the present invention is that the substrate can be planarized prior to formation of the electronic circuitry thereby providing a substantially smooth and planar surface topography for subsequent process steps for fabricating the electronic circuitry.
Still another advantage of the present invention is that the encapsulated MEM devices can be annealed under temperature and time conditions sufficient to relieve strain in elements of the MEM devices prior to formation of the electronic circuitry including the interconnect metallization.
Yet another advantage is that by providing one or more encapsulated MEM devices formed within a cavity below a device surface of a planarized substrate, the substrate can be handled and processed thereafter using substantially standard process steps with little if any modification for forming the electronic circuitry (including the interconnect metallization).
Another advantage of the present invention is that the electronic circuitry can be protected during an etching step for releasing the encapsulated MEM device by covering the electronic circuitry with a layer of deposited tungsten that can be removed without damaging the underlying electronic circuitry after the MEM device is released.
Yet another advantage of the method of the present invention is that packaging of both MEM and integrated devices (i.e. MEM devices integrated with electronic circuitry) can be simplified and cost reduced by forming one or more of the MEM devices below a device surface of a substrate with an overlying layer forming at least a part of an enclosure for packaging the devices.
These and other advantages of the method of the present invention will become evident to those skilled in the art.
The present invention relates to a method for integrating one or more microelectromechanical (MEM) devices with electronic circuitry on a common substrate. The method comprises steps for etching a cavity within a first portion of the substrate; fabricating the MEM device within the cavity, and filling the cavity with one or more layers of a sacrificial material; fabricating the electronic circuitry comprising a plurality of transistors within a second portion of the substrate proximate to the first portion, and interconnecting the electronic circuitry to the MEM device; protecting the electronic circuitry by depositing a layer of tungsten to blanket the second portion of the substrate and to cover the electronic circuitry; and releasing the MEM device for operation thereof by removing at least a portion of the sacrificial material filling the cavity by etching the sacrificial material with a first wet etchant which does not substantially remove the layer of tungsten protecting the electronic circuitry. In preferred embodiments of the present invention, the step for protecting the electronic circuitry further comprises a step for depositing an adhesion layer (e.g. comprising titanium nitride) over the second portion of the substrate prior to the step for depositing the layer of tungsten. The method of the present invention can further comprise a step for removing the layer of tungsten (and the adhesion layer, if present) after the step for releasing the MEM device.
The substrate preferably comprises silicon; and the step for etching the cavity within the first portion of the substrate can comprise either etching the cavity into the substrate, or etching the cavity into one or more semiconductor layers formed on the substrate. The step for fabricating the MEM device can comprise steps for depositing, patterning and etching layers of one or more micromachineable materials selected from the group consisting of polycrystalline silicon (also termed polysilicon), silicon dioxide, silicon nitride, silicate glass, metals and metal alloys. The step for filling the cavity with a sacrificial material preferably comprises depositing a silicate glass within the cavity.
In preferred embodiments of the present invention, the step for fabricating the MEM device can include a step for annealing the MEM device, thereby relieving stress in the MEM device. The step for fabricating the MEM device can further include a step for planarizing the substrate (e.g. by a chemical-mechanical polishing step) prior to the step for fabricating the electronic circuitry.
Additional advantages and novel features of the invention will become apparent to those skilled in the art upon examination of the following detailed description thereof when considered in conjunction with the accompanying drawings. The advantages of the invention can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The accompanying drawings, which are incorporated into and form a part of the specification, illustrate several aspects of the present invention and, together with the description, serve to explain the principles of the invention. The drawings are only for the purpose of illustrating preferred embodiments of the invention and are not to be construed as limiting the invention. In the drawings:
FIG. 1 shows a schematic cross-sectional representation of an integrated device 10 having one or more MEM devices integrated with electronic circuitry according to the method of the present invention.
FIGS. 2-13 show schematic cross-section representations of the integrated device of FIG. 1 during various process steps for forming the integrated device.
The fabrication method of the present invention combines processes for fabricating one or more microelectromechanical (MEM) devices with processes for fabricating electronic circuitry in a mutually compatible manner. The electronic circuitry can comprise complementary metal-oxide semiconductor (CMOS) transistors, bipolar complementary metal-oxide semiconductor (BiCMOS) transistors, or bipolar transistors. The integration of the MEM devices with electronic circuitry provides added functionality for driving and control of microactuators (i.e. MEM devices providing some form of actuation, including linear and rotary motors, gears, levers, linkages and the like) and provides a means for amplifying and/or processing (including compensation, linearization, and control) of sensory signals generated by microsensors (i.e. MEM devices responding to some form of external applied stimuli, including accelerometers, pressure sensors, flow sensors, chemical sensors, optical sensors, resonant oscillators and the like). Such integration provides advantages in terms of increased functionality and sensitivity, and reduced size and cost as compared to MEM devices being formed on a separate chip from the electronic circuitry.
Referring to FIG. 1, there is shown a schematic cross-section representation of an example of an integrated device 10 comprising at least one microelectromechanical (MEM) device 12 fabricated on a first portion of a common substrate 14 and electrically connected to electronic circuitry 16 fabricated on a second portion on the substrate proximate to the first portion. In the example of FIG. 1, the first portion of the substrate 14 lies below the bracket and label "Microelectromechanical Device 12"; whereas the second portion lies below the bracket and label "Electronic Circuitry 16".
The process steps for forming such an integrated device 10 in the example of FIG. 1 are shown in FIGS. 2-13, and described hereinafter. Although the example of the MEM device 12 is described in FIGS. 1-13 as being formed within a cavity 20, it will be understood by those skilled in the art that, in some embodiments of the present invention, the completed MEM device 12 can extend upward beyond the cavity 20. In particular, for forming pressure sensors, a moveable pressure sensing diaphragm can be formed over the cavity 20 to cover and seal the cavity 20, with polysilicon piezoresistors then being formed above the pressure diaphragm for measuring changes in pressure or vacuum. Thus, although the MEM device 12 is generally described as being located within the cavity 20, in some instances, the cavity 20 itself can form a part of the MEM device 12, as in the case of a pressure sensor.
In FIG. 2, a substrate 14 is provided for formation of the integrated device 10. The substrate 14 preferably comprises a monocrystalline silicon wafer or a portion thereof. The substrate 14 can be undoped, or n- or p-type doped depending on a predetermined set of standard processes (and including design rules) to be used for forming the electronic circuitry 16. As an example, an n-type doped substrate 14 can be preferred for forming electronic circuitry 16 by a set of standard CMOS process steps having 2-micron (μm) design rules (i.e. a 2-μm minimum feature size). As another example, a p-type doped substrate can be preferred for forming electronic circuitry 16 by another set of standard CMOS processing steps having 0.5-μm design rules. The substrate 14 can further include one or more semiconductor layers formed or epitaxially deposited thereon (including doped layers) with a total layer thickness of about 2-10 μm or more for providing a smooth low-defect-density device surface 18 for formation of the electronic circuitry 16. (A buried doped epitaxial layer can be provided for forming BiCMOS or bipolar transistors for forming the electronic circuitry 16.)
In FIG. 2, one or more open cavities 20 are etched into the device surface 18 of the substrate at predetermined locations (i.e. the first portion of the substrate) wherein each MEM device 12 is to be fabricated. The size of each cavity 20 including its length, width and depth, will in general depend on the particular type of MEM device 12 to be formed. The length and width can each be on the order of one millimeter, for example, and the depth can be in the range of about 2-20 μm.
Each cavity 20 is preferably formed by a bulk micromachining process after providing a patterned first masking layer (e.g. about 500 nanometers of a silicate glass deposited from the decomposition of tetraethylortho silicate, also termed TEOS, that has been densified by heating to a high temperature for a specified period of time) covering the device surface 18 with openings at the locations of each cavity to be formed. Each cavity 20 is then etched into the substrate using a wet and/or dry etching process. A preferred etching process uses an anisotropic wet etchant such as potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH) or ethylenediamine pyrocatechol (EDP) to form one or more cavities 20 that can be, for example, about 2-20 μm or more deep with a substantially planar bottom surface and sloping inner sidewalls formed by selective etching along preferred (111) crystallographic planes as shown in FIG. 2. The use of an anisotropic etchant can be advantageous for providing improved optical access to the bottom surface of each cavity thereby providing an increased latitude for subsequent photolithography steps for forming elements of the MEM structure within each cavity (including providing alignment marks on the bottom surface of the cavity). After formation of one or more cavities on the substrate, the patterned first masking layer can be removed with a wet etchant comprising HF.
In FIG. 3, a first silicon nitride layer 22 is deposited to blanket the device surface 18 and each cavity 20 after first forming a thin blanket layer of a thermal oxide (approximately 60 nanometers of silicon dioxide formed by a thermal diffusion process) to protect the bare silicon from exposure to the first silicon nitride layer 22. The first silicon nitride layer 22 can be up to about 200-300 nanometers thick, and is preferably formed by a low-pressure chemical vapor deposition (CVD) process that produces low residual stress in the first silicon nitride layer 22. The portion of the first silicon nitride layer 22 extending above the device surface 18 can later be used as a stop for a chemical-mechanical polishing process for planarizing a top side of the substrate; and the remainder of the first silicon nitride layer 22 covering the inner surfaces of each cavity 20 serves as a dielectric isolation layer, and also as an etch stop during an etching step for releasing the MEM device 12 after fabrication of the electronic circuitry.
In FIG. 4, one or more MEM devices 12 are formed within each cavity 20 in the first portion of the substrate 14, with the MEM devices 12 preferably being located substantially below the device surface 18 of the substrate 14. Formation of the MEM devices can include surface and bulk micromachining processes as known to the art. In surface micromachining processes, for example, one or more thin films (up to a few microns thick) of micromachineable materials such as polysilicon, silicon nitride (also termed nitride), silicon dioxide (also termed oxide), metals (e.g. tungsten, gold, copper, platinum, nickel, palladium), metal alloys (including metal silicides) and the like can be deposited within the cavity through patterned masking layers and anisotropically etched to form the MEM devices 12. One or more sacrificial layers comprising a sacrificial material such as silicon dioxide or one or more silicate glasses as can be deposited by a CVD process. After formation of the electronic circuitry 16 on the second portion of the substrate 14, the sacrificial material can be removed, at least in part, from each cavity 20 for releasing the MEM devices 12 for movement or operation. Bulk micromachining processes including LIGA (a German acronym taken from words referring to lithography, electroplating and injection molding) can be used to form MEM devices 12 having larger vertical dimensions (up to 300 μm or more), and with minimum feature sizes down to about 2 μm.
FIG. 4 shows an example of a MEM device 12 comprising a first-deposited polysilicon layer 24 that is preferably doped (e.g. by an ion implantation and/or thermal diffusion step, or in-situ by chemical vapor deposition) and patterned for forming a voltage reference plane and for providing electrical interconnections between elements of the MEM device. In FIG. 4, additional polysilicon layers can be deposited and patterned by any conventional method to form one or more fixed support beams 26, moveable support beams (not shown), electrical interconnection studs 28, or the like having predetermined forms or shapes depending on a particular MEM device 12 to be fabricated. A single additional polysilicon layer can be provided above the first polysilicon layer 24 when simple MEM devices 12 such as accelerometers based on capacitively-coupled cantilevered beams are to be formed according to the present invention.
For more complex MEM devices, however, further polysilicon layers are generally required. For example, a preferred process for forming complex, interconnected, interactive, microactuated MEM devices 12 having springs, linkages, mass elements, joints and the like generally requires the deposition and patterning of three additional layers of polysilicon above the first polysilicon layer 24, with each of the polysilicon layers being separated by a sacrificial layer (e.g. a thin oxide or silicate glass layer) and/or by a friction-reduction nitride layer (e.g. for forming bearing surfaces for moveable elements such as gears, rotors, levers, linkages etc.). This preferred three-layer process is advantageous for mechanically interconnecting elements of a MEM device 12 by hard linkages for actuation, or for coupling mechanical energy via micromachined gears, levers, linkages or the like. Furthermore, since each polysilicon layer can be selectively doped for use as an electrical conductor, this preferred three-layer process provides additional flexibility for electrical interconnections and/or electrodes. The additional polysilicon layers can be deposited, at least in part, through one or more patterned sacrificial layers 30 for defining a shape of the MEM elements, and for forming anchor portions for mechanical and electrical connection to the first-deposited polysilicon layer 24.
In FIG. 5, after formation of the MEM devices 12 (with the polysilicon layers being formed into their final shapes to define elements of the MEM devices), one or more additional sacrificial layers 32 (comprising the same or different sacrificial materials such as silicon dioxide or silicate glasses that can be later removed by selective etching) can be deposited to fill the cavity 20 and completely bury or encapsulate the MEM devices 12. The steps for depositing the sacrificial material to fill the cavity 20 provide for protection of the MEM devices 12 within the cavity and/or for planarization of the cavity 20 and the substrate 14. The sacrificial layers 30 and 32 can be grown or deposited in a conventional manner (e.g. by CVD wherein an oxide or silicate glass layer-forming gas is decomposed to form the layers 30; or by plasma-enhanced CVD, also termed PECVD, wherein applied rf power is provided to assist the decomposition for deposition at a low temperature of about 600° C. or less), with each layer thickness being tailored to particular requirements of the MEM devices 12 being formed.
The additional sacrificial layers 32 are preferably deposited so as to extend upward beyond the device surface 18 and most preferably beyond the first silicon nitride layer 22 as shown in FIG. 5, thereby allowing a step for planarizing the substrate. In FIG. 6, the substrate planarization step is preferably performed by chemical-mechanical polishing a top side of the substrate. To reduce the time required for chemical-mechanical polishing of the substrate, a preferable method for planarizing the substrate is to mask the first region of the substrate 14 above the cavity 20 with a mask layer (e.g. a patterned photoresist layer) and to remove the sacrificial layers 30 and 32 covering the remainder of the substrate 14 by a dry etching step. During the substrate planarization step, the first silicon nitride layer 22 is preferably used as a polishing stop to limit a downward extent of the chemical-mechanical polishing, thereby providing a substantially planar upper surface for the substrate. After the chemical-mechanical polishing step, the silicon nitride layer 22 in acting as a polishing stop can be reduced to about 100-300 nanometers thickness.
After planarization of the substrate 14, a second silicon nitride layer (i.e. a cap layer) 34 can be deposited over the planar upper surface of the substrate covering the remaining portion of the first silicon nitride layer 22 and any exposed portions of the sacrificial layers 30 and 32, thereby forming a nitride-to-nitride seal for sealing the encapsulated MEM devices 12. After this sealing step has been performed, the electronic circuitry 16 can be fabricated within the second portion of the substrate 14 according to conventional methods (i.e. standard process steps with little if any modification thereof as known to the art for forming CMOS, BiCMOS, or bipolar transistors). The sealed substrate can even be shipped to a foundry or other entity for fabrication of the electronic circuitry 16 by a set of standard process steps.
Since any stress within elements of the MEM devices 12 (e.g. polysilicon cantilevered beams) can be detrimental to operation of the device, an annealing step for relieving the stress is preferably performed. This annealing step can be performed before fabrication of the electronic circuitry 16 by heating the substrate and encapsulated MEM devices to a preselected temperature in the range of about 700-1300° C. for a time period of up to about three hours or more depending upon the level of stress to be relieved. Alternately, the annealing step can be performed during a thermal cycle used for fabricating the electronic circuitry 16 (e.g one or more thermal diffusion steps for forming transistors).
In some cases, the formation of the electronic circuitry 16 can begin immediately after planarizing the substrate 14, with the second silicon nitride layer 34 being deposited during a standard process step for forming the electronic circuitry 16. In this case shown schematically in FIGS. 7-13 and described hereinafter with reference to a preferred process for forming CMOS circuitry 16 (i.e. circuitry comprising a plurality of complementary metal-oxide semiconductor transistors), the first silicon nitride layer 22 and the underlying thermal oxide are preferably removed by etching in the second portion of the substrate (see FIG. 7) to provide a bare portion of the substrate 14 upon which new thermal oxide and silicon nitride layers can be formed with precise thicknesses for carrying out a set of standard processes for forming the CMOS circuitry 16. For certain interconnect metallization schemes, this process of removing the first silicon nitride layer 22 and the underlying oxide and forming the new thermal oxide and silicon nitride layers is to be preferred for reducing or eliminating metallization step coverage problems. During these standard process steps for forming the electronic circuitry 16, openings can also be made to each polysilicon stud 28 as shown in FIG. 7 for later use in forming electrical interconnections between the electronic circuitry 16 and each MEM device 12.
In FIG. 8, after formation of a new thermal oxide layer (about 30-40 nanometers thick) on the exposed device surface 18, a second silicon nitride layer 34 (i.e. the new silicon nitride layer which is also termed a cap layer) can then be deposited over the entire upper surface of the wafer 14 to a layer thickness of about 120 nanometers, for example, for use in forming the CMOS circuitry 16 and also for use in sealing the cavity 20 containing the encapsulated MEM device 12. In FIG. 9, openings can be formed through the second silicon nitride layer 34 for forming n-type and p-type isolation wells (also termed tubs) by ion implantation and thermal diffusion steps. Subsequent standard CMOS process steps can be used for forming n-type transistors 36 within the p-type wells, and for forming p-type transistors 38 within the n-type wells. Such standard CMOS process steps can include the deposition and patterning of one or more polysilicon layers for forming transistor gates and resistors 40; and the deposition and patterning of a plurality of passivation layers 42 (including, for example, a field oxide layer of CVD silicon dioxide and overlying layers of one or more silicate glasses such as TEOS; phosphorous silicate glass, also termed PSG; or borophosphorous silicate glass, also termed BPSG deposited by CVD or PECVD).
In FIG. 10, one or more layers of an interconnect metallization 44 are provided by standard deposition and patterning steps to interconnect elements (e.g. transistors, resistors, capacitors) forming the electronic circuitry 16, to provide electrical interconnections to the MEM device 12 via the polysilicon studs 28, and to provide a plurality of bonding or contact pads (not shown) for providing electrical connections to form a packaged integrated device 10. The interconnect metallization 44 is considered herein to form a part of the electronic circuitry 16.
Aluminum or an alloy thereof is preferred for use as the interconnect metallization 44, although other metals (e.g tungsten, gold, copper, platinum, nickel, palladium), metal alloys (including metal silicides) and even doped polysilicon can be used for the electrical interconnections depending upon operating requirements for the integrated devices 10, and a particular set of standard process steps to be used for practice of the present invention. Additional passivation layers (e.g. about 200 nanometers of a silicate glass such as plasma-enhanced TEOS, also termed PETEOS) can be provided to separate a plurality of layers of the interconnect metallization 44 (not shown in FIG. 10), and to blanket the electronic circuitry 16 and interconnect metallization for environmental protection and stress relief.
After fabrication of the electronic circuitry is substantially completed, a protection layer 46 preferably comprising tungsten is deposited to blanket the second portion of the substrate 14 and cover the electronic circuitry 16 for protection of the electronic circuitry 16 during an etch release process step whereby the MEM device 12 is exposed to an etchant for removing the sacrificial material, at least in part, and releasing the MEM device 12 into its final suspended state for movement or operation. As shown in FIG. 11, the protection layer 46 can also be deposited to blanket the first portion of the substrate 14 containing the MEMS device 12, with one or more etch channels 48 being formed (e.g. by photolithographic patterning and etching) through the protection layer 46 and the second silicon nitride layer 34 to expose the sacrificial material for removal by etching.
The use of a tungsten protection layer 46 is especially preferred when an wet etchant comprising, at least in part, hydrofluoric acid (HF). Particular etchant compositions that can be used according to the present invention for releasing the MEMS device 12 include mixtures of hydrofluoric acid (HF) and hydrochloric acid (HCI), and mixtures of HF and water (H2 O). The exact proportions of the constituents in each mixture will depend upon a predetermined etching rate for the sacrificial material which can be determined from practice of the present invention. Such HF:HCI or HF:H2 O wet etchants are advantageous for etching the sacrificial material at a much faster rate as compared with a buffered oxide etchant, thereby substantially reducing the time required for releasing the MEM devices 12. However, use of the HF:HCI or HF:H2 O wet etchants require more substantial protection for the electronic circuitry 16 than is provided by a photoresist protection layer 46 which is generally sufficient for the buffered oxide etchant.
A preferred method for forming the protection layer 46 according to the present invention is to initially deposit (e.g. by sputtering or CVD) a thin layer (e.g. about 50 nanometers thick) of titanium nitride (TiN) over the substrate 14 as an adhesion layer, and then to deposit a thicker layer (e.g. about 0.1-1 microns thick) of tungsten (W) over the titanium nitride layer (e.g. by CVD using WF6 as a source gas). This forms a two-ply protection layer 46 which has a substantial chemical resistance to the HF:HCI or HF:H2 O wet etchants, thereby protecting the electronic circuitry 16 from exposure to the wet etchants which could damage the electronic circuitry 16. The TiN:W protection layer 46 can be removed after the etch release step described hereinafter without damaging the electronic circuitry 16 by exposing the tungsten and titanium nitride layers to another wet etchant having a chemical composition different from the chemical composition of the wet etchant used for releasing the MEM device 12. This wet etchant for removing the TiN:W protection layer 46 can comprise hydrogen peroxide, for example.
FIG. 12 shows the substrate 14 with integrated MEM device 12 and electronic circuitry 16 after the etch release step in which the sacrificial material (e.g. sacrificial layers 30 and 32) is removed at least in part by the HF:HCI wet etchant or by the HF:H2 O wet etchant. These wet etchant compositions dissolve the sacrificial material, but preferably do not substantially affect (i.e. attack) any other materials (e.g. polysilicon, silicon nitride or metals) used to form the MEM device 12. In order to remove all of the sacrificial material, the etch release step can proceed for up to an hour or longer, depending upon the size, number and location of etch channels 48 provided.
Alternately, the wet etching process step can be limited in time duration so that some of the sacrificial material is left to support the polysilicon studs 28 and/or other fixed structural elements of the MEM devices. In this latter case, factors of the etch release process including the position, number and size of the etch channels 48; the chemical composition of the etchant; and the time for etching can be selected to limit a lateral extent of etching of the sacrificial material, thereby leaving portions of the sacrificial material surrounding the polysilicon studs 28 or the other fixed structural elements of the MEM devices 12.
After this etch release step, the substrate is then preferably washed in a rinse fluid for cleansing thereof, and is dried preferably using one of the stiction-free drying methods known to the art. Additionally, the released MEM devices 12 can be exposed to a stiction-prevention agent as known to the art for reducing possibility for stiction of moveable elements (e.g. cantilevered beams) of the MEM devices 12 during the drying step or afterwards.
The etch channels 48 in FIGS. 11 and 12 can range in size from about 1-1000 μm diameter depending on the particular type of MEM device 12 to be formed and also on whether one or more of the etch channels 48 will later be plugged by a deposition step for forming a sealed cavity (e.g. for providing a predetermined level of pressure or vacuum therein, or for forming a pressure sensing diaphragm above the cavity for sensing an ambient or applied pressure or vacuum); or for providing a protected enclosure for the MEM devices, thereby simplifying packaging. This process step for plugging one or more of the etch channels according to some embodiments of the present invention is shown in FIG. 13. By plugging the etch channels 48 with plugs 50 of a deposited material such as PECVD silicon nitride, the MEM devices can be sealed under a near-vacuum condition (about 200 Torr pressure). Alternately, the step of plugging the etch channels 48 can be carried out by sputtering or evaporating a metal (e.g. aluminum), or by low-temperature deposition of a plasma-enhanced oxide or silicate glass.
In some embodiments of the present invention, polysilicon piezoresistors can be formed over a pressure diaphragm formed above the MEM devices by the plugged nitride layer 34 for measuring changes in pressure or vacuum. These process steps for sealing the MEM devices 12 can also be advantageous for packaging the integrated device 10 since the sealed MEM device 12 (with or without plugs 50) is protected from the environment outside the cavity 20, thereby preventing the possibility of damage from dust, and also minimizing possible damage from handling, testing and packaging. The completed device 10 with one or more sealed MEM devices 12 integrated with electronic circuitry 16 can be packaged by any means known to the art including the use of relatively inexpensive molded packages formed of plastics, epoxy or the like.
The matter set forth in the foregoing description and accompanying drawings is offered by way of illustration only and not as a limitation. Other applications and variations of the method for integrating microelectromechanical devices with electronic circuitry will become evident to those skilled in the art. The actual scope of the invention is intended to be defined in the following claims when viewed in their proper perspective based on the prior art.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4562092 *||30 Oct 1984||31 Dec 1985||Fine Particle Technology Corporation||Method of fabricating complex microcircuit boards, substrates and microcircuits and the substrates and microcircuits|
|US4859629 *||14 Dec 1987||22 Aug 1989||M/A-Com, Inc.||Method of fabricating a semiconductor beam lead device|
|US5095401 *||21 May 1990||10 Mar 1992||Kopin Corporation||SOI diaphragm sensor|
|US5227335 *||30 Apr 1990||13 Jul 1993||At&T Bell Laboratories||Tungsten metallization|
|US5242839 *||25 Nov 1992||7 Sep 1993||Electronics And Telecommunications Research Institute||Method of manufacturing an integrated photoelectric receiving device|
|US5260596 *||8 Apr 1991||9 Nov 1993||Motorola, Inc.||Monolithic circuit with integrated bulk structure resonator|
|US5314572 *||22 Apr 1992||24 May 1994||Analog Devices, Inc.||Method for fabricating microstructures|
|US5326726 *||21 Jun 1993||5 Jul 1994||Analog Devices, Inc.||Method for fabricating monolithic chip containing integrated circuitry and suspended microstructure|
|US5345824 *||4 Mar 1993||13 Sep 1994||Analog Devices, Inc.||Monolithic accelerometer|
|US5399415 *||4 Jun 1993||21 Mar 1995||Cornell Research Foundation, Inc.||Isolated tungsten microelectromechanical structures|
|US5412265 *||5 Apr 1993||2 May 1995||Ford Motor Company||Planar micro-motor and method of fabrication|
|US5417111 *||10 Jun 1993||23 May 1995||Analog Devices, Inc.||Monolithic chip containing integrated circuitry and suspended microstructure|
|US5427975 *||10 May 1993||27 Jun 1995||Delco Electronics Corporation||Method of micromachining an integrated sensor on the surface of a silicon wafer|
|US5431051 *||29 Mar 1994||11 Jul 1995||Siemens Aktiengesellschaft||Tunnel effect acceleration sensor|
|US5431057 *||18 Feb 1994||11 Jul 1995||Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V.||Integratable capacitative pressure sensor|
|US5455203 *||11 Feb 1993||3 Oct 1995||Seiko Instruments Inc.||Method of adjusting the pressure detection value of semiconductor pressure switches|
|US5493177 *||26 Oct 1993||20 Feb 1996||The Regents Of The University Of California||Sealed micromachined vacuum and gas filled devices|
|US5504026 *||14 Apr 1995||2 Apr 1996||Analog Devices, Inc.||Methods for planarization and encapsulation of micromechanical devices in semiconductor processes|
|US5550090 *||5 Sep 1995||27 Aug 1996||Motorola Inc.||Method for fabricating a monolithic semiconductor device with integrated surface micromachined structures|
|US5798283 *||6 Sep 1995||25 Aug 1998||Sandia Corporation||Method for integrating microelectromechanical devices with electronic circuitry|
|US5814554 *||21 Nov 1995||29 Sep 1998||U.S. Philips Corporation||Semiconductor device provided with a microcomponent having a fixed and a movable electrode|
|JPH04357854A *||Title not available|
|1||P. J. Ireland, "High Aspect Ratio Contacts: A Review of the Current Tungsten Plug Process," Thin Solid Films, vol. 304, pp. 1-12, 1997.|
|2||*||P. J. Ireland, High Aspect Ratio Contacts: A Review of the Current Tungsten Plug Process, Thin Solid Films , vol. 304, pp. 1 12, 1997.|
|3||R. T. Howe, "Polysilicon Integrated Microsystems: Technologies and Applications," Digest of Technical Papers for the 8th International Conference on Solid-State Sensors and Actuators and Eurosensors IX, Stockholm, Sweden, Jun. 25-29, 1995, vol. 1, pp. 43-46, 1995.|
|4||*||R. T. Howe, Polysilicon Integrated Microsystems: Technologies and Applications, Digest of Technical Papers for the 8th International Conference on Solid State Sensors and Actuators and Eurosensors IX , Stockholm, Sweden, Jun. 25 29, 1995, vol. 1, pp. 43 46, 1995.|
|5||*||S. Wolf, Silicon Processing fro the VLSI Era, vol. 2, pp. 247 251, 1990.|
|6||S. Wolf, Silicon Processing fro the VLSI Era, vol. 2, pp. 247-251, 1990.|
|7||W. Kuehnel and S. Sherman, "A Surface Micromachined Silicon Accelerometer with On-Chip Detection Circuitry," Sensors and Acuators A, vol. 45, pp. 7-16, 1994.|
|8||*||W. Kuehnel and S. Sherman, A Surface Micromachined Silicon Accelerometer with On Chip Detection Circuitry, Sensors and Acuators A, vol. 45, pp. 7 16, 1994.|
|9||W. Riethmuller, W. Benecke, U. Schnakenberg, and B. Wagner, "A Smart Accererometer with On-Chip Electronics Fabricated by a Commercial CMOS Process," Sensors and Actuators A, vol. 31, pp. 121-124, 1992.|
|10||*||W. Riethmuller, W. Benecke, U. Schnakenberg, and B. Wagner, A Smart Accererometer with On Chip Electronics Fabricated by a Commercial CMOS Process, Sensors and Actuators A, vol. 31, pp. 121 124, 1992.|
|11||*||W. Yun, CMOS Metallization for Integration with Micromachining Processes, Thesis for Master of Science Degree in Electrical Engineering from the University of California, Berkley, May 19, 1989.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6077784 *||11 Aug 1998||20 Jun 2000||United Microelectronics Corp.||Chemical-mechanical polishing method|
|US6136630 *||3 Jun 1999||24 Oct 2000||The Regents Of The University Of Michigan||Method of making a micromechanical device from a single crystal semiconductor substrate and monolithic sensor formed thereby|
|US6174820 *||16 Feb 1999||16 Jan 2001||Sandia Corporation||Use of silicon oxynitride as a sacrificial material for microelectromechanical devices|
|US6184054 *||27 Nov 1998||6 Feb 2001||Miracle Technology Co., Ltd.||Optical electronic IC capable of photo detection and its process|
|US6271052||19 Oct 2000||7 Aug 2001||Axsun Technologies, Inc.||Process for integrating dielectric optical coatings into micro-electromechanical devices|
|US6301965||14 Dec 1999||16 Oct 2001||Sandia Corporation||Microelectromechanical accelerometer with resonance-cancelling control circuit including an idle state|
|US6335224||16 May 2000||1 Jan 2002||Sandia Corporation||Protection of microelectronic devices during packaging|
|US6350015||24 Nov 2000||26 Feb 2002||Xerox Corporation||Magnetic drive systems and methods for a micromachined fluid ejector|
|US6355534 *||26 Jan 2000||12 Mar 2002||Intel Corporation||Variable tunable range MEMS capacitor|
|US6367915||28 Nov 2000||9 Apr 2002||Xerox Corporation||Micromachined fluid ejector systems and methods|
|US6392144||1 Mar 2000||21 May 2002||Sandia Corporation||Micromechanical die attachment surcharge|
|US6406130||20 Feb 2001||18 Jun 2002||Xerox Corporation||Fluid ejection systems and methods with secondary dielectric fluid|
|US6409311||24 Nov 2000||25 Jun 2002||Xerox Corporation||Bi-directional fluid ejection systems and methods|
|US6416169||24 Nov 2000||9 Jul 2002||Xerox Corporation||Micromachined fluid ejector systems and methods having improved response characteristics|
|US6419335||24 Nov 2000||16 Jul 2002||Xerox Corporation||Electronic drive systems and methods|
|US6429458 *||31 Jul 2000||6 Aug 2002||The Regents Of The University Of Michigan||Method of making a micromechanical device from a single crystal semiconductor substrate and monolithic sensor formed thereby|
|US6437965||28 Nov 2000||20 Aug 2002||Harris Corporation||Electronic device including multiple capacitance value MEMS capacitor and associated methods|
|US6440766||7 Jul 2000||27 Aug 2002||Analog Devices Imi, Inc.||Microfabrication using germanium-based release masks|
|US6448103 *||30 May 2001||10 Sep 2002||Stmicroelectronics, Inc.||Method for making an accurate miniature semiconductor resonator|
|US6472332||28 Nov 2000||29 Oct 2002||Xerox Corporation||Surface micromachined structure fabrication methods for a fluid ejection device|
|US6503775 *||21 Sep 2001||7 Jan 2003||Aisin Seiki Kabushiki Kaisha||Production method of a micromachine|
|US6511859||10 Mar 2000||28 Jan 2003||California Institute Of Technology||IC-compatible parylene MEMS technology and its application in integrated sensors|
|US6513898 *||23 Jun 1998||4 Feb 2003||Stmicroelectronics S.R.L.||Integrated inkjet print head and manufacturing process thereof|
|US6521965 *||12 Sep 2000||18 Feb 2003||Robert Bosch Gmbh||Integrated pressure sensor|
|US6528887||1 Mar 2001||4 Mar 2003||Onix Microsystems||Conductive equipotential landing pads formed on the underside of a MEMS device|
|US6531331||16 Jul 2002||11 Mar 2003||Sandia Corporation||Monolithic integration of a MOSFET with a MEMS device|
|US6534413 *||27 Oct 2000||18 Mar 2003||Air Products And Chemicals, Inc.||Method to remove metal and silicon oxide during gas-phase sacrificial oxide etch|
|US6586841||10 Apr 2000||1 Jul 2003||Onix Microsystems, Inc.||Mechanical landing pad formed on the underside of a MEMS device|
|US6600587||23 Apr 2001||29 Jul 2003||Memx, Inc.||Surface micromachined optical system with reinforced mirror microstructure|
|US6611033||12 Apr 2001||26 Aug 2003||Ibm Corporation||Micromachined electromechanical (MEM) random access memory array and method of making same|
|US6696364 *||8 Aug 2002||24 Feb 2004||Stmicroelectronics S.R.L.||Method for manipulating MEMS devices, integrated on a wafer semiconductor and intended to be diced one from the other, and relevant support|
|US6707591||15 Aug 2001||16 Mar 2004||Silicon Light Machines||Angled illumination for a single order light modulator based projection system|
|US6712480||27 Sep 2002||30 Mar 2004||Silicon Light Machines||Controlled curvature of stressed micro-structures|
|US6727436||15 Mar 2002||27 Apr 2004||Memx, Inc.||Interconnect bus crossover for MEMS|
|US6728023||28 May 2002||27 Apr 2004||Silicon Light Machines||Optical device arrays with optimized image resolution|
|US6731513||15 Mar 2002||4 May 2004||Memx, Inc.||Shielded multi-conductor interconnect bus for MEMS|
|US6747340||15 Mar 2002||8 Jun 2004||Memx, Inc.||Multi-level shielded multi-conductor interconnect bus for MEMS|
|US6747781||2 Jul 2001||8 Jun 2004||Silicon Light Machines, Inc.||Method, apparatus, and diffuser for reducing laser speckle|
|US6753205||27 Jan 2003||22 Jun 2004||Tru-Si Technologies, Inc.||Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity|
|US6756317||23 Apr 2001||29 Jun 2004||Memx, Inc.||Method for making a microstructure by surface micromachining|
|US6762116 *||12 Jun 2002||13 Jul 2004||Zyvex Corporation||System and method for fabricating microcomponent parts on a substrate having pre-fabricated electronic circuitry thereon|
|US6764875||24 May 2001||20 Jul 2004||Silicon Light Machines||Method of and apparatus for sealing an hermetic lid to a semiconductor die|
|US6764936||23 Jul 2001||20 Jul 2004||Onix Microsystems, Inc.||Mechanical landing pad formed on the underside of a MEMS device|
|US6767751||28 May 2002||27 Jul 2004||Silicon Light Machines, Inc.||Integrated driver process flow|
|US6778305||8 Apr 2003||17 Aug 2004||Memx, Inc.||Surface micromachined optical system with reinforced mirror microstructure|
|US6778306||5 May 2003||17 Aug 2004||Memx, Inc.||Surface micromachined optical system with reinforced mirror microstructure|
|US6781208||9 Aug 2002||24 Aug 2004||Nec Corporation||Functional device, method of manufacturing therefor and driver circuit|
|US6782205||15 Jan 2002||24 Aug 2004||Silicon Light Machines||Method and apparatus for dynamic equalization in wavelength division multiplexing|
|US6787384||3 Sep 2003||7 Sep 2004||Nec Corporation||Functional device, method of manufacturing therefor and driver circuit|
|US6787916||13 Sep 2001||7 Sep 2004||Tru-Si Technologies, Inc.||Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity|
|US6788520||28 Nov 2000||7 Sep 2004||Behrang Behin||Capacitive sensing scheme for digital control state detection in optical switches|
|US6790698||18 Sep 2001||14 Sep 2004||Axsun Technologies, Inc.||Process for integrating dielectric optical coatings into micro-electromechanical devices|
|US6791730||8 Apr 2003||14 Sep 2004||Memx, Inc.||Surface micromachined optical system with reinforced mirror microstructure|
|US6794213 *||5 Aug 2003||21 Sep 2004||The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration||Method of assembling a silicon carbide high temperature anemometer|
|US6800238||15 Jan 2002||5 Oct 2004||Silicon Light Machines, Inc.||Method for domain patterning in low coercive field ferroelectrics|
|US6801354||20 Aug 2002||5 Oct 2004||Silicon Light Machines, Inc.||2-D diffraction grating for substantially eliminating polarization dependent losses|
|US6806997||28 Feb 2003||19 Oct 2004||Silicon Light Machines, Inc.||Patterned diffractive light modulator ribbon for PDL reduction|
|US6813057||27 Sep 2001||2 Nov 2004||Memx, Inc.||Configurations for an optical crossconnect switch|
|US6813059||28 Jun 2002||2 Nov 2004||Silicon Light Machines, Inc.||Reduced formation of asperities in contact micro-structures|
|US6819820||18 Aug 2001||16 Nov 2004||Analog Devices, Inc.||Use of applied force to improve MEMS switch performance|
|US6822797||31 May 2002||23 Nov 2004||Silicon Light Machines, Inc.||Light modulator structure for producing high-contrast operation using zero-order light|
|US6824278||15 Mar 2002||30 Nov 2004||Memx, Inc.||Self-shadowing MEM structures|
|US6829077||28 Feb 2003||7 Dec 2004||Silicon Light Machines, Inc.||Diffractive light modulator with dynamically rotatable diffraction plane|
|US6829092||15 Aug 2001||7 Dec 2004||Silicon Light Machines, Inc.||Blazed grating light valve|
|US6829258||26 Jun 2002||7 Dec 2004||Silicon Light Machines, Inc.||Rapidly tunable external cavity laser|
|US6838228 *||14 May 2001||4 Jan 2005||Fairchild Semiconductor Corporation||System to enable photolithography on severe structure topologies|
|US6841464||30 Apr 2003||11 Jan 2005||Memx, Inc.||Multi-level shielded multi-conductor interconnect bus for MEMS|
|US6856449||10 Jul 2003||15 Feb 2005||Evans & Sutherland Computer Corporation||Ultra-high resolution light modulation control system and method|
|US6888979||12 Apr 2001||3 May 2005||Analog Devices, Inc.||MEMS mirrors with precision clamping mechanism|
|US6913993||20 Nov 2001||5 Jul 2005||United Microelectronics Corp.||Chemical-mechanical polishing method|
|US6923669 *||13 Feb 2004||2 Aug 2005||Zyvex Corporation||Microconnectors and non-powered microassembly therewith|
|US6930364 *||13 Sep 2001||16 Aug 2005||Silicon Light Machines Corporation||Microelectronic mechanical system and methods|
|US6937131||12 Nov 2004||30 Aug 2005||Memx, Inc.||Self-shadowing MEM structures|
|US6956219||12 Nov 2004||18 Oct 2005||Zyvex Corporation||MEMS based charged particle deflector design|
|US6958285||27 Mar 2002||25 Oct 2005||Tru-Si Technologies, Inc.||Methods of manufacturing devices having substrates with opening passing through the substrates and conductors in the openings|
|US6980412||5 Nov 2001||27 Dec 2005||Intel Corporation||Variable tunable range MEMS capacitor|
|US7002436 *||19 Aug 2004||21 Feb 2006||Intel Corporation||Vacuum-cavity MEMS resonator|
|US7005314||27 Jun 2001||28 Feb 2006||Intel Corporation||Sacrificial layer technique to make gaps in MEMS applications|
|US7021151 *||29 Oct 2004||4 Apr 2006||National Semiconductor Corporation||MEMS pressure sensing array with leaking sensor|
|US7025619||8 Mar 2005||11 Apr 2006||Zyvex Corporation||Sockets for microassembly|
|US7026698||11 May 2004||11 Apr 2006||Denso Corporation||Functional device, method of manufacturing therefor and driver circuit|
|US7029829||16 Apr 2003||18 Apr 2006||The Regents Of The University Of Michigan||Low temperature method for forming a microcavity on a substrate and article having same|
|US7045459||19 Feb 2002||16 May 2006||Northrop Grumman Corporation||Thin film encapsulation of MEMS devices|
|US7049164 *||9 Oct 2002||23 May 2006||Silicon Light Machines Corporation||Microelectronic mechanical system and methods|
|US7052622||8 Oct 2002||30 May 2006||Applied Materials, Inc.||Method for measuring etch rates during a release process|
|US7054052 *||4 Sep 2003||30 May 2006||Frank Niklaus||Adhesive sacrificial bonding of spatial light modulators|
|US7060522||7 Nov 2001||13 Jun 2006||Xerox Corporation||Membrane structures for micro-devices, micro-devices including same and methods for making same|
|US7081630||12 Mar 2004||25 Jul 2006||Zyvex Corporation||Compact microcolumn for automated assembly|
|US7096568||10 Jul 2003||29 Aug 2006||Zyvex Corporation||Method of manufacturing a microcomponent assembly|
|US7105131||5 Sep 2002||12 Sep 2006||Xerox Corporation||Systems and methods for microelectromechanical system based fluid ejection|
|US7109051 *||15 Nov 2004||19 Sep 2006||Freescale Semiconductor, Inc.||Method of integrating optical devices and electronic devices on an integrated circuit|
|US7121146||29 Oct 2004||17 Oct 2006||National Semiconductor Corporation||MEMS pressure sensing device|
|US7141812||3 Dec 2002||28 Nov 2006||Mikro Systems, Inc.||Devices, methods, and systems involving castings|
|US7170141||7 Mar 2003||30 Jan 2007||Cornell Research Foundation, Inc.||Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry|
|US7183633||1 Mar 2002||27 Feb 2007||Analog Devices Inc.||Optical cross-connect system|
|US7183637 *||13 May 2005||27 Feb 2007||Silicon Light Machines Corporation||Microelectronic mechanical system and methods|
|US7221033||30 Jun 2005||22 May 2007||Robert Bosch Gmbh||Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems|
|US7248131||14 Mar 2005||24 Jul 2007||Avago Technologies Wireless Ip (Singapore) Pte. Ltd.||Monolithic vertical integration of an acoustic resonator and electronic circuitry|
|US7288464||11 Apr 2005||30 Oct 2007||Hewlett-Packard Development Company, L.P.||MEMS packaging structure and methods|
|US7314382||18 May 2005||1 Jan 2008||Zyvex Labs, Llc||Apparatus and methods of manufacturing and assembling microscale and nanoscale components and assemblies|
|US7328609||29 Oct 2004||12 Feb 2008||National Semiconductor Corporation||Wireless pressure sensing Schrader valve|
|US7335598||19 Apr 2005||26 Feb 2008||United Microelectronics Corp.||Chemical-mechanical polishing method|
|US7352039 *||24 Mar 2005||1 Apr 2008||Intel Corporation||Methods and apparatuses for microelectronic assembly having a material with a variable viscosity around a MEMS device|
|US7358580||30 Sep 2005||15 Apr 2008||Intel Corporation||Sacrificial layer technique to make gaps in MEMS applications|
|US7373833||9 Aug 2006||20 May 2008||National Semiconductor Corporation||MEMS pressure sensing device|
|US7410606||5 Jun 2002||12 Aug 2008||Appleby Michael P||Methods for manufacturing three-dimensional devices and devices created thereby|
|US7411204 *||21 Nov 2006||12 Aug 2008||Michael Appleby||Devices, methods, and systems involving castings|
|US7443002 *||18 Dec 2003||28 Oct 2008||Commissariat A L'energie Atomique||Encapsulated microstructure and method of producing one such microstructure|
|US7449355||27 Apr 2005||11 Nov 2008||Robert Bosch Gmbh||Anti-stiction technique for electromechanical systems and electromechanical device employing same|
|US7605377||17 Oct 2006||20 Oct 2009||Zyvex Corporation||On-chip reflectron and ion optics|
|US7615788||10 Nov 2009||Cornell Research Foundation, Inc.||Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry|
|US7633360||27 Sep 2006||15 Dec 2009||Analog Devices, Inc.||MEMS resonator having an inner element and an outer element that flex|
|US7638429||29 Dec 2009||Northrop Grumman Corporation||Thin film encapsulation of MEMS devices|
|US7750420 *||6 Jul 2010||Cypress Semiconductor Corporation||Integrated circuit having one or more conductive devices formed over a SAW and/or MEMS device|
|US7757393||20 Jul 2010||Georgia Tech Research Corporation||Capacitive microaccelerometers and fabrication methods|
|US7767484||30 May 2007||3 Aug 2010||Georgia Tech Research Corporation||Method for sealing and backside releasing of microelectromechanical systems|
|US7785098||14 Dec 2007||31 Aug 2010||Mikro Systems, Inc.||Systems for large area micro mechanical systems|
|US7863069 *||27 Sep 2006||4 Jan 2011||Analog Devices, Inc.||Method of forming an integrated MEMS resonator|
|US7872792||18 Jan 2011||Qualcomm Mems Technologies, Inc.||Method and device for modulating light with multiple electrodes|
|US7889415||15 Feb 2011||Qualcomm Mems Technologies, Inc.||Device having a conductive light absorbing mask and method for fabricating same|
|US7891818||12 Dec 2007||22 Feb 2011||Evans & Sutherland Computer Corporation||System and method for aligning RGB light in a single modulator projector|
|US7906353||29 Jun 2009||15 Mar 2011||Qualcomm Mems Technologies, Inc.||Method of fabricating interferometric devices using lift-off processing techniques|
|US7916980||13 Jan 2006||29 Mar 2011||Qualcomm Mems Technologies, Inc.||Interconnect structure for MEMS device|
|US7929197||19 Apr 2011||Qualcomm Mems Technologies, Inc.||System and method for a MEMS device|
|US7935556 *||27 Aug 2007||3 May 2011||Memsmart Semiconductor Corp.||Microelectromechanical system and process of making the same|
|US7947603||24 May 2011||United Microelectronics Corp.||Chemical-mechanical polishing method|
|US8023167||25 Jun 2008||20 Sep 2011||Qualcomm Mems Technologies, Inc.||Backlight displays|
|US8035883||11 Oct 2011||Qualcomm Mems Technologies, Inc.||Device having a conductive light absorbing mask and method for fabricating same|
|US8071411 *||6 Dec 2011||The Royal Institution For The Advancement Of Learning/Mcgill University||Low temperature ceramic microelectromechanical structures|
|US8077378||12 Nov 2009||13 Dec 2011||Evans & Sutherland Computer Corporation||Calibration system and method for light modulation device|
|US8105496 *||31 Jan 2012||Qualcomm Mems Technologies, Inc.||Method of fabricating MEMS devices (such as IMod) comprising using a gas phase etchant to remove a layer|
|US8115266 *||28 Jun 2011||14 Feb 2012||Seiko Epson Corporation||MEMS device having a movable electrode|
|US8217473 *||29 Jul 2005||10 Jul 2012||Hewlett-Packard Development Company, L.P.||Micro electro-mechanical system packaging and interconnect|
|US8231924||31 Jul 2012||Cargill, Incorporated||Ingredient systems comprising trehalose, food products containing trehalose, and methods of making same|
|US8243360||30 Sep 2011||14 Aug 2012||Qualcomm Mems Technologies, Inc.||Device having a conductive light absorbing mask and method for fabricating same|
|US8330323 *||9 Nov 2011||11 Dec 2012||Cornell Research Foundation, Inc.||Thermal-mechanical signal processing|
|US8358317||22 Jan 2013||Evans & Sutherland Computer Corporation||System and method for displaying a planar image on a curved surface|
|US8372677||8 May 2012||12 Feb 2013||Qualtre, Inc.||Three-axis accelerometers and fabrication methods|
|US8389410||14 Apr 2011||5 Mar 2013||United Microelectronics Corp.||Chemical mechanical polishing method|
|US8390547||7 Jun 2011||5 Mar 2013||Qualcomm Mems Technologies, Inc.||Conductive bus structure for interferometric modulator array|
|US8395227||6 Jan 2012||12 Mar 2013||Seiko Epson Corporation||MEMS device having a movable electrode|
|US8540913||31 Oct 2007||24 Sep 2013||Mikro Systems, Inc.||Methods for manufacturing three-dimensional devices and devices created thereby|
|US8593811 *||23 Sep 2011||26 Nov 2013||Dunan Microstaq, Inc.||Method and structure for optimizing heat exchanger performance|
|US8598553||31 Aug 2011||3 Dec 2013||Mikro Systems, Inc.||Methods for manufacturing three-dimensional devices and devices created thereby|
|US8629517 *||10 Dec 2012||14 Jan 2014||Taiwan Semiconductor Manufacturing Company, Ltd.||Wafer level packaging|
|US8638491||9 Aug 2012||28 Jan 2014||Qualcomm Mems Technologies, Inc.||Device having a conductive light absorbing mask and method for fabricating same|
|US8693084||27 Apr 2012||8 Apr 2014||Qualcomm Mems Technologies, Inc.||Interferometric modulator in transmission mode|
|US8702248||11 Jun 2009||22 Apr 2014||Evans & Sutherland Computer Corporation||Projection method for reducing interpixel gaps on a viewing surface|
|US8709849||10 Dec 2012||29 Apr 2014||Taiwan Semiconductor Manufacturing Company, Ltd.||Wafer level packaging|
|US8813824||5 Dec 2012||26 Aug 2014||Mikro Systems, Inc.||Systems, devices, and/or methods for producing holes|
|US8817357||8 Apr 2011||26 Aug 2014||Qualcomm Mems Technologies, Inc.||Mechanical layer and methods of forming the same|
|US8877648 *||26 Mar 2010||4 Nov 2014||Semprius, Inc.||Methods of forming printable integrated circuit devices by selective etching to suspend the devices from a handling substrate and devices formed thereby|
|US8928967||4 Oct 2010||6 Jan 2015||Qualcomm Mems Technologies, Inc.||Method and device for modulating light|
|US8940210||9 Sep 2010||27 Jan 2015||Mikro Systems, Inc.||Methods for manufacturing three-dimensional devices and devices created thereby|
|US8963159||4 Apr 2011||24 Feb 2015||Qualcomm Mems Technologies, Inc.||Pixel via and methods of forming the same|
|US8971675||28 Mar 2011||3 Mar 2015||Qualcomm Mems Technologies, Inc.||Interconnect structure for MEMS device|
|US9040425 *||17 Jul 2014||26 May 2015||Semprius, Inc.||Methods of forming printable integrated circuit devices and devices formed thereby|
|US9086564||4 Mar 2013||21 Jul 2015||Qualcomm Mems Technologies, Inc.||Conductive bus structure for interferometric modulator array|
|US9097885||27 Jan 2014||4 Aug 2015||Qualcomm Mems Technologies, Inc.||Device having a conductive light absorbing mask and method for fabricating same|
|US9110289||13 Jan 2011||18 Aug 2015||Qualcomm Mems Technologies, Inc.||Device for modulating light with multiple electrodes|
|US9134527||4 Apr 2011||15 Sep 2015||Qualcomm Mems Technologies, Inc.||Pixel via and methods of forming the same|
|US9171966 *||19 Apr 2012||27 Oct 2015||Cavendish Kinetics, Inc.||Implantation of gaseous chemicals into cavities formed in intermediate dielectrics layers for subsequent thermal diffusion release|
|US9315663||24 Sep 2009||19 Apr 2016||Mikro Systems, Inc.||Systems, devices, and/or methods for manufacturing castings|
|US9341529 *||4 Nov 2010||17 May 2016||Rohm Co., Ltd||Pressure sensor and method for manufacturing pressure sensor|
|US9434607 *||17 Mar 2015||6 Sep 2016||Seiko Epson Corporation||MEMS device|
|US9443883 *||11 May 2015||13 Sep 2016||Semprius, Inc.||Methods of forming printable integrated circuit devices and devices formed thereby|
|US20020058584 *||4 Sep 2001||16 May 2002||Bennett Alison Margaret Anne||Polymerization of olefins|
|US20020132113 *||18 Jan 2002||19 Sep 2002||Ball Semiconductor, Inc.||Method and system for making a micromachine device with a gas permeable enclosure|
|US20030006468 *||27 Jun 2001||9 Jan 2003||Qing Ma||Sacrificial layer technique to make gaps in mems applications|
|US20030080060 *||30 Oct 2001||1 May 2003||.Gulvin Peter M||Integrated micromachined filter systems and methods|
|US20030087468 *||7 Nov 2001||8 May 2003||Xerox Corporation||Membrane structures for micro-devices, micro-devices including same and methods for making same|
|US20030124848 *||8 Oct 2002||3 Jul 2003||Applied Materials, Inc.||Method for measuring etch rates during a release process|
|US20030138986 *||9 Oct 2002||24 Jul 2003||Mike Bruner||Microelectronic mechanical system and methods|
|US20030155643 *||19 Feb 2002||21 Aug 2003||Freidhoff Carl B.||Thin film encapsulation of MEMS devices|
|US20030173112 *||15 Mar 2002||18 Sep 2003||Barnes Stephen Matthew||Interconnect bus crossover for MEMS|
|US20030183916 *||27 Mar 2002||2 Oct 2003||John Heck||Packaging microelectromechanical systems|
|US20040012057 *||12 Dec 2002||22 Jan 2004||Reid Bennett||Monolithic integration of a MOSFET with a MEMS device|
|US20040046837 *||5 Sep 2002||11 Mar 2004||Xerox Corporation||Systems and methods for microelectromechanical system based fluid ejection|
|US20040049428 *||5 Sep 2002||11 Mar 2004||Soehnlen John Pius||Wireless environmental sensing in packaging applications|
|US20040053434 *||13 Sep 2001||18 Mar 2004||Silicon Light Machines||Microelectronic mechanical system and methods|
|US20040057101 *||28 Jun 2002||25 Mar 2004||James Hunter||Reduced formation of asperities in contact micro-structures|
|US20040077164 *||7 Mar 2003||22 Apr 2004||Kevin Kornegay||Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry|
|US20040180524 *||31 Mar 2004||16 Sep 2004||Rodgers Murray Steven||Shielded multi-conductor interconnect bus for MEMS|
|US20040209393 *||11 May 2004||21 Oct 2004||Toshiyuki Okumura||Functional device, method of manufacturing therefor and driver circuit|
|US20040247237 *||18 Aug 2001||9 Dec 2004||Murali Chaparala||Use of applied force to improve mems switch performance|
|US20050007652 *||10 Jul 2003||13 Jan 2005||Evans & Sutherland Computer Corporation.||Ultra-high resolution light modulation control system and method|
|US20050036269 *||19 Aug 2004||17 Feb 2005||Intel Corporation||Vacuum-cavity MEMS resonator|
|US20050059184 *||29 Jun 2004||17 Mar 2005||Sniegowski Jeffry J.||Method for making a microstructure by surface micromachining|
|US20050087826 *||12 Nov 2004||28 Apr 2005||Rodgers Murray S.||Self-shadowing MEM structures|
|US20050088765 *||12 Nov 2004||28 Apr 2005||Rodgers Murray S.||Self-shadowing MEM structures|
|US20050101048 *||12 Nov 2004||12 May 2005||Rodgers Murray S.||Self-shadowing MEM structures|
|US20050127206 *||10 Dec 2003||16 Jun 2005||Xerox Corporation||Device and system for dispensing fluids into the atmosphere|
|US20050127207 *||9 Aug 2004||16 Jun 2005||Xerox Corporation||Micromechanical dispensing device and a dispensing system including the same|
|US20050129568 *||20 Apr 2004||16 Jun 2005||Xerox Corporation||Environmental system including a micromechanical dispensing device|
|US20050130747 *||20 Apr 2004||16 Jun 2005||Xerox Corporation||Video game system including a micromechanical dispensing device|
|US20050181636 *||8 Mar 2005||18 Aug 2005||Zyvex Corporation||Sockets for microassembly|
|US20050181658 *||13 Feb 2004||18 Aug 2005||Zyvex Corporation||Microconnectors and non-powered microassembly therewith|
|US20050186799 *||19 Apr 2005||25 Aug 2005||Kun-Lin Wu||Chemical-mechanical polishing method|
|US20050199821 *||12 Mar 2004||15 Sep 2005||Zyvex Corporation||Compact microcolumn for automated assembly|
|US20050199822 *||12 Nov 2004||15 Sep 2005||Zyvex Corporation||Mems based charged particle deflector design|
|US20050214974 *||24 Mar 2005||29 Sep 2005||Field Dean L||Integrated circuit having one or more conductive devices formed over a SAW and/or MEMS device|
|US20050221528 *||13 May 2005||6 Oct 2005||Mike Bruner||Microelectronic mechanical system and methods|
|US20050255645 *||30 Jun 2005||17 Nov 2005||Markus Lutz||Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems|
|US20050255666 *||11 May 2004||17 Nov 2005||Miradia Inc.||Method and structure for aligning mechanical based device to integrated circuits|
|US20060027891 *||30 Sep 2005||9 Feb 2006||Qing Ma||Sacrificial layer technique to make gaps in MEMS applications|
|US20060049471 *||18 Dec 2003||9 Mar 2006||Commissariat A L'energie Atomique||Encapsulated microstructure and method of producing one such microstructure|
|US20060049826 *||1 Mar 2002||9 Mar 2006||Onix Microsystems||Optical cross-connect system|
|US20060105479 *||15 Nov 2004||18 May 2006||Cave Nigel G||Method of integrating optical devices and electronic devices on an integrated circuit|
|US20060148133 *||3 Jan 2005||6 Jul 2006||Analog Devices, Inc.||Method of forming a MEMS device|
|US20060183262 *||12 Apr 2006||17 Aug 2006||Northrop Grumman Corporation||Thin film encapsulation of MEMS devices|
|US20060186220 *||17 Apr 2006||24 Aug 2006||Xerox Corporation||Device and system for dispensing fluids into the atmosphere|
|US20060202779 *||14 Mar 2005||14 Sep 2006||Fazzio R S||Monolithic vertical integration of an acoustic resonator and electronic circuitry|
|US20060214246 *||24 Mar 2005||28 Sep 2006||Garcia Jason A||Methods and apparatuses for microelectronic assembly having a material with a variable viscosity around a MEMS device|
|US20060228869 *||11 Apr 2005||12 Oct 2006||Hewlett-Packard Development Company, L.P. Intellectual Property Administration||MEMS packaging structure and methods|
|US20060234412 *||19 Apr 2005||19 Oct 2006||Hewlett-Packard Development Company, L.P. Intellectual Property Administration||MEMS release methods|
|US20060246631 *||27 Apr 2005||2 Nov 2006||Markus Lutz||Anti-stiction technique for electromechanical systems and electromechanical device employing same|
|US20060278009 *||9 Aug 2006||14 Dec 2006||Hopper Peter J||MEMS pressure sensing device|
|US20060289674 *||28 Aug 2006||28 Dec 2006||Xerox Corporation||Device and system for dispensing fluids into the atmosphere|
|US20070070821 *||27 Sep 2006||29 Mar 2007||Analog Devices, Inc.||MEMS Resonator|
|US20070072327 *||27 Sep 2006||29 Mar 2007||Analog Devices, Inc.||Method of Forming an Integrated MEMS Resonator|
|US20070128828 *||29 Jul 2005||7 Jun 2007||Chien-Hua Chen||Micro electro-mechanical system packaging and interconnect|
|US20070177247 *||26 Jan 2007||2 Aug 2007||Miles Mark W||Method and device for modulating light with multiple electrodes|
|US20070281381 *||30 May 2007||6 Dec 2007||Georgia Tech Research Corporation||Method for sealing and backside releasing of microelectromechanical systems|
|US20080054759 *||10 Aug 2007||6 Mar 2008||Farrokh Ayazi||Wafer-level encapsulation and sealing of electrostatic transducers|
|US20080061163 *||8 Jan 2007||13 Mar 2008||Xerox Corporation||Device and system for dispensing fluids into the atmosphere|
|US20080087841 *||17 Oct 2006||17 Apr 2008||Zyvex Corporation||On-chip reflectron and ion optics|
|US20080093605 *||29 Jan 2007||24 Apr 2008||Cornell Research Foundation, Inc.|
|US20080102635 *||28 Dec 2007||1 May 2008||Kun-Lin Wu||Chemical-mechanical polishing method|
|US20080130089 *||14 Feb 2008||5 Jun 2008||Idc, Llc||METHOD OF FABRICATING MEMS DEVICES (SUCH AS IMod) COMPRISING USING A GAS PHASE ETCHANT TO REMOVE A LAYER|
|US20090057817 *||27 Aug 2007||5 Mar 2009||Yeh Li-Ken||Microelectromechanical System and Process of Making the Same|
|US20090160040 *||22 Dec 2008||25 Jun 2009||The Royal Institution For The Advancement Of Learning/Mcgill University||Low temperature ceramic microelectromechanical structures|
|US20090262412 *||22 Oct 2009||Idc, Llc||Method of fabricating interferometric devices using lift-off processing techniques|
|US20100109104 *||30 Oct 2008||6 May 2010||Radi Medical Systems Ab||Pressure sensor and wire guide assembly|
|US20100245980 *||30 Sep 2010||Qualcomm Mems Technologies, Inc.||System and method for a mems device|
|US20100248484 *||30 Sep 2010||Christopher Bower||Methods of Forming Printable Integrated Circuit Devices and Devices Formed Thereby|
|US20120058741 *||9 Nov 2011||8 Mar 2012||Cornell Research Foundation, Inc.||Thermal-mechanical signal processing|
|US20120140416 *||7 Jun 2012||Dunan Microstaq, Inc.||Method and structure for optimizing heat exchanger performance|
|US20120205653 *||4 Nov 2010||16 Aug 2012||Rohm Co., Ltd.||Pressure sensor and method for manufacturing pressure sensor|
|US20140246740 *||19 Apr 2012||4 Sep 2014||CAVENDISH KINETICS, INC. a Corporation||Implantation of gaseous chemicals into cavities formed in intermediate dielectrics layers for subsequent thermal diffusion release|
|US20150079783 *||17 Jul 2014||19 Mar 2015||Semprius, Inc.||Methods of Forming Printable Integrated Circuit Devices and Devices Formed Thereby|
|US20150228730 *||26 Jan 2015||13 Aug 2015||Jung-Gil YANG||Metal-oxide semiconductor field effect transistor, method of fabricating the same, and semiconductor apparatus including the same|
|US20150266721 *||17 Mar 2015||24 Sep 2015||Seiko Epson Corporation||Mems device|
|CN102398888A *||7 Sep 2011||4 Apr 2012||台湾积体电路制造股份有限公司||Wafer level packaging|
|CN102398888B||7 Sep 2011||27 Aug 2014||台湾积体电路制造股份有限公司||晶圆级封装|
|EP1339101A2 *||21 Feb 2003||27 Aug 2003||Xerox Corporation||Systems and methods for integration of heterogeneous circuit devices|
|EP1352877A2 *||9 Apr 2003||15 Oct 2003||Dalsa Semiconductor Inc.||Wafer-level MEMS packaging|
|EP1352877A3 *||9 Apr 2003||17 Nov 2004||Dalsa Semiconductor Inc.||Wafer-level MEMS packaging|
|EP1366518A1 *||6 Mar 2002||3 Dec 2003||Analog Devices, Inc.||In-situ cap and method of fabricating same for an integrated circuit device|
|EP1366518A4 *||6 Mar 2002||11 Mar 2009||Analog Devices Inc||In-situ cap and method of fabricating same for an integrated circuit device|
|EP1683199A2 *||15 Jun 2004||26 Jul 2006||Robert Bosch Gmbh||Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems|
|EP2036132A2 *||24 May 2007||18 Mar 2009||Akustica Inc.||An integrated circuit device having barrier and method of fabricating the same|
|EP2559533A2||24 Sep 2009||20 Feb 2013||Mikro Systems Inc.||Systems, devices, and/or methods for manufacturing castings|
|EP2559534A2||24 Sep 2009||20 Feb 2013||Mikro Systems Inc.||Systems, devices, and/or methods for manufacturing castings|
|EP2559535A2||24 Sep 2009||20 Feb 2013||Mikro Systems Inc.||Systems, devices, and/or methods for manufacturing castings|
|WO2000054312A1 *||10 Mar 2000||14 Sep 2000||California Institute Of Technology||Ic-compatible parylene mems technology and its application in integrated sensors|
|WO2003002450A2 *||27 Jun 2002||9 Jan 2003||Intel Corporation||Sacrificial layer technique to make gaps in mems applications|
|WO2003002450A3 *||27 Jun 2002||4 Dec 2003||Intel Corp||Sacrificial layer technique to make gaps in mems applications|
|WO2003063223A1 *||19 Dec 2002||31 Jul 2003||Ball Semiconductor, Inc||Method for making a gas permeable enclosure for micromachine devices|
|WO2003070625A2 *||19 Feb 2003||28 Aug 2003||Northrop Grumman Corporation||Thin film encapsulation of mems devices|
|WO2003070625A3 *||19 Feb 2003||25 Mar 2004||Carl B Freidhoff||Thin film encapsulation of mems devices|
|WO2003082732A2 *||5 Feb 2003||9 Oct 2003||Intel Corporation||Packaging microelectromechanical systems|
|WO2003082732A3 *||5 Feb 2003||8 Apr 2004||Intel Corp||Packaging microelectromechanical systems|
|WO2003083932A1 *||11 Oct 2002||9 Oct 2003||Applied Materials, Inc.||A method for measuring etch rtes during a release process|
|WO2003089368A2 *||17 Apr 2003||30 Oct 2003||The Regents Of The University Of Michigan||Low temperature method for forming a microcavity on a substrate and article having same|
|WO2003089368A3 *||17 Apr 2003||13 May 2004||Univ Michigan||Low temperature method for forming a microcavity on a substrate and article having same|
|WO2003090281A2 *||15 Apr 2003||30 Oct 2003||University Of Florida||Single crystal silicon membranes for microelectromechanical applications|
|WO2003090281A3 *||15 Apr 2003||8 Jan 2004||Univ Florida||Single crystal silicon membranes for microelectromechanical applications|
|WO2004058628A2||18 Dec 2003||15 Jul 2004||Commissariat A L'energie Atomique||Encapsulated microstructure and method of producing one such microstructure|
|WO2004058628A3 *||18 Dec 2003||19 Aug 2004||Commissariat Energie Atomique||Encapsulated microstructure and method of producing one such microstructure|
|WO2006055476A2 *||14 Nov 2005||26 May 2006||Freescale Semiconductor, Inc.||Method of integrating optical devices and electronic devices on an integrated circuit|
|WO2006055476A3 *||14 Nov 2005||14 May 2009||Nigel G Cave||Method of integrating optical devices and electronic devices on an integrated circuit|
|WO2006115592A1 *||10 Mar 2006||2 Nov 2006||Robert Bosch Gmbh||Anti-stiction technique for electromechanical systems and electromechanical device employing same|
|U.S. Classification||438/48, 438/50, 438/53, 148/DIG.105|
|International Classification||G03F9/00, G03F7/09, B81B7/00, B81B7/02, G03F7/207, B81B3/00|
|Cooperative Classification||H01L2924/14, H01L2924/1305, Y10S148/105, G03F9/70, B81C1/00246, G03F7/094, B81C2203/0728, H01L24/24|
|European Classification||G03F9/70, G03F7/09M, B81C1/00C12F|
|22 Dec 1997||AS||Assignment|
Owner name: SANDIA CORPORATION, NEW MEXICO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BARRON, CAROLE C.;FLEMING, JAMES G.;MONTAGUE, STEPHEN;REEL/FRAME:008860/0227;SIGNING DATES FROM 19971104 TO 19971119
|22 Jan 2003||FPAY||Fee payment|
Year of fee payment: 4
|29 Jun 2005||AS||Assignment|
Owner name: ENERGY, U.S. DEPARTMENT OF, DISTRICT OF COLUMBIA
Free format text: CONFIRMATORY LICENSE;ASSIGNOR:SANDIA CORPORATION;REEL/FRAME:016427/0762
Effective date: 19971217
|12 Oct 2006||FPAY||Fee payment|
Year of fee payment: 8
|9 May 2011||REMI||Maintenance fee reminder mailed|
|15 Sep 2011||SULP||Surcharge for late payment|
Year of fee payment: 11
|15 Sep 2011||FPAY||Fee payment|
Year of fee payment: 12