US5776663A - Method for electroplating a conductive layer on a substrate - Google Patents

Method for electroplating a conductive layer on a substrate Download PDF

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Publication number
US5776663A
US5776663A US08/596,026 US59602696A US5776663A US 5776663 A US5776663 A US 5776663A US 59602696 A US59602696 A US 59602696A US 5776663 A US5776663 A US 5776663A
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layer
seed layer
substrate
conductive layer
polyimide
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US08/596,026
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Jae-Woo Roh
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Bellwave Co Ltd
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Daewoo Electronics Co Ltd
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Assigned to DAEWOO ELECTRONICS CO., LTD. reassignment DAEWOO ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ROH, JAE-WOO
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Assigned to BELLWAVE CO., LTD. reassignment BELLWAVE CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DAEWOO ELECTRONICS CORP.
Assigned to BELLWAVE CO., LTD. reassignment BELLWAVE CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DAEWOO ELECTRONICS CORP.
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/127—Structure or manufacture of heads, e.g. inductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

Definitions

  • the present invention relates to a method for forming a conductive layer on a substrate; and, more particularly, to an improved method for forming a conductive layer on a substrate by employing a polyimide layer.
  • FIGS. 1A to 1F there are provided schematic cross sectional views illustrating a prior art method for forming or electroplating a conductive layer on a substrate.
  • a process for forming the conductive layer 16 begins with the preparation of a substrate 10 having a top surface, as shown in FIG. 1A, whereon a seed layer 12, made of metal, is formed by using a technique such as sputtering.
  • a photoresist layer 14 is deposited on top of the seed layer 12 by using a spin coating method, and then a portion thereof is patterned after a predetermined configuration. The patterned portion is then removed by a developer, thereby exposing a top surface of the seed layer 12 under the patterned portion.
  • the conductive layer 16 is formed on the exposed top surface of the seed layer 12, as illustrated in FIG. 1B, and the remaining portion of the photoresist layer 14 is removed by applying an appropriate solution, as shown in FIG. 1C.
  • the seed layer 12 which is not covered with the conductive layer 16 is then removed by using an appropriate etchant, as depicted in FIG. 1D.
  • an insulating material e.g., silicon dioxide(SiO 2 ) or aluminum oxide(Al 2 O 3
  • the wedge-shaped topography formed by a lateral surface of the conductive layer 16 and the top surface of the substrate 10, as is shown in FIG. 1D makes it difficult to deposit the dielectric layer 18 uniformly and may result in forming a sparsely filled dielectric layer region at the wedged portion.
  • a bump of the dielectric layer 18 having a significant size is formed around the top of the conductive layer 16 as shown in FIG. 1E, which must be planarized in order to improve the optical resolution in a subsequent photolithographic process, as shown in FIG. 1F.
  • the above-described electroplating method involves the steps for forming and stripping off the photoresist layer 14, depositing the dielectric layer 18, patterning the dielectric layer 18 into a predetermined configuration and planarizing the top surface thereof. These complicated processes, therefore, tend to make it difficult to obtain the desired reliability and yield.
  • an object of the present invention to provide a novel method for forming a conductive layer on a substrate by employing a polyimide layer.
  • a method for forming a conductive layer on a substrate having a top surface comprising the steps of: (a) forming a seed layer on the top surface of the substrate; (b) patterning the seed layer after a predetermined configuration; (c) depositing a polyimide layer on the patterned seed layer and a part of the substrate which is not covered with the patterned seed layer; (d) directing a light beam onto a portion of the polyimide layer formed on top of the patterned seed layer; (e) developing the portion of the polyimide layer, thereby exposing the patterned seed layer; (f) curing the remaining portion of the polyimide layer at an appropriate condition, thereby turning it into an insulator; and (g) electroplating the conductive layer on the exposed patterned seed layer.
  • FIGS. 1A to 1F show schematic cross sectional views illustrating the manufacturing steps for forming a conductive layer on a seed layer previously disclosed.
  • FIGS. 2A to 2E represent schematic cross sectional views setting forth the manufacturing steps for forming a conductive layer on a substrate in accordance with the present invention.
  • FIGS. 2A to 2E there are shown schematic cross sectional views setting forth the steps involved in forming a conductive layer on a substrate in accordance with the present invention.
  • the forming of the conductive layer having a thickness of 3 to 5 ⁇ m begins with the preparation of the substrate 100 having the top surface, whereon a seed layer 110 having a thickness 100 ⁇ 200 ⁇ is formed by using an evaporation method or a sputtering method, as shown in FIG. 2A.
  • the seed layer 110 consists of a top and a bottom layers, each of the layers having a thickness of 50 ⁇ 100 ⁇ , the top layer being made of a conductive material, e.g., gold(Au), and the bottom layer being usually made of titanium(Ti).
  • the seed layer 110 is patterned after a predetermined configuration using a photolithography method, thereby obtaining the patterned seed layer 120, as depicted in FIG. 2B.
  • a polyimide layer 130 which is photosensitive, is spin coated on top of the patterned seed layer 120 and a part of the substrate 100 which is not covered with the patterned seed layer 120, as illustrated in FIG. 2C.
  • the thickness of the polyimide layer 130 is determined by that of the conductive layer to be formed.
  • a portion of the polyimide layer 130 formed on top of the patterned seed layer 120 is exposed to a light beam, the exposed portion being developed by an appropriate developer, e.g., KOH or NaOH, thereby exposing the patterned seed layer 120, as depicted in FIG. 2D.
  • an appropriate developer e.g., KOH or NaOH
  • the remaining portion of the polyimide layer 130 is cured at an appropriate condition, e.g., at 400 degrees for approximately 60 minutes, to solidify the remaining portion thereof, the remaining portion to serve as a dielectric layer for insulating the conductive layer to be formed.
  • the conductive layer 140 is formed on top of the patterned seed layer 120 by using an electroplating method until a top surface of the conductive layer 140 is at a same level with that of the remaining portion of the polyimide layer 130, as represented in FIG. 2E.
  • the conductive layer 140 is made of a same or compatible material with that of the top layer of the patterned seed layer 120 to enhance an adhesion therebetween.
  • the top layer of the patterned seed layer 120 is made of a magnetic material, e.g, Ni-Fe alloy or Ni-Fe-Co alloy
  • the conductive layer 140 should also preferably be made of the same material.
  • the inventive method dispenses with a number of difficult manufacturing steps, e.g., forming a photoresist layer, stripping off the photoresist and planarizing dielectric layer, thereby simplifying the overall manufacturing procedure and improving the reliability and yield. This is achieved by utilizing the polyimide layer which is photosensitive before the curing and becomes insulating after the curing.

Abstract

A method for forming a conductive layer on a substrate having a patterned seed layer thereon includes the steps of: (a) depositing a polyimide layer on the patterned seed layer and a part of the substrate which is not covered with the patterned seed layer; (b) directing a light beam onto a portion of the polyimide layer formed on top of the patterned seed layer; (c) developing the portion of the polyimide layer, thereby exposing the patterned seed layer; (d) curing the remaining portion of the polyimide layer at an appropriate condition, thereby turning it into an insulator; and (e) electroplating the conductive layer on the exposed patterned seed layer.

Description

FIELD OF THE INVENTION
The present invention relates to a method for forming a conductive layer on a substrate; and, more particularly, to an improved method for forming a conductive layer on a substrate by employing a polyimide layer.
BACKGROUND OF THE INVENTION
In FIGS. 1A to 1F, there are provided schematic cross sectional views illustrating a prior art method for forming or electroplating a conductive layer on a substrate. As is well known, a process for forming the conductive layer 16 begins with the preparation of a substrate 10 having a top surface, as shown in FIG. 1A, whereon a seed layer 12, made of metal, is formed by using a technique such as sputtering. A photoresist layer 14 is deposited on top of the seed layer 12 by using a spin coating method, and then a portion thereof is patterned after a predetermined configuration. The patterned portion is then removed by a developer, thereby exposing a top surface of the seed layer 12 under the patterned portion.
In a subsequent step, the conductive layer 16 is formed on the exposed top surface of the seed layer 12, as illustrated in FIG. 1B, and the remaining portion of the photoresist layer 14 is removed by applying an appropriate solution, as shown in FIG. 1C. The seed layer 12 which is not covered with the conductive layer 16 is then removed by using an appropriate etchant, as depicted in FIG. 1D.
In order to insulate the conductive layer 16, a dielectric layer 18, made of an insulating material, e.g., silicon dioxide(SiO2) or aluminum oxide(Al2 O3), is deposited on top of the conductive layer 16 and a part of the substrate 10 which is not covered with the patterned seed layer by employing, e.g., a sputtering method or an evaporation method, as illustrated in FIG. 1E.
However, the wedge-shaped topography formed by a lateral surface of the conductive layer 16 and the top surface of the substrate 10, as is shown in FIG. 1D, makes it difficult to deposit the dielectric layer 18 uniformly and may result in forming a sparsely filled dielectric layer region at the wedged portion. Furthermore, owing to a relatively large size and height of the conductive layer 16 rising above the top surface of the substrate 10 as shown in FIG. 1D, a bump of the dielectric layer 18 having a significant size is formed around the top of the conductive layer 16 as shown in FIG. 1E, which must be planarized in order to improve the optical resolution in a subsequent photolithographic process, as shown in FIG. 1F.
The above-described electroplating method, as illustrated in FIGS. 1A to 1F, involves the steps for forming and stripping off the photoresist layer 14, depositing the dielectric layer 18, patterning the dielectric layer 18 into a predetermined configuration and planarizing the top surface thereof. These complicated processes, therefore, tend to make it difficult to obtain the desired reliability and yield.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a novel method for forming a conductive layer on a substrate by employing a polyimide layer.
In accordance with the present invention, there is provided a method for forming a conductive layer on a substrate having a top surface, said method comprising the steps of: (a) forming a seed layer on the top surface of the substrate; (b) patterning the seed layer after a predetermined configuration; (c) depositing a polyimide layer on the patterned seed layer and a part of the substrate which is not covered with the patterned seed layer; (d) directing a light beam onto a portion of the polyimide layer formed on top of the patterned seed layer; (e) developing the portion of the polyimide layer, thereby exposing the patterned seed layer; (f) curing the remaining portion of the polyimide layer at an appropriate condition, thereby turning it into an insulator; and (g) electroplating the conductive layer on the exposed patterned seed layer.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, wherein:
FIGS. 1A to 1F show schematic cross sectional views illustrating the manufacturing steps for forming a conductive layer on a seed layer previously disclosed; and
FIGS. 2A to 2E represent schematic cross sectional views setting forth the manufacturing steps for forming a conductive layer on a substrate in accordance with the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIGS. 2A to 2E, there are shown schematic cross sectional views setting forth the steps involved in forming a conductive layer on a substrate in accordance with the present invention.
The forming of the conductive layer having a thickness of 3 to 5 μm begins with the preparation of the substrate 100 having the top surface, whereon a seed layer 110 having a thickness 100˜200 Å is formed by using an evaporation method or a sputtering method, as shown in FIG. 2A. The seed layer 110 consists of a top and a bottom layers, each of the layers having a thickness of 50˜100 Å, the top layer being made of a conductive material, e.g., gold(Au), and the bottom layer being usually made of titanium(Ti).
In a subsequent step, the seed layer 110 is patterned after a predetermined configuration using a photolithography method, thereby obtaining the patterned seed layer 120, as depicted in FIG. 2B.
In a following step, a polyimide layer 130, which is photosensitive, is spin coated on top of the patterned seed layer 120 and a part of the substrate 100 which is not covered with the patterned seed layer 120, as illustrated in FIG. 2C. The thickness of the polyimide layer 130 is determined by that of the conductive layer to be formed.
Thereafter, a portion of the polyimide layer 130 formed on top of the patterned seed layer 120 is exposed to a light beam, the exposed portion being developed by an appropriate developer, e.g., KOH or NaOH, thereby exposing the patterned seed layer 120, as depicted in FIG. 2D. Subsequently, the remaining portion of the polyimide layer 130 is cured at an appropriate condition, e.g., at 400 degrees for approximately 60 minutes, to solidify the remaining portion thereof, the remaining portion to serve as a dielectric layer for insulating the conductive layer to be formed.
Thereafter, the conductive layer 140 is formed on top of the patterned seed layer 120 by using an electroplating method until a top surface of the conductive layer 140 is at a same level with that of the remaining portion of the polyimide layer 130, as represented in FIG. 2E.
In accordance with the present invention, the conductive layer 140 is made of a same or compatible material with that of the top layer of the patterned seed layer 120 to enhance an adhesion therebetween. For example, if the top layer of the patterned seed layer 120 is made of a magnetic material, e.g, Ni-Fe alloy or Ni-Fe-Co alloy, the conductive layer 140 should also preferably be made of the same material.
In comparison with the prior art method for forming a conductive layer on a seed layer, the inventive method dispenses with a number of difficult manufacturing steps, e.g., forming a photoresist layer, stripping off the photoresist and planarizing dielectric layer, thereby simplifying the overall manufacturing procedure and improving the reliability and yield. This is achieved by utilizing the polyimide layer which is photosensitive before the curing and becomes insulating after the curing.
While the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the scope of the present invention as set forth in the following claims.

Claims (7)

What is claimed is:
1. A method for forming a conductive layer on a substrate having a top surface, said method comprising the steps of:
(a) forming a seed layer on the top surface of the substrate;
(b) patterning the seed layer in a predetermined configuration;
(c) depositing a polyimide layer on the patterned seed layer and a part of the substrate which is not covered with the patterned seed layer;
(d) directing a light beam onto a portion of the polyimide layer formed on top of the patterned seed layer;
(e) developing the portion of the polyimide layer to expose the patterned seed layer;
(f) curing the remaining portion of the polyimide layer under appropriate conditions to form an insulator; and
(g) electroplating the conductive layer on the exposed patterned seed layer.
2. The method of claim 1, wherein the conductive layer has a thickness of 3 to 5 μm.
3. The method of claim 1, wherein a top surface of the conductive layer is at a same level with that of the polyimide layer.
4. The method of claim 1, wherein the seed layer includes a top and a bottom layers.
5. The method of claim 4, wherein the top layer is made of conductive material.
6. The method of claim 4, wherein each of the top and bottom layers of the seed layer has a thickness of 50 to 100 Å.
7. The method of claim 5, wherein the conductive layer is made of a same material as that of the top layer.
US08/596,026 1995-06-30 1996-02-06 Method for electroplating a conductive layer on a substrate Expired - Lifetime US5776663A (en)

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KR95-18639 1995-06-30
KR1019950018639A KR0147976B1 (en) 1995-06-30 1995-06-30 A method for planarization patterning onto the thin film head

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US20020142583A1 (en) * 1999-08-27 2002-10-03 Dinesh Chopra Barrier and electroplating seed layer
US20030140941A1 (en) * 1986-09-09 2003-07-31 Semiconductor Energy Laboratory Co., Ltd. CVD apparatus
US6791176B2 (en) 1998-12-02 2004-09-14 Formfactor, Inc. Lithographic contact elements
JP2017199718A (en) * 2016-04-25 2017-11-02 Tdk株式会社 Electronic component and method for manufacturing the same
CN112074098A (en) * 2015-07-15 2020-12-11 Lg伊诺特有限公司 Printed circuit board

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TW589453B (en) * 1998-12-02 2004-06-01 Formfactor Inc Lithographic contact elements
US6268015B1 (en) 1998-12-02 2001-07-31 Formfactor Method of making and using lithographic contact springs
KR100530737B1 (en) * 2000-01-27 2005-11-28 한국전자통신연구원 Fabrication method of metalization by electroplating in multi-chip module substrate manufacturing process
FR2834300B1 (en) * 2002-01-03 2004-02-27 Cit Alcatel PROCESS FOR LOCAL GALVANIZATION OF A PART
KR100861293B1 (en) * 2002-12-09 2008-10-01 주식회사 하이닉스반도체 Method for fabricating photoresist pattern
KR100604819B1 (en) 2003-06-12 2006-07-28 삼성전자주식회사 Flexible substrate for LDI package, manufacturing method thereof and semiconductor package using the same
JP6261258B2 (en) * 2013-09-26 2018-01-17 Ｎｉｓｓｈａ株式会社 Transparent conductive support, touch sensor, and manufacturing method thereof
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US5209817A (en) * 1991-08-22 1993-05-11 International Business Machines Corporation Selective plating method for forming integral via and wiring layers
US5529863A (en) * 1994-08-01 1996-06-25 Motorola, Inc. Method for fabricating LCD substrates having solderable die attach pads

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030140941A1 (en) * 1986-09-09 2003-07-31 Semiconductor Energy Laboratory Co., Ltd. CVD apparatus
US20080115353A1 (en) * 1998-12-02 2008-05-22 Formfactor, Inc. Lithographic contact elements
US6791176B2 (en) 1998-12-02 2004-09-14 Formfactor, Inc. Lithographic contact elements
US20050148214A1 (en) * 1998-12-02 2005-07-07 Formfactor, Inc. Lithographic contact elements
US7287322B2 (en) 1998-12-02 2007-10-30 Formfactor, Inc. Lithographic contact elements
US7555836B2 (en) 1998-12-02 2009-07-07 Formfactor, Inc. Method of making lithographic contact elements
US20100088888A1 (en) * 1998-12-02 2010-04-15 Formfactor, Inc. Lithographic contact elements
US7041595B2 (en) 1999-08-27 2006-05-09 Micron Technology, Inc. Method of forming a barrier seed layer with graded nitrogen composition
US20020142583A1 (en) * 1999-08-27 2002-10-03 Dinesh Chopra Barrier and electroplating seed layer
CN112074098A (en) * 2015-07-15 2020-12-11 Lg伊诺特有限公司 Printed circuit board
US11723153B2 (en) 2015-07-15 2023-08-08 Lg Innotek Co., Ltd. Printed circuit board and method of fabricating the same
CN112074098B (en) * 2015-07-15 2023-12-15 Lg伊诺特有限公司 Printed circuit board with improved heat dissipation
JP2017199718A (en) * 2016-04-25 2017-11-02 Tdk株式会社 Electronic component and method for manufacturing the same

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KR0147976B1 (en) 1998-10-15
KR970002880A (en) 1997-01-28
JPH0918118A (en) 1997-01-17
CN1139709A (en) 1997-01-08

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