US5751164A - Programmable logic device with multi-level power control - Google Patents
Programmable logic device with multi-level power control Download PDFInfo
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- US5751164A US5751164A US08/668,896 US66889696A US5751164A US 5751164 A US5751164 A US 5751164A US 66889696 A US66889696 A US 66889696A US 5751164 A US5751164 A US 5751164A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17784—Structural details for adapting physical parameters for supply voltage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17792—Structural details for adapting physical parameters for operating speed
Definitions
- This invention relates generally to complex programmable logic devices and in particular to a method and structure used to control power consumption and speed performance in a complex programmable logic device.
- CMOS complementary metal-oxide-semiconductor
- CMOS technology has the characteristic that if no signals are changing, no appreciable power is consumed for true digital circuits.
- the power consumed is proportional to the number of signals switching, and the rate at which the signals switch. As more signals switch, more power is consumed. As signals switch at higher frequencies, more power is consumed. Power consumption associated with signal switching in CMOS circuitry is referred to as dynamic power consumption.
- CPLDs use digital CMOS technology for most portions of the circuitry, but there are some critical analog CMOS circuits that consume power even when no signals are switching. This component of power consumption is referred to as static power consumption.
- static power consumption This component of power consumption.
- the total power consumption of a CPLD is made up of two components: a static component from the analog circuits, and a dynamic component from the digital circuits.
- FPGAs use only digital CMOS technology
- FPGAs have only a dynamic power consumption component. While this component is comparable to the dynamic power consumption of a CPLD, the static component of the CPLD power raises the CPLD power consumption considerably when compared to an FPGA or other CMOS standard logic. Consequently, CPLDs are at a competitive disadvantage to FPGAs when power consumption is an important factor.
- heat given off by the CPLD This heat is generated in the silicon, and is transferred to the ambient environment through the package of the CPLD.
- the actual temperature of the silicon is determined by the temperature of the ambient environment and the ability of the package to draw heat away from the silicon into the ambient environment. This characteristic of the package is referred to as the thermal impedance of the package. The higher the thermal impedance of the package, the harder it is for heat generated inside the silicon to get out into the ambient environment. If heat cannot escape, the temperature of the silicon rises.
- the static component of CMOS power consumption is fixed. As the size of CPLD is increased, the power consumption raises in direct proportion to the density due to the static component. This has limited the size of CPLDs that can be built.
- FIG. 1 is a block diagram of a logic structure 100 typically found in prior art CPLDs.
- a plurality of product terms 110 drive sensing and OR gate circuity. 120.
- the sensing circuitry was used to detect whether a product term should be interpreted as a logic zero or a logic one.
- the OR gate circuitry was used to generate a sum-of-product terms.
- the output signal from sensing and OR gate circuity 120 drives a logic macrocell 130 and the output signal from logic macrocell 130 in turn drives a first feedback line 131 and an I/O cell 140.
- the output signal from I/O cell 140 drives I/O pin 150 and a second feedback line 151.
- a programmable power-down cell 260 (FIG. 2) was provided with each logic structure 100 to allow a trade-off between speed and power. Static power is predominantly dissipated in sensing circuitry and OR gate circuitry 120 between product terms 110 and macrocell 130. Thus, by configuring programmable power-down cell 260, each logic structure 100 was programmed either for higher speed or lower power consumption, but not both. See for example, "Obtaining 70 MHz performance in the MAX architecture," Electronic Engineering, FIG. 5, pg 69, 72, May 1991.
- the number of macrocells controlled by a single power-down cell is defined as the granularity of power control.
- a maximum granularity of one power-down cell per macrocell was used.
- the granularity of the power control must be reduced. For instance, one power-down cell per block could be used. The difficulty with this approach is that for the performance that most designs require, the power could not be reduced enough to be competitive with the high-granularity power control devices. If the power reduction were made larger, the speed in the power-down mode would not be adequate for many applications.
- One approach for the two level power control would be to power-down all but the highest speed signals. If few signals require a high-power mode for acceptable speed, more signals can be powered down, potentially lowering the overall power consumption of the chip. This approach requires that the speed of signals in the power-down mode has to be high enough to satisfy the requirements of all but the fastest signals. Unfortunately, this requirement limits the power reduction so that enough speed performance remains. Consequently, such an approach provides only a limited power reduction benefit.
- the low-power mode speed performance suffers. In this case, more signals require high-power mode. So while the powered-down signals consume less power, there are fewer candidates for power-down. Since more signals require full power, the power reduction for the entire circuit is not appreciable.
- a complex programmable logic device has block-level power-down control with multiple power-down levels.
- This power-down control architecture eliminates the prior art die size penalties of fine-granularity power-down control, and the trade-off inefficiencies associated with block-level power-down control.
- the multiple power-down levels permit configurations that eliminate the necessity of trading speed performance for power savings.
- circuits having a common speed performance are placed in a block and a power-level commensurate with that speed performance is selected for that block.
- the multiple levels available make this possible in comparison to the prior-art two-level approach.
- each programmable logic structure includes a plurality of logic elements, and a power and speed performance control line coupled to each of the plurality of logic elements.
- a speed performance and a power consumption of the programmable logic structure are determined by a signal on the power and speed performance control line.
- a programmable power and speed control circuit is coupled to the power and speed performance control line.
- the programmable power and speed control circuit is programmably configurable to provide a signal selected from one of at least three power and speed performance point signals on the power and speed performance control line.
- a plurality of programmable power/speed reference architectural cells are connected to the programmable power and speed control circuit. Upon programming the plurality of programmable power/speed reference architectural cells, the programmable power and speed control generates the signal on the power and speed performance control line.
- FIG. 1 is a block diagram of a prior art cell structure used in a programmable logic device.
- FIG. 2 is an illustration of the prior art cell structure with a cell level power-down granularity.
- FIG. 3 is an illustration of a programmable logic block built using the prior art cell-level power-down structure with a supplemental block-level power-down.
- FIG. 4 is an illustration of a segment of a complex programmable logic device with a multi-power level block power-down granularity of this invention.
- FIG. 5 is a more detailed illustration of one programmable logic block of the CPLD of FIG. 4 that is illustrates the novel power-down structure of this invention.
- FIG. 6 is a more detailed illustration of one programmable logic block of the CPLD of FIG. 5 that illustrates another embodiment of the novel power-down structure of this invention.
- FIG. 7A is a diagram of one embodiment of a block-level reference voltage generator circuit of this invention.
- FIG. 7B is a diagram of another embodiment of a block-level reference voltage generator circuit of this invention.
- the prior art die size penalties of fine-granularity power-down control, and the trade-off inefficiencies associated with block-level power-down control are eliminated by providing multiple power-down levels at a low-granularity level.
- the multiple power-down levels permit configurations that eliminate the necessity of trading speed performance for power savings.
- circuits having a common speed performance are placed in a block and a power-level commensurate with that speed performance is selected for that block.
- each programmable logic block is coupled to a programmable power and speed control circuit 450-A to 450-D, respectively, by a power and speed control line 451-A to 451-D, respectively.
- the particular interconnect architecture, i.e, a segmented structure, and block structure of CPLD 400 are not essential features of this invention.
- a block structure is not intended to limit the invention to a particular architecture.
- the power control principles of this invention can be used with any-lower granularity grouping of signals, e.g., a grouping of logic elements that share a common programmable power and speed control circuit.
- a block is any lower granularity group of signals where the signal speed is controlled by a signal on a power and speed control line from the common programmable power and speed control circuit.
- Each programmable power and speed control circuit 450-i is programmably configurable to generate on power and speed control line 451-i a signal that selects one of at least three power and speed performance points for programmable logic block 401-i, e.g., a plurality of power and speed performance points.
- the signal is a reference voltage level that determines the power consumption of programmable logic block 401-i, and the speed performance of programmable logic block 401-i.
- the power control granularity is at the programmable logic block level, but multiple power consumptions levels for each programmable logic block are available. This overcomes the limitations of the prior art methods by allowing selection of a specific power/speed performance point, as explained more completely below, that is optimal for programmable logic block 401-i.
- FIG. 4 is an illustration of one segment 101 that in addition to programmable logic blocks 401-A to 401-D includes a plurality of block switch matrices 466A to 466D, where each block switch matrix couples a programmable logic block to a segment switch matrix 461. Segment switch matrix couples global switch matrix 465 to the plurality of block switch matrices 466A to 466D.
- CPLD 400 is provided in U.S. Pat. No. 5,521,529 entitled "VERY HIGH-DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES WITH A MULTI-TIERED HIERARCHICAL SWITCH MATRIX AND OPTIMIZED FLEXIBLE LOGIC ALLOCATION" of Om P. Agrawal et al. issued on May 28, 1996, which is incorporated herein by reference in its entirety.
- programmable power and speed control circuit 450-i is programmably configurable to generate an output signal on power and speed control line 451-i so that the static power consumption of the corresponding programmable logic block 401-i is adjusted to provide a particular combination of power and speed for that programmable logic block, i.e., a specific power/speed performance point.
- a plurality of programmable selectable speed/power levels are provided by programmable power and speed control circuit 450-i.
- the CPLD of this invention has enhanced speed performance and reduced power consumption because the power consumption is selected to provide the desired speed performance for a particular block.
- each programmable logic block 401-i in CPLD 400 has the same configuration, the principles of this invention are demonstrated for one embodiment using programmable logic block 501 (FIG. 5) that includes a plurality of product terms 510-1 to 510-n and each product term 510-1 to 510-n drives one of sensing and OR circuitry 520-1 to 520-n, i.e, drives a group of logic elements, respectively.
- a sum of product terms from sensing and OR circuitry 520-i drives a logic macrocell 530-i that in turn drives a feedback line 531-i and an I/O output cell 540-i.
- I/O output cell 540-i is connected to another feedback line 541-i and an I/O pin 555-i.
- the particular configuration of the programmable AND array, sensing and OR circuitry 520-i, macrocell 530-i, and I/O cell 540-i are not essential to this invention, because the principles of this invention apply to any programmable logic device with a programmable block structure that includes a plurality of logic elements coupled to a common power and speed control line.
- power and speed control circuit 450-i is a programmable reference voltage generator circuit 550.
- programmable reference voltage generator circuit 550 a reference voltage controlling the drive capability of internal transistors in programmable logic block 501 is programmably adjusted to select one of at least three different power/speed points.
- Programmable reference voltage generator 550 is connected to a reference voltage line 551 that in turn is connected to each of sensing and OR circuitry 520-1 to 520-n.
- Programmable reference voltage generator 550 is programmably configured using programmable power/speed reference architectural cells S0 and S1 to provide a voltage level VREF on reference voltage line 551, where voltage level VREF is one of at least three reference voltage levels.
- voltage level VREF is one of at least three reference voltage levels.
- programmable logic block 501 has a different speed performance and power consumption.
- speed performance is measured in terms of signal delay time. As the power consumption decreases, the signal delay time increases and conversely.
- Table 1 is one example of the different power/speed points for the possible configurations of programmable power/speed reference architectural cells S0 and 51.
- columns S0 and S1 represent the state of architectural cells S0 and S1 respectively.
- Column Vref is the reference voltage level Vref generated by reference voltage generator circuit 550 for the particular combination of states of architectural cells S0 and S1 given and the typical levels of reference voltage level Vref in volts.
- Columns speed and power give the relative speed/power point for the programmable logic block for the reference voltage Vref.
- reference voltage Vref has a high value of 1.2 volts.
- the levels of the speed and power for this reference voltage are taken as high and so are represented by a one, i.e, a maximum, in the speed and power columns.
- a medium high reference voltage level is 1.09 volts and a medium fast speed is a time delay that is 1.3 times the delay for the fast speed.
- a medium high power level is 0.6 of the high power level.
- VT transistor threshold voltage
- Table 1 illustrates one embodiment of the encoding of architectural cells S0 and S1 and the corresponding function of reference voltage generator circuit 550.
- a zero in columns S0 and S1 corresponds to a logic zero and is equivalent to a programmed state
- a one corresponds to a logic one and is equivalent to an unprogrammed or erased state.
- alternative definitions of the programmed and unprogrammed states may be used with the principles of this invention to define alternative embodiments.
- the cells in these applications may be fuses, EPROM cells, EEPROM cells, RAM cells, or antifuse technology in accordance with the invention.
- the architectural cells are a means for providing signals to a programmable reference voltage generator so that the generator drives a desired voltage level on the output line of the generator.
- the novel multi-level block-level granularity provides a range of power and speed performances trade-offs.
- High-speed signals can be placed and routed to one programmable logic block 401-i and reference voltage generator 550-i configured for high speed high power performance.
- Other signals that have an intermediate speed performance requirement can be placed and routed to another programmable logic block 401-j and reference voltage generator 550-j configured for medium fast speed performance and medium high power consumption.
- the slowest speed performance signals can be placed and routed to yet another programmable logic block 401-k and reference voltage generator 550-k configured for slow performance and ultra-low power consumption.
- programmable logic block 601 (FIG. 6) is the same as that described above for programmable logic block 501 and that description is incorporated herein by reference.
- power and speed control circuit 450-i includes a programmable sense/OR reference voltage generator 651 that is connected by a sense reference voltage line 653 to sensing and OR circuitry 520-1 to 520-n, and a programmable slew rate reference voltage generator 652 that is connected by slew rate reference voltage line 654 to each of I/O cells 540-1 to 540-n.
- Programmable sense/OR reference voltage generator 651 is programmably configured using programmable power/speed reference architectural cells S0 and S1 to provide a voltage level VREFSENSE on reference voltage line 653, where voltage level VREFSENSE is one of at least three reference voltage levels. For each reference voltage level VREFSENSE, programmable logic block 501 has a different speed performance and power consumption.
- Programmable slew rate reference voltage generator 652 is programmably configured using programmable power/speed reference architectural cells S0 and S1 to provide a voltage level VREFSLEW on reference voltage line 654, where voltage level VREFSLEW is one of at least two reference voltage levels.
- programmable power/speed reference architectural cells S0 and S1 are used to programmably configure both programmable sense/OR reference voltage generator 651 and programmable slew rate reference voltage generator 652. Since the number of programmable power/speed reference architectural cells S0 and S1 is unchanged, this embodiment has three power levels: a fast slew rate associated with the highest-speed mode; a slow slew rate associated with the lowest-power mode; and a selectable slew rate, e.g., fast or slow, for the medium speed/power mode
- Table 2 is one example of the different power/speed points and slew rates for one embodiment of the possible configurations of programmable power/speed reference architectural cells S0 and S1.
- Providing multiple power levels at a block level granularity allows some signals in the CPLD to have extremely fast speeds, and some signals to be powered down far below what would be possible in the prior art two-level power-down methods including methods with fine granularity control.
- User implementations requiring low speed therefore operate at power consumption levels far below anything possible in prior-art CPLDs.
- a prior-art CPLD with fine granularity control achieves 130 mA of current when all cells are in low power mode; an equivalent device using this invention is expected to draw less than 50 mA of current, cutting the power consumption by over 60%. This invention therefore allows both the offering of power consumption levels more attractive to users for all performance levels, and the development of larger CPLDs than might be possible without the invention.
- FIG. 7A is a diagram of one embodiment of a programmable reference voltage generator circuit 700.
- Programmable reference voltage generator circuit 700 includes a single current source 701, such as a bandgap reference, and a plurality of current mirrors 702 to 705.
- Each of current mirrors 702 to 705 is programmably connected to and disconnected from generator circuit 700 to adjust the level of reference voltage Vref on power and speed control output line 711.
- the state of programmable power/speed reference architectural cell S0 controls the states of switches 710 and 711
- the state of programmable power/speed reference architectural cell S1 controls the states of switches 712 and 713.
- the use of switch elements 710 to 713 in FIG. 7A is illustrative only of a function performed in generator circuit 700. Those of skill in the art will appreciate that the switch function can be implemented in a wide variety of ways.
- the programmable reference voltage generator circuit includes a plurality of current sources.
- the set of current sources are individually programmably connected to and disconnected from the reference voltage output line so as to vary the reference voltage level.
- circuit 750 has a first current source 751 that is fixedly connected to output line 752 and provides a minimum reference voltage level.
- a second current source 753 is programmably connectable to and disconnectable from output line 752 by programmable power/speed reference architectural cell S1.
- programmable sense/OR reference voltage generator 651 is constructed using a current mirror circuit similar is to that illustrated in FIG. 7A, and programmable slew rate reference voltage generator 652 is constructed using a plurality of current sources as illustrated in FIG. 7B.
Abstract
Description
TABLE 1 ______________________________________ Power/Speed Points for ReferenceVoltage Generator Circuit 550 Vref S0 S1 (Volts) Speed Power ______________________________________ 0 0 High 1.2Fast 1High 1 0 1 Med Hi 1.09 Med Fast 1.3 Med Hi 0.6 1 0 Med Lo 1.02 Med Slow 1.6 Low 0.4 1 1 Low 0.92 Slow 2 Ultra-low 0.2 ______________________________________
TABLE 2 ______________________________________ Power/Speed Points with Slew Rate for Programmable Sense/ORReference Voltage Generator 651 and Programmable Slew RateReference Voltage Generator 652 VREFSENSE S0 S1 (Volts) Speed Power Slew Rate ______________________________________ 0 0 High 1.2Fast 1High 1Fast 1 0 1 Med 1.05 Med 1.5 Med 0.5Fast 1 1 0 Med 1.05 Med 1.5 Med 0.5 Slow 0.3 1 1 Low 0.92 Slow 2 Low 0.2 Slow 0.3 ______________________________________
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