US5654660A - Level shifted high impedance input multiplexor - Google Patents
Level shifted high impedance input multiplexor Download PDFInfo
- Publication number
- US5654660A US5654660A US08/534,420 US53442095A US5654660A US 5654660 A US5654660 A US 5654660A US 53442095 A US53442095 A US 53442095A US 5654660 A US5654660 A US 5654660A
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- Prior art keywords
- input
- multiplexor
- buffer
- output
- channel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Definitions
- the present invention relates to integrated circuit design and in particular to the design of high density high impedance multiplexors.
- CMOS inverter When an CMOS inverter is driven from this less than full voltage swing signal, the P-channel device in the inverter is never turned completely off. This results in an undesirable DC current from the output of the inverter.
- One well known way of dealing with this unwanted current is to add a weak feedback inverter to raise the input level to the main inverter to Vdd and thereby allow the P-channel device in the inverter to shut off completely.
- FIG. 1 illustrates a prior art multiplexor which uses a feedback inverter to restore the input level to the main inverter.
- four N-channel switches 101, 103, 105 and 107 are connected to form a 4 to 1 multiplexor as is known in the art.
- Input signals IN1-IN4 are the signal inputs to the N-channel switches 101-107 respectively.
- Select signals S1-S4 control the gates of the N-channel switches 101-107, respectively, and serve to select which, if any, of the N-channel switches are turned to thereby allow the associated input signal to pass through the multiplexor.
- This inverter is designed as a standard CMOS inverter with a P-channel pull up transistor and a N-channel pull down transistor.
- the output of the main inverter becomes the circuit output 111.
- a weak feedback inverter 113 which has an input connected to the output of the main inverter.
- the output of the weak inverter is connected to the input of the main inverter (Node A).
- Inside the weak inverter is a two transistor CMOS inverter with the pull up and pull down transistors sized such that the output of the weak inverter can be overpowered by any of the N-channel switches 101-107 so the input to the main inverter can change.
- the P-channel pull up transistor in the weak inverter serves to pull up Node A to Vdd when a logic "1" is output on Node A by one of the N-channel switches.
- the weak inverter changes the input impedance of the N-channel switches 101-107. While a typical CMOS transistor has an input of approximately 10 14 ohms, since the output of the weak inverter is connected to Node A, the input impedance as seen by a device connected to any of the inputs IN1-IN4 is approximately (30*10 3 ) ohms. In FPGAs where the fanout may be very large and the series resistance of long interchip interconnect lines may be high, this low input impedance becomes a problem. In particular a transistor driving one of the N-channel switch inputs may not be able to supply the current required to drive the input at high speed, if at all.
- the present invention is a high input impedance multiplexor.
- a buffer stage is connected to a common output from a plurality of N-channel multiplexor switches.
- a pull up P-channel transistor in this buffer is connected to a voltage source which equals (Vdd--VtN-channel switch) such that the buffer output can be fully shut off when a logic "1" is output by one of the N-channel multiplexor switches.
- the output of the buffer is fed through an isolation N-channel transistor to a main inverter and weak feedback inverter.
- the input impedance as seen from a device driving a signal input to one of the N-channel multiplexor switches is approximately the input impedance of the buffer (high impedance).
- This novel circuit allows for the use of N-channel switching transistors while maintaining a high input impedance and eliminating unwanted output current.
- FIG. 1 illustrates a prior art CMOS 4 to 1 multiplexor.
- FIG. 2 illustrates a 4 to 1 CMOS multiplexor according to the present invention.
- FIG. 2 illustrates the preferred embodiment of the present invention.
- the common output "Node A" of the N-channel switches feeds the input of a buffer 201.
- Also connected to Node A are four series connected pull up P-channel transistors 203,205,207 and 209.
- the buffer 201 is constructed as a standard two transistor CMOS inverter with a P-channel pull up transistor and a N-channel pull down transistor. Instead of connecting the P-channel pull up transistor (inside 201) to Vdd as is normally done, the source of the P-channel transistor is connected to the drain 211 of a voltage drop N-channel transistor 213. The source and gate of transistor 213 are connected to Vdd.
- An isolation N-channel transistor 215 is connected in series between the buffer 201 output 217 and the junction 219 of the main inverter 109 input and weak inverter 113 output. The output of the main inverter 109 becomes the circuit output 221.
- the multiplexor switch transistors 101-107 operate as previously discussed in association with FIG. 1.
- the four pull up transistors 203-209 serve to keep Node A from “floating" when none of the mutiplexor switch transistors are selected (S1-S4 are at logic "0").
- the maximum voltage present on Node A when a multiplexor switch is selected is (Vdd-Vt N-channel) as already discussed. Since the source voltage 211 for the CMOS buffer is (Vdd-Vt of N-channel transistor 213) the signal on Node A is rail to rail with respect to the buffer. As such, the P-channel pull up transistor in buffer 201 is completely shut off when a logic "1" is output onto Node A by one of the multiplexor switch transistors.
- the output 217 of the buffer 201 is isolated from the higher voltage output of the weak inverter 113 by the series N-channel transistor 215.
- This transistor 215 keeps the drain of the P-channel pull up transistor inside buffer 201 from being at a higher voltage than the source voltage from the voltage drop transistor 213. This problem would occur without transistor 215 as the output of the weak inverter switches from rail to rail (Vdd to approximately 0.0 volts).
- the main inverter provides the circuit output 221 and the weak inverter performs a level restore function for the main inverter as discussed in association with FIG. 1.
- the input impedance as seen by a device driving one of the N-channel inputs IN1-IN4 is the input impedance of the buffer 201 which is approximately 10 14 ohms. Therefore this novel circuit allows the use of N-channel multiplexor switch transistors which is highly desirable in FPGAs while maintaining the high input impedance required for high fan out designs.
Abstract
A high input impedance CMOS multiplexor. A buffer stage is connected to common outputs of a plurality of N-channel multiplexor switches. A pull up P-channel transistor in this buffer is connected to a voltage source which is equal to the maximum voltage output from one of the plurality of N-channel multiplexor switches. As such, the buffer output can be fully shut off when a logic "1" is output by one of the multiplexor switches. The input impedance of the multiplexor is approximately the input impedance of the buffer or approximately 1014 ohms.
Description
The present invention relates to integrated circuit design and in particular to the design of high density high impedance multiplexors.
In switch intensive chips such as field programmable gate arrays (FPGAs) chip area requirements dictate the use of N-channel only switches instead of complementary (P-channel and N-Channel) switches. The use of N-channel only switches results in less than rail to rail signal swings since the voltage out of a N-channel switch is (Vgate-Vthreshold).
When an CMOS inverter is driven from this less than full voltage swing signal, the P-channel device in the inverter is never turned completely off. This results in an undesirable DC current from the output of the inverter. One well known way of dealing with this unwanted current is to add a weak feedback inverter to raise the input level to the main inverter to Vdd and thereby allow the P-channel device in the inverter to shut off completely.
FIG. 1 illustrates a prior art multiplexor which uses a feedback inverter to restore the input level to the main inverter. As shown, four N- channel switches 101, 103, 105 and 107 are connected to form a 4 to 1 multiplexor as is known in the art. Input signals IN1-IN4 are the signal inputs to the N-channel switches 101-107 respectively. Select signals S1-S4 control the gates of the N-channel switches 101-107, respectively, and serve to select which, if any, of the N-channel switches are turned to thereby allow the associated input signal to pass through the multiplexor.
The output of the multiplexor, Node A, feeds a main inverter 109. This inverter is designed as a standard CMOS inverter with a P-channel pull up transistor and a N-channel pull down transistor. The output of the main inverter becomes the circuit output 111.
A weak feedback inverter 113 is provided which has an input connected to the output of the main inverter. The output of the weak inverter is connected to the input of the main inverter (Node A). Inside the weak inverter is a two transistor CMOS inverter with the pull up and pull down transistors sized such that the output of the weak inverter can be overpowered by any of the N-channel switches 101-107 so the input to the main inverter can change. The P-channel pull up transistor in the weak inverter serves to pull up Node A to Vdd when a logic "1" is output on Node A by one of the N-channel switches.
While this circuit works generally, the downside of this design is the weak inverter changes the input impedance of the N-channel switches 101-107. While a typical CMOS transistor has an input of approximately 1014 ohms, since the output of the weak inverter is connected to Node A, the input impedance as seen by a device connected to any of the inputs IN1-IN4 is approximately (30*103) ohms. In FPGAs where the fanout may be very large and the series resistance of long interchip interconnect lines may be high, this low input impedance becomes a problem. In particular a transistor driving one of the N-channel switch inputs may not be able to supply the current required to drive the input at high speed, if at all.
Therefore what is needed in the industry is a multiplexor which allows for the use of N-channel switches but retains a high impedance on the inputs to the switches.
The present invention is a high input impedance multiplexor. A buffer stage is connected to a common output from a plurality of N-channel multiplexor switches. A pull up P-channel transistor in this buffer is connected to a voltage source which equals (Vdd--VtN-channel switch) such that the buffer output can be fully shut off when a logic "1" is output by one of the N-channel multiplexor switches. The output of the buffer is fed through an isolation N-channel transistor to a main inverter and weak feedback inverter. As the buffer is between the output of the weak inverter and the outputs from the N-channel multiplexor switches, the input impedance as seen from a device driving a signal input to one of the N-channel multiplexor switches is approximately the input impedance of the buffer (high impedance).
This novel circuit allows for the use of N-channel switching transistors while maintaining a high input impedance and eliminating unwanted output current.
FIG. 1 illustrates a prior art CMOS 4 to 1 multiplexor.
FIG. 2 illustrates a 4 to 1 CMOS multiplexor according to the present invention.
FIG. 2 illustrates the preferred embodiment of the present invention. As shown, the common output "Node A" of the N-channel switches feeds the input of a buffer 201. Also connected to Node A are four series connected pull up P-channel transistors 203,205,207 and 209.
The buffer 201 is constructed as a standard two transistor CMOS inverter with a P-channel pull up transistor and a N-channel pull down transistor. Instead of connecting the P-channel pull up transistor (inside 201) to Vdd as is normally done, the source of the P-channel transistor is connected to the drain 211 of a voltage drop N-channel transistor 213. The source and gate of transistor 213 are connected to Vdd.
An isolation N-channel transistor 215 is connected in series between the buffer 201 output 217 and the junction 219 of the main inverter 109 input and weak inverter 113 output. The output of the main inverter 109 becomes the circuit output 221.
In operation, the multiplexor switch transistors 101-107 operate as previously discussed in association with FIG. 1. The four pull up transistors 203-209 serve to keep Node A from "floating" when none of the mutiplexor switch transistors are selected (S1-S4 are at logic "0"). The maximum voltage present on Node A when a multiplexor switch is selected is (Vdd-Vt N-channel) as already discussed. Since the source voltage 211 for the CMOS buffer is (Vdd-Vt of N-channel transistor 213) the signal on Node A is rail to rail with respect to the buffer. As such, the P-channel pull up transistor in buffer 201 is completely shut off when a logic "1" is output onto Node A by one of the multiplexor switch transistors.
The output 217 of the buffer 201 is isolated from the higher voltage output of the weak inverter 113 by the series N-channel transistor 215. This transistor 215 keeps the drain of the P-channel pull up transistor inside buffer 201 from being at a higher voltage than the source voltage from the voltage drop transistor 213. This problem would occur without transistor 215 as the output of the weak inverter switches from rail to rail (Vdd to approximately 0.0 volts).
The main inverter provides the circuit output 221 and the weak inverter performs a level restore function for the main inverter as discussed in association with FIG. 1.
Through the addition of the buffer 201, the input impedance as seen by a device driving one of the N-channel inputs IN1-IN4 is the input impedance of the buffer 201 which is approximately 1014 ohms. Therefore this novel circuit allows the use of N-channel multiplexor switch transistors which is highly desirable in FPGAs while maintaining the high input impedance required for high fan out designs.
The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. For example, the pull up transistors 203-209 can be replaced with a high resistance resister. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various other embodiments and various modifications as are suited to the particular use contemplated. It is intended therefore that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.
Claims (6)
1. A high input impedance CMOS multiplexor having a plurality of N-channel multiplexor input switching transistors connected to a common output node comprising:
a main inverter having an input and an output;
a weak inverter having an input connected to the output of the main inverter and the weak inverter having an output connected to the input of the main inverter;
a buffer having an input connected to the common output node and the buffer having an output connected to the input of the main inverter; and
the high input impedance of the CMOS multiplexor is approximately the high input impedance of the buffer when any signals are received by the plurality of N-channel multiplexor input switching transistors.
2. A high input impedance CMOS multiplexor as in claim 1 further comprising a turned-on isolation transistor wherein the output of the buffer is connected to the input of the main inverter through the isolation transistor in-order to isolate the buffer output from the output of the weak inverter.
3. A high input impedance CMOS multiplexor as in claim 2 further comprising:
a power supply providing a voltage Vdd coupled to power the turned-on isolation transistor;
a voltage source coupled to power the buffer and having voltage lower than the voltage Vdd powering the turned-on isolation transistor.
4. A high input impedance CMOS multiplexor as in claim 3 further comprising:
an N-channel transistor having a drain and a gate electrode coupled to the voltage Vdd and a source electrode forming the voltage source, wherein
the voltage source coupled to power the buffer is less than Vdd by approximately one threshold voltage drop of the N-channel transistor.
5. A high input impedance CMOS multiplexor having a plurality of N-channel multiplexor input switching transistors each having a signal input node and a select input for selectively coupling the signal input node to a common output node, the multiplexor comprising:
a main inverter having an input and an output;
a weak inverter having an input connected to the output of the main inverter and the weak inverter having an output connected to the input of the main inverter;
an isolation transistor having an output connected to the input of the main inverter and the isolation transistor having a gate input connected to a first voltage source (Vdd) and the isolation transistor having an input;
a buffer having an input connected to the common output node and the buffer having an output connected to the input of the isolation transistor,
a second voltage source coupled to power the buffer, the second voltage source having a voltage less than Vdd by an amount approximately equal to a threshold voltage of the N-channel multiplexor input switching transistors so that the maximum voltage at the common output node substantially equals the voltage of the second voltage source in-order to shut off the buffer; and
a pull up device coupled between the first voltage source and the common output node and controlled by each of the select inputs of the input switching transistors which operates to keep the common output node from floating in the event none of the plurality of N-channel multiplexor input switching transistors connected to the common output node are conducting current.
6. A high input impedance CMOS multiplexor as in claim 5 wherein:
the pull up device includes a plurality of series connected transistors which are controlled by the select inputs.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/534,420 US5654660A (en) | 1995-09-27 | 1995-09-27 | Level shifted high impedance input multiplexor |
| JP8252628A JPH09116405A (en) | 1995-09-27 | 1996-09-25 | Multiplexer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/534,420 US5654660A (en) | 1995-09-27 | 1995-09-27 | Level shifted high impedance input multiplexor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US5654660A true US5654660A (en) | 1997-08-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US08/534,420 Expired - Fee Related US5654660A (en) | 1995-09-27 | 1995-09-27 | Level shifted high impedance input multiplexor |
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| Country | Link |
|---|---|
| US (1) | US5654660A (en) |
| JP (1) | JPH09116405A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789966A (en) * | 1996-09-18 | 1998-08-04 | International Business Machines Corporation | Distributed multiplexer |
| EP0926828A1 (en) * | 1997-12-25 | 1999-06-30 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit |
| US5982220A (en) * | 1996-12-27 | 1999-11-09 | Hyundai Electronics Industries Co., Ltd. | High speed multiplexer circuit |
| US6087855A (en) * | 1998-06-15 | 2000-07-11 | International Business Machines Corporation | High performance dynamic multiplexers without clocked NFET |
| WO2001040947A1 (en) * | 1999-12-06 | 2001-06-07 | Infineon Technologies North America Corp. | Fuse latch having multiplexers with reduced sizes and lower power consumption |
| WO2001045260A1 (en) * | 1999-12-14 | 2001-06-21 | Koninklijke Philips Electronics N.V. | Electronic component with reduced inductive coupling |
| US20030076821A1 (en) * | 2001-10-19 | 2003-04-24 | Fujitsu Limited | Multiplexer circuit for converting parallel data into serial data at high speed and synchronized with a clock signal |
| US20050083107A1 (en) * | 2003-07-28 | 2005-04-21 | Elixent Limited | Methods and systems for reducing leakage current in semiconductor circuits |
| WO2011035519A1 (en) * | 2009-09-23 | 2011-03-31 | 惠州市正源微电子有限公司 | Radio frequency power synthesis circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4883578B2 (en) * | 2007-05-11 | 2012-02-22 | 独立行政法人産業技術総合研究所 | Multiplexer circuit |
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| US4820939A (en) * | 1987-11-24 | 1989-04-11 | National Semiconductor Corporation | Finite metastable time synchronizer |
| US5046047A (en) * | 1989-02-10 | 1991-09-03 | Plessey Overseas Limited | Circuit arrangement for verifying data stored in a random access memory |
| US5099143A (en) * | 1988-10-15 | 1992-03-24 | Sony Corporation | Dual voltage supply circuit with multiplier-controlled transistor |
| US5164612A (en) * | 1992-04-16 | 1992-11-17 | Kaplinsky Cecil H | Programmable CMOS flip-flop emptying multiplexers |
| US5173870A (en) * | 1989-03-09 | 1992-12-22 | Mitsubishi Denki Kabushiki Kaisha | Transmission and latch circuit for logic signal |
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| EP0637132A2 (en) * | 1993-07-30 | 1995-02-01 | Nec Corporation | Simple temporary information storage circuit controllable with enable/reset signal |
| US5467038A (en) * | 1994-02-15 | 1995-11-14 | Hewlett-Packard Company | Quick resolving latch |
| US5504919A (en) * | 1993-02-19 | 1996-04-02 | National Science Council | Sorter structure based on shiftable content memory |
-
1995
- 1995-09-27 US US08/534,420 patent/US5654660A/en not_active Expired - Fee Related
-
1996
- 1996-09-25 JP JP8252628A patent/JPH09116405A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US4806786A (en) * | 1987-11-02 | 1989-02-21 | Motorola, Inc. | Edge set/reset latch circuit having low device count |
| US4820939A (en) * | 1987-11-24 | 1989-04-11 | National Semiconductor Corporation | Finite metastable time synchronizer |
| US5099143A (en) * | 1988-10-15 | 1992-03-24 | Sony Corporation | Dual voltage supply circuit with multiplier-controlled transistor |
| US5046047A (en) * | 1989-02-10 | 1991-09-03 | Plessey Overseas Limited | Circuit arrangement for verifying data stored in a random access memory |
| US5173870A (en) * | 1989-03-09 | 1992-12-22 | Mitsubishi Denki Kabushiki Kaisha | Transmission and latch circuit for logic signal |
| US5173626A (en) * | 1990-06-25 | 1992-12-22 | Kabushiki Kaisha Toshiba | Flip-flop with scan path |
| US5264738A (en) * | 1991-05-31 | 1993-11-23 | U.S. Philips Corp. | Flip-flop circuit having transfer gate delay |
| US5164612A (en) * | 1992-04-16 | 1992-11-17 | Kaplinsky Cecil H | Programmable CMOS flip-flop emptying multiplexers |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789966A (en) * | 1996-09-18 | 1998-08-04 | International Business Machines Corporation | Distributed multiplexer |
| US5982220A (en) * | 1996-12-27 | 1999-11-09 | Hyundai Electronics Industries Co., Ltd. | High speed multiplexer circuit |
| US6271685B1 (en) | 1997-12-25 | 2001-08-07 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit |
| EP0926828A1 (en) * | 1997-12-25 | 1999-06-30 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit |
| US6087855A (en) * | 1998-06-15 | 2000-07-11 | International Business Machines Corporation | High performance dynamic multiplexers without clocked NFET |
| WO2001040947A1 (en) * | 1999-12-06 | 2001-06-07 | Infineon Technologies North America Corp. | Fuse latch having multiplexers with reduced sizes and lower power consumption |
| US6693785B1 (en) * | 1999-12-14 | 2004-02-17 | Koninklijke Philips Electronics N.V. | Electronic component with reduced inductive coupling |
| WO2001045260A1 (en) * | 1999-12-14 | 2001-06-21 | Koninklijke Philips Electronics N.V. | Electronic component with reduced inductive coupling |
| US20030076821A1 (en) * | 2001-10-19 | 2003-04-24 | Fujitsu Limited | Multiplexer circuit for converting parallel data into serial data at high speed and synchronized with a clock signal |
| US7154918B2 (en) | 2001-10-19 | 2006-12-26 | Fujitsu Limited | Multiplexer circuit for converting parallel data into serial data at high speed and synchronized with a clock signal |
| US20050083107A1 (en) * | 2003-07-28 | 2005-04-21 | Elixent Limited | Methods and systems for reducing leakage current in semiconductor circuits |
| US7233197B2 (en) | 2003-07-28 | 2007-06-19 | Panasonic Europe Ltd. | Methods and systems for reducing leakage current in semiconductor circuits |
| US20070241811A1 (en) * | 2003-07-28 | 2007-10-18 | Alan Marshall | Methods and Systems for Reducing Leakage Current in Semiconductor Circuits |
| US7315201B2 (en) | 2003-07-28 | 2008-01-01 | Panasonic Europe Ltd. | Methods and systems for reducing leakage current in semiconductor circuits |
| WO2011035519A1 (en) * | 2009-09-23 | 2011-03-31 | 惠州市正源微电子有限公司 | Radio frequency power synthesis circuit |
| CN101667854B (en) * | 2009-09-23 | 2013-02-13 | 惠州市正源微电子有限公司 | Radio-frequency power composite circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09116405A (en) | 1997-05-02 |
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