US5506155A - Method for manufacturing a substrate for semiconductor device using a selective gettering technique - Google Patents

Method for manufacturing a substrate for semiconductor device using a selective gettering technique Download PDF

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US5506155A
US5506155A US08/184,642 US18464294A US5506155A US 5506155 A US5506155 A US 5506155A US 18464294 A US18464294 A US 18464294A US 5506155 A US5506155 A US 5506155A
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substrate
semiconductor device
manufacturing
wafer
layer
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Hiroyuki Kaigawa
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing

Definitions

  • the present invention relates to method for a manufacturing a substrate for a semiconductor device and more particularly, gettering impurities in the substrate.
  • a semiconductor device is formed on a thin substrate referred to as a wafer.
  • the wafer contains impurities, such as, Fe, etc., therein.
  • FIG. 1A and FIG. 1B illustrate particles 10 of the polysilicon layer formed on the bottom surface of the wafer.
  • FIG. 1A and FIG. 1B are shown upside down, meaning the bottom surface of the wafer is shown in the up side of the figures and the top surface of the wafer is shown in the down side of the figures.
  • the particles 10 of the polysilicon layer are grown as illustrated in FIG. 1B.
  • distortion ST1 occurs at a surface S1 of the wafer 1 where the wafer faces particles 10 of the polysilicon layer.
  • a distortion ST2 occurs at a surface S1 of the wafer 1 where the particles 10 of the polysilicon layer overlap each other.
  • Contained impurities such as Fe, etc. of the wafer 1 are trapped in the distortions. That is, on carrying out heat treatment to the wafer 1 on which a polysilicon layer is formed, the contained impurities in the wafer 1 are effectively trapped in the distortions.
  • a poly silicon layer 20 is formed on top and bottom surfaces of wafer 1 as illustrated in FIG. 2A, utilizing the CVD(Chemical Vapor Deposition) method (see FIG. 2B), replace removing the polysilicon layer 20 on the top surface of the wafer 1 (up side of FIG. 2) by chemical etching the polysilicon layer 20 exists on the bottom side of the wafer l (see FIG. 2C). Then, the distortions occur between the polysilicon layer 20 and the wafer l (see FIG. 1B).
  • the wafer 1 has relative stress against the polysilicon layer 20 to inside (as shown in by arrow 200 of FIG. 3A and FIG. 3B), while the polysilicon layer 20 formed on the bottom surface of the wafer 1 has relative stress against the wafer 1 to outside (as shown in an arrow 200 of FIG. 3A and FIG. 3B).
  • the discrepancies of these stresses between wafer l (the arrow 200) and the polysilicon layer 20 (the arrow 100) cause distortion ST10 and distortion ST20 (see FIG. 3A). Therefore, the impurities in the wafer are trapped in the distortion ST10 and distortion ST20.
  • wafer 1 has relative stress to the inside (the arrow 100 as shown in FIG. 3A and FIG. 3B), and the polysilicon layer 20 keeps relative stress to the out side (the arrow 200 as shown in FIG. 3A and 3B).
  • the polysilicon layer 20 still exists after the partial removal on the bottom surface of the wafer 1 as it is shown in FIG. 2C, the wafer 1 receives stress as illustrated by an arrow 300 in FIG. 3B. This is due to discrepancies of stress direction between wafer 1 (compression stress represented by arrow 100 in FIG. 3A and FIG. 3B) and the polysilicon layer 20 (stretch stress represented by the arrow 200 in FIG. 3A and FIG. 3B).
  • the wafer 1 Once the wafer 1 receives the stress represented by the arrow 300, the wafer 1 curves slightly as shown in FIG. 3B.
  • the stress represented by the arrow 300 causes curvature of the wafer 1 (see FIG. 3B).
  • the heat treatment accelerates the stress represented by the arrow 300, so that the wafer 1 curves more as shown in FIG. 3C.
  • the wafer 1 When the wafer 1 is curved as shown on FIG. 3C, it decreases the yield of semiconductor device production. Also the curved wafer affects the production steps of making a semiconductor device, especially the curvature affects the alignment step.
  • the curvature of the wafer 1 causes misalignment between center the part of the wafer 1 and the edge part of the wafer 1.
  • the misalignment to the wafer 1 decreases reliability of the semiconductor device, even when the curvature is slight. Accuracy of alignment is required, particularly for the steps of a highly integrated semiconductor device.
  • a method for manufacturing a substrate for a semiconductor device comprises the steps of;
  • FIG. 1A-1B are enlarged views illustrating particles 10 of the polysilicon layer being formed on bottom surface of a substrate.
  • FIG. 2A-2C are views illustrating steps of a conventional method for manufacturing a substrate for a semiconductor device.
  • FIG. 3A-3C are views illustrating the direction of relative stresses between the polysilicon layer 20 and the wafer 1 in the conventional method, and curvature of the wafer 1.
  • FIG. 4A-4D are views illustrating a method for manufacturing a substrate for a semiconductor device which is an embodiment of the present invention.
  • FIG. 5A-5C are views illustrating forms of a gettering layer which is formed on the bottom surface of the wafer 1, according to embodiments of the present invention.
  • FIG. 6 is a view illustrating the direction of relative stresses between the polysilicon layer 20 and wafer 1 according to the present invention.
  • FIG. 7A-7C are views illustrating another embodiment according to the present invention of a method for manufacturing a substrate for a semiconductor device.
  • FIG. 8A-8C are views illustrating far yet another embodiment according to the present invention of a method for manufacturing a substrate for a semiconductor device.
  • FIG. 9A-9B are views illustrating still another embodiment according to the present invention of a method for a manufacturing a substrate for semiconductor device.
  • a method for manufacturing a substrate for semiconductor device according to the present invention is described below.
  • the aforementioned gettering layer is formed on the bottom surface of the substrate.
  • a semiconductor device is formed on the top surface of the wafer.
  • a polysilicon layer 20 is formed on both the top surface and the bottom surface of the wafer 1 as a gettering layer by the CVD(Chemical Vapor Deposition) method(see FIG. 4B).
  • a photo resist layer (not shown) is formed on the bottom surface of the wafer 1 where the polysilicon layer 20 has been formed.
  • the polysilicon layer 20 is removed from the top surface of the wafer 1 by chemical etching (see FIG. 4C).
  • FIG. 5A shows an example of the existence of the polysilicon layer 20 which is formed selectively opposite side 30R of device formation region 30 on the bottom surface of the wafer 1.
  • the size of each one of the polysilicon layers 20 is approximately the same as a semiconductor device, for instance 10 mm by 20 mm rectangle shape.
  • Distortion ST50 and distortion ST60 occurred between the wafer 1 and the polysilicon layer 20 which are formed opposite side 30R of device formation region 30 (see FIG. 4D). Occurrence of the distortions causes stable absorption of impurities in the wafer 1. Therefore, purity of the device formation region 30 of the wafer 1 is increased. In addition to the purity at the device formation region 30, reliability of semiconductor device is also increased.
  • FIG. 6 illustrates the relationship of relative stress between the wafer 1 and the polysilicon layer 20 as shown in FIG. 4D.
  • wafer 1 has compressive stress to the inside (direction of arrow 100), and the polysilicon layer 20 has tensile stress to the outside (direction of arrow 200).
  • each tensile stress of the polysilicon layer 20 in this embodiment is released at each polysilicon layer 20 formed on the bottom surface of the wafer 1, (see FIG. 6).
  • This is completely different from the wafer shown in FIG. 3B. That is forming the polysilicon layer as shown in FIG. 6 releases the tensile stress to the outside (direction the arrow 200) at intermediate locations, and the wafer does not develop relative stress as represented by arrow 300 (see FIG. 3B). Therefore, when carrying out heat treatment, preferrably at 1200° C. or less not much curvature is caused to the wafer 1.
  • the wafer 1 has less curvature than one made with the conventional method, and yield of semiconductor devices is much increased. Also, the wafer 1 can be utilized in production of highly integrated semiconductor devices due to the high accuracy of alignment.
  • the polysilicon layer 20 on the bottom surface is removed selectively after removal of the polysilicon layer 20 from top surface of the wafer 1, the polysilicon layer 20 an both top surface and bottom surfaces can be removed (selectively) simultaneously, provided the polysilicon layers 20 can be removed in a predetermined fashion.
  • polysilicon layers 20 are formed on both top surface and bottom surface of the wafer 1 (see FIG. 4B), and then polysilicon layer 20 which is formed on top surface of the wafer 1 is removed. After the removal of the polysilicon 20 from top surface of the wafer 1, the polysilicon layer 20 which is formed on the bottom surface of wafer 1 is selectively removed by chemical etching (see FIG.4C FIG. 4D).
  • a polysilicon layer 20 is formed on the bottom surface of the wafer as it is shown in FIG. 7A. Then, the polysilicon layer 20 is removed from the bottom surface of the wafer 1, except opposite side 30R of device formation region 30. This means the polysilicon layer 20 is formed only opposite side 30R of device formation region 30. The removal forms the polysilicon layer 20 in lattice shape (see FIG. 5A).
  • heat treatment preferrably at 1200° C. or less is carried out on the wafer 1 on which lattice shaped polysilicon layer 20 is formed.
  • wafer 1 does not curve as it is shown in FIG. 3C.
  • impurities Fe etc, which are contained in device formation region 30 are trapped into distortions which occurred between wafer 1 and opposite side 30R of the device formation region 30. Therefore, purity of the device formation region is increased.
  • utilizing the wafer 1 in production of a semiconductor device contributes to improve the quality of the semiconductor device.
  • the polysilicon layer 20 has been removed selectively to form a gettering layer.
  • a polysilicon layer 20 is formed selectively on the bottom surface of the wafer 1.
  • a silicon oxide layer 3 is formed on the bottom surface of a wafer 1 which is shown in FIG. 8A by heat oxidation (see FIG. 8B). Then, a resist layer 40 is formed on the silicon oxide layer 3 except opposite side 30R of device formation region 30. Chemical etching is then carried out to remove the silicon oxide layer 3 opposite side 30R of device formation region 30. After the removal, a polysilicon layer 20 is formed on the bottom surface of the wafer 1 (FIG. 8C). The polysilicon layer 20 is ground mechanically until the height of the silicon oxide layer 3 and the polysilicon layer 20 are to equal (FIG. 9A). After the grind, the silicon oxide layer 3 is removed by chemical etching utilizing aqueous hydrogen fluoride (FIG. 9B). By carrying out these steps, a lattice shaped polysilicon layer 20 is formed on the bottom surface of the wafer 1, as it is shown in FIG. 9A and FIG. 5A.
  • a polysilicon layer 20 is utilized as a gettering layer.
  • a silicon nitride layer or a monocrystalline silicon layer is also applicable for the gettering layer, since it causes distortions at a surface of the wafer and traps impurities into the distortions.
  • a layer is applicable for a gettering layer which has a different lattice constant than the wafer 1.
  • the polysilicon layer 20 is formed on the wafer 1 in lattice shape (see FIG. 5A).
  • other shapes of gettering layers are possible, for instance, concentric circles and dotted shape, as shown in FIG. 5B and FIG. 5C can be applied instead of lattice shape; provided, that the other shapes of gettering layers cause the distortions to trap the impurities in the wafer, release relative stress to prevent curvature of the wafer.
  • size of the each gettering layer can be changed depending on the size of the semiconductor.

Abstract

It is an object of the present invention to provide a method for manufacturing a substrate for a semiconductor device which can increase efficiency of production of the substrate for a semiconductor device, and a method for manufacturing a substrate which can be utilized to produce a highly integrated semiconductor device. A polysilicon layer is formed on both the top surface and the bottom surface of the wafer (see FIG. 4B), before removing the polysilicon layer from the top surface of the wafer (see FIG. 4C). The polysilicon layer which remains on the bottom surface of the wafer is selectively removed, except in the device formation region (see FIG. 4D). Impurities (such as Fe or the like) contained in the wafer are trapped in distortion ST50 and distortion ST60 which occur between the wafer and the polysilicon layer. Since the polysilicon layer is formed separately on the bottom surface of the wafer, the tensile stress of the polysilicon layer is released. As a result, the wafer experiences less curvature, and it is possible to manufacture a substrate for the semiconductor device which can increase efficiency of production.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method for a manufacturing a substrate for a semiconductor device and more particularly, gettering impurities in the substrate.
2. Description of the Prior Art
Generally, a semiconductor device is formed on a thin substrate referred to as a wafer. Often, the wafer contains impurities, such as, Fe, etc., therein. Once a semiconductor device is formed in a device formation region of the wafer which contains impurities, the formed semiconductor device operates erroneously.
To remove the impurities from the device formation region of the wafer, a layer is formed on the bottom surface of the wafer and distortions are caused between the wafer and the layer. As a result, the impurities are trapped in the distortions which are formed on the bottom surface of the wafer. Then, the semiconductor device is formed on the top surface of the wafer. This technique is referred to as "gettering" to those skilled in the art. When the gettering function is provided from outside of the wafer, it is referred to as EG(Extrinsic Gettering).
The mechanism of EG will be described below. FIG. 1A and FIG. 1B illustrate particles 10 of the polysilicon layer formed on the bottom surface of the wafer. For easy reference, FIG. 1A and FIG. 1B are shown upside down, meaning the bottom surface of the wafer is shown in the up side of the figures and the top surface of the wafer is shown in the down side of the figures. When growing a polysilicon layer on the wafer, the particles 10 of the polysilicon layer are grown as illustrated in FIG. 1B. At the same time, distortion ST1 occurs at a surface S1 of the wafer 1 where the wafer faces particles 10 of the polysilicon layer. Also, a distortion ST2 occurs at a surface S1 of the wafer 1 where the particles 10 of the polysilicon layer overlap each other. Contained impurities such as Fe, etc. of the wafer 1 are trapped in the distortions. That is, on carrying out heat treatment to the wafer 1 on which a polysilicon layer is formed, the contained impurities in the wafer 1 are effectively trapped in the distortions.
Next, conventional gettering is described. A poly silicon layer 20 is formed on top and bottom surfaces of wafer 1 as illustrated in FIG. 2A, utilizing the CVD(Chemical Vapor Deposition) method (see FIG. 2B), replace removing the polysilicon layer 20 on the top surface of the wafer 1 (up side of FIG. 2) by chemical etching the polysilicon layer 20 exists on the bottom side of the wafer l (see FIG. 2C). Then, the distortions occur between the polysilicon layer 20 and the wafer l (see FIG. 1B).
Incidentally, the wafer 1 has relative stress against the polysilicon layer 20 to inside (as shown in by arrow 200 of FIG. 3A and FIG. 3B), while the polysilicon layer 20 formed on the bottom surface of the wafer 1 has relative stress against the wafer 1 to outside (as shown in an arrow 200 of FIG. 3A and FIG. 3B). The discrepancies of these stresses between wafer l (the arrow 200) and the polysilicon layer 20 (the arrow 100), cause distortion ST10 and distortion ST20 (see FIG. 3A). Therefore, the impurities in the wafer are trapped in the distortion ST10 and distortion ST20.
When, heat treatment is carried out to the wafer 1 which is shown in FIG. 2C, the trapping of is accelerated and the impurities are trapped in the distortions more effectively. After the heat treatment, the polysilicon layer 20 is partially removed from the wafer 1.
However, wafer 1 has relative stress to the inside (the arrow 100 as shown in FIG. 3A and FIG. 3B), and the polysilicon layer 20 keeps relative stress to the out side (the arrow 200 as shown in FIG. 3A and 3B). Provided, the polysilicon layer 20 still exists after the partial removal on the bottom surface of the wafer 1 as it is shown in FIG. 2C, the wafer 1 receives stress as illustrated by an arrow 300 in FIG. 3B. This is due to discrepancies of stress direction between wafer 1 (compression stress represented by arrow 100 in FIG. 3A and FIG. 3B) and the polysilicon layer 20 (stretch stress represented by the arrow 200 in FIG. 3A and FIG. 3B). Once the wafer 1 receives the stress represented by the arrow 300, the wafer 1 curves slightly as shown in FIG. 3B. The stress represented by the arrow 300 causes curvature of the wafer 1 (see FIG. 3B). Furthermore, the heat treatment accelerates the stress represented by the arrow 300, so that the wafer 1 curves more as shown in FIG. 3C.
When the wafer 1 is curved as shown on FIG. 3C, it decreases the yield of semiconductor device production. Also the curved wafer affects the production steps of making a semiconductor device, especially the curvature affects the alignment step. The curvature of the wafer 1 causes misalignment between center the part of the wafer 1 and the edge part of the wafer 1. The misalignment to the wafer 1 decreases reliability of the semiconductor device, even when the curvature is slight. Accuracy of alignment is required, particularly for the steps of a highly integrated semiconductor device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for a manufacturing a substrate for semiconductor device which will increase efficiency of production of the substrate for semiconductor device, and a method for manufacturing a substrate which can be utilized in the production of highly integrated semiconductor devices.
A method for manufacturing a substrate for a semiconductor device comprises the steps of;
a) forming a gettering layer on top and bottom surfaces of the substrate;
b) removing the gettering layer on the top surface of the substrate;
c) selectively removing the gettering layer on the bottom surface of the substrate.
While the novel features of the invention are set forth in a general fashion, both as to organization and content, the invention will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A-1B are enlarged views illustrating particles 10 of the polysilicon layer being formed on bottom surface of a substrate.
FIG. 2A-2C are views illustrating steps of a conventional method for manufacturing a substrate for a semiconductor device.
FIG. 3A-3C are views illustrating the direction of relative stresses between the polysilicon layer 20 and the wafer 1 in the conventional method, and curvature of the wafer 1.
FIG. 4A-4D are views illustrating a method for manufacturing a substrate for a semiconductor device which is an embodiment of the present invention;
FIG. 5A-5C are views illustrating forms of a gettering layer which is formed on the bottom surface of the wafer 1, according to embodiments of the present invention.
FIG. 6 is a view illustrating the direction of relative stresses between the polysilicon layer 20 and wafer 1 according to the present invention.
FIG. 7A-7C are views illustrating another embodiment according to the present invention of a method for manufacturing a substrate for a semiconductor device.
FIG. 8A-8C are views illustrating far yet another embodiment according to the present invention of a method for manufacturing a substrate for a semiconductor device.
FIG. 9A-9B are views illustrating still another embodiment according to the present invention of a method for a manufacturing a substrate for semiconductor device.
DESCRIPTION OF THE PREFERRED EMBODIMENT
A method for manufacturing a substrate for semiconductor device according to the present invention is described below. In this embodiment for making a substrate for a semiconductor device, the aforementioned gettering layer is formed on the bottom surface of the substrate. In this case, a semiconductor device is formed on the top surface of the wafer. First, a polysilicon layer 20 is formed on both the top surface and the bottom surface of the wafer 1 as a gettering layer by the CVD(Chemical Vapor Deposition) method(see FIG. 4B). Then, a photo resist layer (not shown) is formed on the bottom surface of the wafer 1 where the polysilicon layer 20 has been formed. After forming the photo resist layer, the polysilicon layer 20 is removed from the top surface of the wafer 1 by chemical etching (see FIG. 4C).
Subsequently, another photo resist layer 40 is formed on the opposite side of the device formation region 30 in which the device is formed as shown in FIG. 4C. Then, the polysilicon layer 20 is selectively removed from the bottom surface of the wafer 1, except opposite side 30R of device formation region 30 (see FIG. 4D). Removing the polysilicon layer 20 selectively from the bottom surface of the wafer 1 makes the polysilicon layer 20 only exist on opposite side 30R of device formation region 30. FIG. 5A shows an example of the existence of the polysilicon layer 20 which is formed selectively opposite side 30R of device formation region 30 on the bottom surface of the wafer 1. In this embodiment, the size of each one of the polysilicon layers 20 is approximately the same as a semiconductor device, for instance 10 mm by 20 mm rectangle shape.
Distortion ST50 and distortion ST60 occurred between the wafer 1 and the polysilicon layer 20 which are formed opposite side 30R of device formation region 30 (see FIG. 4D). Occurrence of the distortions causes stable absorption of impurities in the wafer 1. Therefore, purity of the device formation region 30 of the wafer 1 is increased. In addition to the purity at the device formation region 30, reliability of semiconductor device is also increased.
FIG. 6 illustrates the relationship of relative stress between the wafer 1 and the polysilicon layer 20 as shown in FIG. 4D. As described above, wafer 1 has compressive stress to the inside (direction of arrow 100), and the polysilicon layer 20 has tensile stress to the outside (direction of arrow 200). However, each tensile stress of the polysilicon layer 20 in this embodiment is released at each polysilicon layer 20 formed on the bottom surface of the wafer 1, (see FIG. 6). This is completely different from the wafer shown in FIG. 3B. That is forming the polysilicon layer as shown in FIG. 6 releases the tensile stress to the outside (direction the arrow 200) at intermediate locations, and the wafer does not develop relative stress as represented by arrow 300 (see FIG. 3B). Therefore, when carrying out heat treatment, preferrably at 1200° C. or less not much curvature is caused to the wafer 1.
As described above, the wafer 1 has less curvature than one made with the conventional method, and yield of semiconductor devices is much increased. Also, the wafer 1 can be utilized in production of highly integrated semiconductor devices due to the high accuracy of alignment.
Although, the polysilicon layer 20 on the bottom surface is removed selectively after removal of the polysilicon layer 20 from top surface of the wafer 1, the polysilicon layer 20 an both top surface and bottom surfaces can be removed (selectively) simultaneously, provided the polysilicon layers 20 can be removed in a predetermined fashion.
Another embodiment will be described below. In the aforementioned embodiment, polysilicon layers 20 are formed on both top surface and bottom surface of the wafer 1 (see FIG. 4B), and then polysilicon layer 20 which is formed on top surface of the wafer 1 is removed. After the removal of the polysilicon 20 from top surface of the wafer 1, the polysilicon layer 20 which is formed on the bottom surface of wafer 1 is selectively removed by chemical etching (see FIG.4C FIG. 4D).
However, in the present embodiment a polysilicon layer 20 is formed on the bottom surface of the wafer as it is shown in FIG. 7A. Then, the polysilicon layer 20 is removed from the bottom surface of the wafer 1, except opposite side 30R of device formation region 30. This means the polysilicon layer 20 is formed only opposite side 30R of device formation region 30. The removal forms the polysilicon layer 20 in lattice shape (see FIG. 5A).
Subsequently, heat treatment preferrably at 1200° C. or less is carried out on the wafer 1 on which lattice shaped polysilicon layer 20 is formed. During and after the heat treatment, wafer 1 does not curve as it is shown in FIG. 3C. Furthermore, impurities (Fe etc,) which are contained in device formation region 30 are trapped into distortions which occurred between wafer 1 and opposite side 30R of the device formation region 30. Therefore, purity of the device formation region is increased. As a result, utilizing the wafer 1 in production of a semiconductor device contributes to improve the quality of the semiconductor device.
Under this embodiment, it is not necessary to carry out etching to the polysilicon layer 20 on the top surface of the wafer 1. Rather in forming the polysilicon layer 20 on the bottom surface of the wafer 1, the top surface of the wafer 1 is faced completely to a bench.
Another embodiment of the method for manufacturing a substrate for semiconductor device will be described below. With the aforementioned embodiments of the present invention, the polysilicon layer 20 has been removed selectively to form a gettering layer. However, under this embodiment, a polysilicon layer 20 is formed selectively on the bottom surface of the wafer 1.
Initially, a silicon oxide layer 3 is formed on the bottom surface of a wafer 1 which is shown in FIG. 8A by heat oxidation (see FIG. 8B). Then, a resist layer 40 is formed on the silicon oxide layer 3 except opposite side 30R of device formation region 30. Chemical etching is then carried out to remove the silicon oxide layer 3 opposite side 30R of device formation region 30. After the removal, a polysilicon layer 20 is formed on the bottom surface of the wafer 1 (FIG. 8C). The polysilicon layer 20 is ground mechanically until the height of the silicon oxide layer 3 and the polysilicon layer 20 are to equal (FIG. 9A). After the grind, the silicon oxide layer 3 is removed by chemical etching utilizing aqueous hydrogen fluoride (FIG. 9B). By carrying out these steps, a lattice shaped polysilicon layer 20 is formed on the bottom surface of the wafer 1, as it is shown in FIG. 9A and FIG. 5A.
Through all the embodiments above, a polysilicon layer 20 is utilized as a gettering layer. However, a silicon nitride layer or a monocrystalline silicon layer is also applicable for the gettering layer, since it causes distortions at a surface of the wafer and traps impurities into the distortions. Furthermore, a layer is applicable for a gettering layer which has a different lattice constant than the wafer 1.
Moreover, all the above embodiments described that the polysilicon layer 20 is formed on the wafer 1 in lattice shape (see FIG. 5A). However, other shapes of gettering layers are possible, for instance, concentric circles and dotted shape, as shown in FIG. 5B and FIG. 5C can be applied instead of lattice shape; provided, that the other shapes of gettering layers cause the distortions to trap the impurities in the wafer, release relative stress to prevent curvature of the wafer. Also, size of the each gettering layer can be changed depending on the size of the semiconductor.
Although the invention has been described in its preferred form with a certain degree of particularity, it is understood that the present disclosure of the preferred form can be changed in the details of its construction and any combination and arrangement of parts may be resorted to without departing from the spirit and the scope of the invention as hereinafter claimed.

Claims (27)

What is claimed is:
1. A method for manufacturing a substrate for a semiconductor device, comprising the steps of:
a) preparing a substrate;
b) forming a gettering layer which has a different lattice constant from the substrate, on top and bottom planar surfaces of the substrate;
c) removing the gettering layer on the top surface of the substrate;
d) selectively removing the gettering layer on the bottom surface of the substrate so that said gettering layer only exists on said substrate opposite a formation region for said semiconductor device.
2. A method for manufacturing a substrate for a semiconductor device in accordance with claim 1, wherein said gettering layer is a polysilicon layer.
3. A method for manufacturing a substrate for a semiconductor device in accordance with claim 1, wherein said gettering layer is a monocrystalline silicon layer.
4. A method for manufacturing a substrate for a semiconductor device in accordance with claim 1, wherein said gettering layer is a silicon nitride layer.
5. A method for manufacturing a substrate for a semiconductor device in accordance with claim 1, wherein said gettering layer is formed in a lattice shape.
6. A method for manufacturing a substrate for a semiconductor device in accordance with claim 1, wherein said gettering layer is formed in a concentric ring shape.
7. A method for manufacturing a substrate for a semiconductor device in accordance with claim 1, wherein said gettering layer is formed in dots.
8. A method for manufacturing a substrate for a semiconductor device in accordance with claim 1, wherein heat treatment is carried out after selectively removing the gettering layer on the bottom of the substrate.
9. A method for manufacturing a substrate for a semiconductor device in accordance with claim 8, wherein heat treatment is carried out at 1200° C. or less.
10. A method for manufacturing a substrate for a semiconductor device, comprising the steps of:
a) preparing a substrate having a bottom planar surface;
b) forming on selected portions of the bottom planar surface of the substrate a gettering layer which has a different lattice constant than the substrate; and,
c) selectively removing the gettering layer.
11. A method for manufacturing a substrate for a semiconductor device in accordance with claim 10, wherein said gettering layer is a polysilicon layer.
12. A method for manufacturing a substrate for a semiconductor device in accordance with claim 10, wherein said gettering layer is a monocrystalline silicon layer.
13. A method for manufacturing a substrate for a semiconductor device in accordance with claim 10, wherein said gettering layer is a silicon nitride layer.
14. A method for manufacturing a substrate for a semiconductor device in accordance with claim 10, wherein said gettering layer is formed in lattice shapes.
15. A method for manufacturing a substrate for a semiconductor device in accordance with claim 10, wherein said gettering layer is formed in concentric ring shapes.
16. A method for manufacturing a substrate for a semiconductor device in accordance with claim 10, wherein said gettering layer is formed in dots.
17. A method for manufacturing a substrate for a semiconductor device in accordance with claim 10, wherein after selectively removing the gettering layer, heat treatment is carried out.
18. A method for manufacturing a substrate for a semiconductor device in accordance with claim 17, wherein the heat treatment is carried out at 1200° C. or less.
19. A method for manufacturing a substrate for a semiconductor device, comprising the steps of:
a) preparing a substrate with a bottom surface;
b) selectively forming on the bottom surface of the substrate an oxide layer;
c) selectively forming on the bottom surface of the substrate on portions not covered by the oxide layer a gettering layer which has a different lattice constant than the substrate; and
d) removing the oxide layer.
20. A method for manufacturing a substrate for a semiconductor device in accordance with claim 19, wherein said gettering layer is a polysilicon layer.
21. A method for manufacturing a substrate for a semiconductor device in accordance with claim 19, wherein said gettering layer is a monocrystalline silicon layer.
22. A method for manufacturing a substrate for a semiconductor device in accordance with claim 19, wherein said gettering layer is a silicon nitride layer.
23. A method for manufacturing a substrate for a semiconductor device in accordance with claim 19, wherein said gettering layer is formed in lattice shapes.
24. A method for manufacturing a substrate for a semiconductor device in accordance with claim 19, wherein said gettering layer is formed in concentric ring shapes.
25. A method for manufacturing a substrate for a semiconductor device in accordance with claim 19, wherein said gettering layer is formed in dots.
26. A method for manufacturing a substrate for a semiconductor device in accordance with claim 19, wherein after said gettering layer forming steps, heat treatment is carried out.
27. A method for manufacturing a substrate for a semiconductor device in accordance with claim 26, wherein the heat treatment is carried out at 1200° C. or less.
US08/184,642 1993-06-18 1994-01-21 Method for manufacturing a substrate for semiconductor device using a selective gettering technique Expired - Lifetime US5506155A (en)

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US5899708A (en) * 1996-06-11 1999-05-04 Semiconductor Energy Laboratory Co., Ltd. Method for forming a thin film transistor using an electrostatic shield
US6146980A (en) * 1997-06-04 2000-11-14 United Microelectronics Corp. Method for manufacturing silicon substrate having gettering capability
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US20060226557A1 (en) * 2005-04-06 2006-10-12 Akihito Yamamoto Semiconductor substrate with occurrence of slip suppressed and method of manufacturing the same
US20090023300A1 (en) * 2007-07-18 2009-01-22 Nanya Technology Corporation Method of forming shadow layer on the wafer bevel
US20150372049A1 (en) * 2014-06-23 2015-12-24 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device

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JP3929557B2 (en) * 1997-07-30 2007-06-13 三菱電機株式会社 Semiconductor device and manufacturing method thereof
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US5789308A (en) * 1995-06-06 1998-08-04 Advanced Micro Devices, Inc. Manufacturing method for wafer slice starting material to optimize extrinsic gettering during semiconductor fabrication
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US5899708A (en) * 1996-06-11 1999-05-04 Semiconductor Energy Laboratory Co., Ltd. Method for forming a thin film transistor using an electrostatic shield
US6146980A (en) * 1997-06-04 2000-11-14 United Microelectronics Corp. Method for manufacturing silicon substrate having gettering capability
US20060180891A1 (en) * 2004-03-12 2006-08-17 Nec Electronics Corporation Semiconductor storage device, semiconductor device, and manufacturing method therefor
US20080099883A1 (en) * 2004-03-12 2008-05-01 Nec Electronics Corporation Semiconductor storage device, semiconductor device, and manufacturing method therefor
US7790579B2 (en) * 2004-03-12 2010-09-07 Nec Electronics Corporation Semiconductor storage device, semiconductor device, and manufacturing method therefor
US8039940B2 (en) * 2004-03-12 2011-10-18 Renesas Electronics Corporation Semiconductor storage device, semiconductor device, and manufacturing method therefor
US20060226557A1 (en) * 2005-04-06 2006-10-12 Akihito Yamamoto Semiconductor substrate with occurrence of slip suppressed and method of manufacturing the same
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US7696108B2 (en) * 2007-07-18 2010-04-13 Nanya Technology Corporation Method of forming shadow layer on the wafer bevel
US20150372049A1 (en) * 2014-06-23 2015-12-24 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device

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