US5465341A - Verifiable security circuitry for preventing unauthorized access to programmed read only memory - Google Patents

Verifiable security circuitry for preventing unauthorized access to programmed read only memory Download PDF

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Publication number
US5465341A
US5465341A US07/965,635 US96563592A US5465341A US 5465341 A US5465341 A US 5465341A US 96563592 A US96563592 A US 96563592A US 5465341 A US5465341 A US 5465341A
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Prior art keywords
security
bit
data bit
programmable read
security data
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US07/965,635
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Bryan C. Doi
Steven D. Thomas
Vincent J. Coli
Vito D. Giglio
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NXP BV
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VLSI Technology Inc
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Priority to US07/965,635 priority Critical patent/US5465341A/en
Assigned to VLSI TECHNOLOGY, INC. reassignment VLSI TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: COLI, VINCENT J.
Assigned to VLSI TECHNOLOGY, INC. reassignment VLSI TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GIGLIO, VITO DI, THOMAS, STEVEN D., DOI, BRYAN C.
Priority to DE69303827T priority patent/DE69303827T2/en
Priority to PCT/US1993/010189 priority patent/WO1994010687A1/en
Priority to JP6511219A priority patent/JPH08503093A/en
Priority to EP93925027A priority patent/EP0665979B1/en
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Publication of US5465341A publication Critical patent/US5465341A/en
Assigned to NXP B.V. reassignment NXP B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PHILIPS SEMICONDUCTORS INC.
Assigned to PHILIPS SEMICONDUCTORS VLSI INC. reassignment PHILIPS SEMICONDUCTORS VLSI INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: VLSI TECHNOLOGY, INC.
Assigned to PHILIPS SEMICONDUCTORS INC. reassignment PHILIPS SEMICONDUCTORS INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: PHILIPS SEMICONDUCTORS VLSI INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. SECURITY AGREEMENT Assignors: NXP B.V.
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Assigned to NXP B.V. reassignment NXP B.V. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells

Definitions

  • the present invention concerns the provision of a method and circuitry to protect a programmable read-only memory (PROM) or programmable logic array within an integrated circuit from unauthorized access.
  • PROM programmable read-only memory
  • VLSI very large scale integrated
  • a security system for programmable read-only memory locations within a VLSI circuit is presented.
  • a first security bit memory location there is stored a first security data bit.
  • the first security data bit has a first value when the first security bit memory location is unprogrammed and a second value when the first security bit memory location is programmed.
  • a second security bit memory location there is stored a second security data bit.
  • the second security data bit has the first value when the second security bit memory location is unprogrammed and the second value when the second security bit memory location is programmed.
  • a selection logic is electrically coupled to the first security bit memory location and the second security bit memory location.
  • the selection logic selects no security data bit, the first security data bit or the second security data bit to be used to generate a security access signal.
  • An access logic allows and prevents direct access, by any device outside the VLSI circuit, to the programmable read-only memory locations in response to the security access signal.
  • the access logic prevents any device outside the VLSI circuit direct access to the programmable read-only memory locations when the selection logic selects no security data bit, when the selection logic selects the first security bit and the first security data bit has the second value, or when the selection logic selects the second security bit and the second security data bit has the second value.
  • the VLSI circuit includes additional logic circuitry.
  • the selection logic includes a first multiplexor which selects between data on address lines from the additional logic circuitry and data on input pins of the VLSI circuit to be connected to input address lines for the programmable read only memory locations.
  • the selection logic additionally includes a second multiplexor which selects between data lines for the additional logic circuitry and output pins of the VLSI circuit to receive data from the programmable read only memory locations.
  • the additional logic circuitry generates a test bit. Additionally, the access logic does not allow any device outside the VLSI circuit direct access to the programmable read-only memory locations when the test bit has the second value.
  • the programmable read-only memory locations are arranged in a memory array within a PROM.
  • the PROM additionally includes an address decoder, a test row, a test column, the first security bit memory location and the second security bit memory location.
  • the VLSI circuit may additionally include program logic which provides a programming voltage to the programmable read-only memory locations.
  • the program logic includes an enable/disable logic for preventing programming when the selection, logic selects no security data bit, when the selection logic selects the first security bit and the first security data bit has the second value, or when the selection logic selects the second security bit and the second security data bit has the second value.
  • the security system has the advantage of being testable. For example, once the test memory locations have been programmed, the first security memory bit may be programmed. Once the first security memory bit is programmed, the first security memory bit is selected and it is verified that no device outside the VLSI circuit can access the programmable read-only memory locations. The end user then can program and protect the programmable read-only memory locations by first selecting the second security memory bit. Then, the programmable read-only memory locations may be programmed. Afterwards, the second security memory bit is programmed, thereby preventing subsequent unauthorized access to the programmable read-only memory locations.
  • FIG. 1 shows implementation of security logic in an integrated circuit, in accordance with the preferred embodiment of the present invention.
  • FIG. 2 shows the arrangement of a testable programmable read only memory in accordance with the preferred embodiment of the present invention.
  • FIG. 3 is a flowchart which describes a process for testing the security feature of a VLSI circuit in accordance with a preferred embodiment of the present invention.
  • FIG. 4 is a flowchart which describes a process which a customer follows to program and test a part in accordance with a preferred embodiment of the present invention.
  • FIG. 1 shows a block diagram of circuitry which implements security for a programmable read only memory (PROM) 15 which is within a VLSI circuit.
  • IC logic circuitry 14 within the VLSI circuit controls operation of the VLSI circuit. Under normal operating conditions, when PROM 15 is accessed, a multiplexor 13 selects an address on lines 33 to be forwarded to PROM 15 on address lines 32. In response, IC logic circuitry 14 receives data from PROM 15 through PROM output lines 27.
  • IC logic circuitry 14 controls the interface of the VLSI circuit to other devices.
  • IC logic circuitry 14 receives data through input pins 10 via lines 22.
  • a multiplexor 16 selects data on logic output lines 26 to be connected to output pins 17.
  • multiplexor 13 selects an address on lines 22 from input pins 10 to be forwarded to PROM 15 on address lines 32.
  • Multiplexor 16 selects data on PROM output lines 27 to be connected to output pins 17.
  • program logic 11 provides programming voltages to PROM 15 through lines 25.
  • a selection input to multiplexor 13 and a selection input to multiplexor 16 are controlled respectively by a logical AND gate 18 and a logical AND gate 19.
  • the function of logical AND gate 18 and logical AND gate 19 may be accomplished by a single logical AND gate.
  • Logical AND gate 18 and logical AND gate 19 each performs a logical AND operation on a test/program bit and a security bit.
  • the test/program bit is generated by IC logic circuitry 14 and placed on a line 30.
  • the security bit is supplied by PROM 15 and placed on a line 29.
  • Program logic 11 also receives the security bit on line 29 which serves to enable/disable program logic 11.
  • multiplexor 13 selects an address on lines 22 to be connected to address lines 32 and multiplexor 16 selects data on PROM output lines 27 to be connected to output pins 17. Therefore, memory locations within PROM 15 may be programmed and accessed by devices outside the VLSI circuit.
  • multiplexor 13 selects the address on lines 33 to be connected to address lines 32 and multiplexor 16 selects the data on logic output lines 26 to be connected to output pins 17. Therefore, memory locations within PROM 15 cannot be programmed or accessed by devices outside the VLSI circuit.
  • two locations within PROM 15 are able to provide the security bit on line 29.
  • Security bit address lines 21 are used to access the first security bit, the second security bit or no security bit.
  • FIG. 2 shows a simplified block diagram of PROM 15.
  • Memory array 50 contains, for example, 64 rows of 8 one-bit memory locations.
  • An address decoder 53 receives an address on address lines 32 and generates a row select activating a selected row. In normal operation, data values stored by the selected row appear on data lines 40, 41, 42, 43, 44, 45, 46 and 47. This data is then forwarded to PROM output lines 27.
  • address decoder 53 receives an address on address lines 32 and generates a row select activating a selected row.
  • a programming voltage through lines 25 is placed on various of programming lines 60, 61, 62, 63, 64, 65, 66 and 67.
  • unprogrammed memory cells store a data value of logic 1 and programmed memory cells store a data value of logic 0.
  • unprogrammed memory cells store a data value of logic 0 and programmed memory cells store a data value of logic 1.
  • PROM 15 may include a test row 52 and a test column 51.
  • the integrity of programming lines 60, 61, 62, 63, 64, 65, 66 and 67 and data lines 40, 41, 42, 43, 44, 45, 46 and 47 may be checked by programming and verifying values in test row 52.
  • the operation of address decoder 53 may be checked by programming and verifying values in test column 51.
  • Test column 51 is programmed using a programming line 68. For more complete testing, an additional test row may be placed below memory array 50.
  • two memory cells within PROM 15 are used to store security bits.
  • One or none of the security bit locations are selected by a security bit decoder 70, based on a value on security bit address lines 21.
  • security bit decoder activates a security bit selection line 23.
  • security bit decoder activates a security bit selection line 24.
  • the value in the selected memory location appears on line 29.
  • the selected memory bit location may also be programmed using a programming line 69.
  • each security bit memory cell when unprogrammed, each security bit memory cell stores a data value of logic 1.
  • each security bit memory cell stores a data value of logic 0.
  • each security bit memory cell when unprogrammed, stores a data value of logic 0. When programmed, each security bit memory cell stores a data value of logic 1. The actual position of the security bit memory location within PROM 15 should be concealed as well as possible to prevent defeat of the security feature by an unauthorized person.
  • FIG. 3 is a flowchart which describes a process for testing the security feature of a VLSI circuit by a device external to the VLSI circuit in accordance with a preferred embodiment of the present invention.
  • IC logic circuitry 14 sets the test/program bit on line 30 to logic 1.
  • a step 80 no security bit is selected by the address on security bit address lines 21.
  • a step 81 an attempt is made to access and program memory locations within memory array 50.
  • a step 82 the first security bit is selected and program memory locations are checked to see if any were programmed or accessed in step 81.
  • a step 83 is a branching step. If any memory locations were successfully programmed, in a step 89 the VLSI circuit is rejected. Otherwise, in a step 84, the first security bit location is selected by the address on security bit address lines 21. In a step 85, an attempt is made to access and program memory locations within the test row(s) and/or test column(s). In a step 86, the programmed memory locations are checked to see if they were successfully programmed in step 85.
  • a step 87 is a branching step. If any memory locations were not successfully programmed, in step 89 the VLSI circuit is rejected. Otherwise, in a step 88, the first security bit is programmed. In a step 90, the first security bit location is selected by the address on security bit address lines 21. In a step 91, an attempt is made to access and program memory locations within memory array 50. In a step 92, the second security bit is selected and program memory locations are checked to see if any were programmed or accessed in step 91.
  • a step 93 is a branching step. If any memory locations were successfully programmed, in step 89 the VLSI circuit is rejected. Otherwise, in a step 94, the second security bit location is selected by the address on security bit address lines 21. In a step 95, an attempt is made to access and program memory locations within memory array 50. In a step 96, program memory locations are checked to see if any were programmed or accessed in step 95.
  • a step 97 is a branching step. If any memory locations were not successfully programmed, in step 89 the VLSI circuit is rejected. Otherwise, in a step 98, after all other testing is complete, the VLSI circuit may be shipped to the customer.
  • FIG. 4 describes a process by which a customer programs and tests the shipped part.
  • the customer selects the second security bit.
  • the customer programs memory locations within memory array 50.
  • the customer verifies the programmed data.
  • a step 104 is a branching step. If any memory locations were not successfully programmed, in a step 110, the VLSI circuit is rejected. Otherwise, in a step 105, the second security bit is programmed. In a step 106, the second security bit is selected. In a step 107, an attempt is made to access memory locations within memory array 50.
  • a step 108 is a branching step. If any memory locations were successfully accessed, in step 110, the VLSI circuit is rejected. Otherwise, in a step 109, the VLSI circuit is ready for further testing or to be utilized in a computing system.

Abstract

A security system is used for programmable read-only memory locations within a very large scale integrated (VLSI) circuit. In a first security bit memory location there is stored a first security data bit. The first security data bit has a first value when the first security bit memory location is unprogrammed and a second value when the first security bit memory location is programmed. In a second security bit memory location there is stored a second security data bit. The second security data bit has the first value when the second security bit memory location is unprogrammed and the second value when the second security bit memory location is programmed. A selection logic is electrically coupled to the first security bit memory location and the second security bit memory location. The selection logic selects no security data bit, the first security data bit or the second security data bit to be used to generate a security access signal. An access logic allows and prevents direct access, by any device outside the VLSI circuit, to the programmable read-only memory locations in response to the security access signal. The access logic prevents any device outside the VLSI circuit direct access to the programmable read-only memory locations when the selection logic selects no security data bit, when the selection logic selects the first security bit and the first security data bit has the second value, or when the selection logic selects the second security bit and the second security data bit has the second value.

Description

BACKGROUND
The present invention concerns the provision of a method and circuitry to protect a programmable read-only memory (PROM) or programmable logic array within an integrated circuit from unauthorized access.
Once a PROM or programmable array of logic within a very large scale integrated (VLSI) circuit has been programmed and verified, it is often desirable to prevent further access by other than logic internal to the VLSI circuit. The restriction of access may be, for example, to prevent further programming of the PROM or to prevent examination of the contents of the PROM.
In the prior art, the burning of a security fuse has been used after programming a programmable array of logic (PAL) to prevent further programming. However, the use of such a security fuse could cause difficulty when applied to a PROM within an integrated circuit. Particularly, in the prior art, there is no way for a manufacture to test the integrity of the security which implements the security fuse prior to use by a user. The inability to test the security logic would, if the security logic were utilized in a PROM, result in a manufacturer being required to develop a very reliable manufacturing process in order to guarantee the shipment of a high yield of working products.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a security system for programmable read-only memory locations within a VLSI circuit is presented. In a first security bit memory location there is stored a first security data bit. The first security data bit has a first value when the first security bit memory location is unprogrammed and a second value when the first security bit memory location is programmed. In a second security bit memory location there is stored a second security data bit. The second security data bit has the first value when the second security bit memory location is unprogrammed and the second value when the second security bit memory location is programmed. A selection logic is electrically coupled to the first security bit memory location and the second security bit memory location. The selection logic selects no security data bit, the first security data bit or the second security data bit to be used to generate a security access signal. An access logic allows and prevents direct access, by any device outside the VLSI circuit, to the programmable read-only memory locations in response to the security access signal. The access logic prevents any device outside the VLSI circuit direct access to the programmable read-only memory locations when the selection logic selects no security data bit, when the selection logic selects the first security bit and the first security data bit has the second value, or when the selection logic selects the second security bit and the second security data bit has the second value.
In the preferred embodiment of the present invention, the VLSI circuit includes additional logic circuitry. Additionally, the selection logic includes a first multiplexor which selects between data on address lines from the additional logic circuitry and data on input pins of the VLSI circuit to be connected to input address lines for the programmable read only memory locations. The selection logic additionally includes a second multiplexor which selects between data lines for the additional logic circuitry and output pins of the VLSI circuit to receive data from the programmable read only memory locations.
Also in the preferred embodiment of the present invention, the additional logic circuitry generates a test bit. Additionally, the access logic does not allow any device outside the VLSI circuit direct access to the programmable read-only memory locations when the test bit has the second value.
In one embodiment of the security system, the programmable read-only memory locations are arranged in a memory array within a PROM. The PROM additionally includes an address decoder, a test row, a test column, the first security bit memory location and the second security bit memory location. Also, the VLSI circuit may additionally include program logic which provides a programming voltage to the programmable read-only memory locations. The program logic includes an enable/disable logic for preventing programming when the selection, logic selects no security data bit, when the selection logic selects the first security bit and the first security data bit has the second value, or when the selection logic selects the second security bit and the second security data bit has the second value.
The security system has the advantage of being testable. For example, once the test memory locations have been programmed, the first security memory bit may be programmed. Once the first security memory bit is programmed, the first security memory bit is selected and it is verified that no device outside the VLSI circuit can access the programmable read-only memory locations. The end user then can program and protect the programmable read-only memory locations by first selecting the second security memory bit. Then, the programmable read-only memory locations may be programmed. Afterwards, the second security memory bit is programmed, thereby preventing subsequent unauthorized access to the programmable read-only memory locations.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows implementation of security logic in an integrated circuit, in accordance with the preferred embodiment of the present invention.
FIG. 2 shows the arrangement of a testable programmable read only memory in accordance with the preferred embodiment of the present invention.
FIG. 3 is a flowchart which describes a process for testing the security feature of a VLSI circuit in accordance with a preferred embodiment of the present invention.
FIG. 4 is a flowchart which describes a process which a customer follows to program and test a part in accordance with a preferred embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows a block diagram of circuitry which implements security for a programmable read only memory (PROM) 15 which is within a VLSI circuit. Integrated circuit (IC) logic circuitry 14 within the VLSI circuit controls operation of the VLSI circuit. Under normal operating conditions, when PROM 15 is accessed, a multiplexor 13 selects an address on lines 33 to be forwarded to PROM 15 on address lines 32. In response, IC logic circuitry 14 receives data from PROM 15 through PROM output lines 27.
Also, under normal operating conditions, IC logic circuitry 14 controls the interface of the VLSI circuit to other devices. IC logic circuitry 14 receives data through input pins 10 via lines 22. A multiplexor 16 selects data on logic output lines 26 to be connected to output pins 17.
When PROM 15 is programmed and verified, multiplexor 13 selects an address on lines 22 from input pins 10 to be forwarded to PROM 15 on address lines 32. Multiplexor 16 selects data on PROM output lines 27 to be connected to output pins 17. In response to values placed on input pins 10 and forwarded to program logic 11 through lines 20, program logic 11 provides programming voltages to PROM 15 through lines 25.
A selection input to multiplexor 13 and a selection input to multiplexor 16 are controlled respectively by a logical AND gate 18 and a logical AND gate 19. Alternately, as will be understood by persons of ordinary skill in the art, the function of logical AND gate 18 and logical AND gate 19 may be accomplished by a single logical AND gate. Logical AND gate 18 and logical AND gate 19 each performs a logical AND operation on a test/program bit and a security bit. The test/program bit is generated by IC logic circuitry 14 and placed on a line 30. The security bit is supplied by PROM 15 and placed on a line 29. Program logic 11 also receives the security bit on line 29 which serves to enable/disable program logic 11.
In the circuitry shown in FIG. 1, when both the test/program bit and the security bit are at logic 1, multiplexor 13 selects an address on lines 22 to be connected to address lines 32 and multiplexor 16 selects data on PROM output lines 27 to be connected to output pins 17. Therefore, memory locations within PROM 15 may be programmed and accessed by devices outside the VLSI circuit. When either the test/program bit or the security bit is at logic 0, multiplexor 13 selects the address on lines 33 to be connected to address lines 32 and multiplexor 16 selects the data on logic output lines 26 to be connected to output pins 17. Therefore, memory locations within PROM 15 cannot be programmed or accessed by devices outside the VLSI circuit.
As may be understood by a person of ordinary skill in the art, while the logic shown assumes the security bit and the test/program bit are active high, the logic shown may be easily modified to accommodate the situation where the security bit and/or the test/program bit are active low.
In the preferred embodiment of the present invention, two locations within PROM 15 are able to provide the security bit on line 29. Security bit address lines 21 are used to access the first security bit, the second security bit or no security bit.
FIG. 2 shows a simplified block diagram of PROM 15. Memory array 50 contains, for example, 64 rows of 8 one-bit memory locations. An address decoder 53 receives an address on address lines 32 and generates a row select activating a selected row. In normal operation, data values stored by the selected row appear on data lines 40, 41, 42, 43, 44, 45, 46 and 47. This data is then forwarded to PROM output lines 27. When memory location in memory array 50 are being programmed, address decoder 53 receives an address on address lines 32 and generates a row select activating a selected row. A programming voltage through lines 25 is placed on various of programming lines 60, 61, 62, 63, 64, 65, 66 and 67. A programming voltage on one of the programming lines results in the corresponding memory cell in the selected row being programmed. In one embodiment of the present invention, unprogrammed memory cells store a data value of logic 1 and programmed memory cells store a data value of logic 0. In an alternate embodiment of the present invention, unprogrammed memory cells store a data value of logic 0 and programmed memory cells store a data value of logic 1.
In order to aid in the factory test of the VLSI circuit, PROM 15 may include a test row 52 and a test column 51. In a test mode, the integrity of programming lines 60, 61, 62, 63, 64, 65, 66 and 67 and data lines 40, 41, 42, 43, 44, 45, 46 and 47 may be checked by programming and verifying values in test row 52. Likewise, the operation of address decoder 53 may be checked by programming and verifying values in test column 51. Test column 51 is programmed using a programming line 68. For more complete testing, an additional test row may be placed below memory array 50.
In the preferred embodiment of the present invention, two memory cells within PROM 15 are used to store security bits. One or none of the security bit locations are selected by a security bit decoder 70, based on a value on security bit address lines 21. When a first memory location is selected, security bit decoder activates a security bit selection line 23. When a second memory location is selected, security bit decoder activates a security bit selection line 24. The value in the selected memory location appears on line 29. The selected memory bit location may also be programmed using a programming line 69. In the disclosed embodiment of the present invention, when unprogrammed, each security bit memory cell stores a data value of logic 1. When programmed, each security bit memory cell stores a data value of logic 0. In an alternate embodiment of the present invention, when unprogrammed, each security bit memory cell stores a data value of logic 0. When programmed, each security bit memory cell stores a data value of logic 1. The actual position of the security bit memory location within PROM 15 should be concealed as well as possible to prevent defeat of the security feature by an unauthorized person.
The use of two separate memory locations for the security bit allows for the manufacturer to test the security features of the VLSI circuit. For example, FIG. 3 is a flowchart which describes a process for testing the security feature of a VLSI circuit by a device external to the VLSI circuit in accordance with a preferred embodiment of the present invention. During testing, IC logic circuitry 14 sets the test/program bit on line 30 to logic 1.
In a step 80, no security bit is selected by the address on security bit address lines 21. In a step 81, an attempt is made to access and program memory locations within memory array 50. In a step 82, the first security bit is selected and program memory locations are checked to see if any were programmed or accessed in step 81.
A step 83 is a branching step. If any memory locations were successfully programmed, in a step 89 the VLSI circuit is rejected. Otherwise, in a step 84, the first security bit location is selected by the address on security bit address lines 21. In a step 85, an attempt is made to access and program memory locations within the test row(s) and/or test column(s). In a step 86, the programmed memory locations are checked to see if they were successfully programmed in step 85.
A step 87 is a branching step. If any memory locations were not successfully programmed, in step 89 the VLSI circuit is rejected. Otherwise, in a step 88, the first security bit is programmed. In a step 90, the first security bit location is selected by the address on security bit address lines 21. In a step 91, an attempt is made to access and program memory locations within memory array 50. In a step 92, the second security bit is selected and program memory locations are checked to see if any were programmed or accessed in step 91.
A step 93 is a branching step. If any memory locations were successfully programmed, in step 89 the VLSI circuit is rejected. Otherwise, in a step 94, the second security bit location is selected by the address on security bit address lines 21. In a step 95, an attempt is made to access and program memory locations within memory array 50. In a step 96, program memory locations are checked to see if any were programmed or accessed in step 95.
A step 97 is a branching step. If any memory locations were not successfully programmed, in step 89 the VLSI circuit is rejected. Otherwise, in a step 98, after all other testing is complete, the VLSI circuit may be shipped to the customer.
FIG. 4 describes a process by which a customer programs and tests the shipped part. In a step 101, the customer selects the second security bit. In a step 102, the customer programs memory locations within memory array 50. In a step 103, the customer verifies the programmed data.
A step 104 is a branching step. If any memory locations were not successfully programmed, in a step 110, the VLSI circuit is rejected. Otherwise, in a step 105, the second security bit is programmed. In a step 106, the second security bit is selected. In a step 107, an attempt is made to access memory locations within memory array 50.
A step 108 is a branching step. If any memory locations were successfully accessed, in step 110, the VLSI circuit is rejected. Otherwise, in a step 109, the VLSI circuit is ready for further testing or to be utilized in a computing system.
The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

Claims (10)

We claim:
1. A security system for programmable read-only memory locations within a very large scale integrated (VLSI) circuit, the security system comprising:
a first security bit memory location in which is stored a first security data bit, the first security data bit having a first value when the first security bit memory location is unprogrammed and the first security data bit having a second value when the first security bit memory location is programmed;
a second security bit memory location in which is stored a second security data bit, the second security data bit having the first value when the second security bit memory location is unprogrammed and the second security data bit having the second value when the second security bit memory location is programmed;
selection means, electrically coupled to the first security bit memory location and the second security bit memory location, for selecting to provide a value for a security access signal, one of the first security data bit, the second security data bit or neither the first security data bit nor the second security data bit; and,
access means, coupled to the selection means, for allowing and preventing direct access, by any device outside the VLSI circuit, to the programmable read-only memory locations in response to the security access signal;
wherein the access means prevents any device outside the VLSI circuit direct access to the programmable read-only memory locations when the selection means selects neither the first security data bit nor the second security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
2. A security system as in claim 1
wherein the VLSI circuit includes input pins, output pins and additional logic circuitry, the additional logic circuitry having address lines and data lines and the additional logic circuit controlling operation of the VLSI circuit; and,
wherein the access means includes
a first multiplexor, coupled to the input pins and the address lines of the additional circuitry, the first multiplexor selecting between an address on the address lines of the additional logic circuitry and information on the input pins of the VLSI circuit to be connected to input address lines for the programmable read only memory locations, and
a second multiplexor, coupled to the output pins, the programmable read-only memory locations and the data lines for the additional logic circuitry, the second multiplexor selecting between the data lines for the additional logic circuitry and data from the programmable read only memory locations to be placed on the output pins of the VLSI circuit.
3. A security system as in claim 2 wherein the additional logic circuitry generates a test bit and wherein the access means includes means, coupled to the additional logic circuitry, for preventing any device outside the VLSI circuit from having direct access to the programmable read-only memory locations when the test bit has a first test bit value.
4. A security system as in claim 1 wherein the programmable read-only memory locations are arranged in a memory array within a programmable read-only memory (PROM), the PROM additionally including an address decoder, coupled to the programmable read-only memory locations, and wherein the programmable read-only memory locations include programmable read only memory locations which form a test row, a test column, the first security bit memory location and the second security bit memory location.
5. A security system as in claim 1 wherein the VLSI circuit additionally includes
program logic, coupled to the programmable read-only memory locations, for providing a programming voltage to the programmable read-only memory locations, the program logic including
enable/disable means, coupled to the selection means, for preventing the program logic from programming the programmable read-only memory locations when the selection means selects neither the first security data bit nor the second security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
6. A method for providing security for programmable read-only memory locations within a VLSI circuit, the VLSI circuit including a first security bit and a second security bit, wherein providing security for programmable read-only memory locations includes verification of correct operation of security features, the method comprising the steps of:
(a) preventing, by the VLSI circuit, a device outside the VLSI circuit from accessing the programmable read-only memory locations except when the first security bit is selected and unprogrammed or when the second security bit is selected and unprogrammed;
(b) programming test memory locations within the VLSI circuit;
(c) programming the first security bit to a first value;
(d) selecting the first security bit; and
(e) while the first security bit is selected, verifying that no device outside the VLSI circuit can access the programmable read-only memory locations.
7. A method as in claim 6 additionally comprising the steps of:
(f) selecting the second security bit;
(g) programming the programmable read-only memory locations; and,
(h) programming the second security bit to the first value.
8. A method for providing security for programmable read-only memory locations within a VLSI circuit, the method comprising the steps of:
(a) providing within the VLSI circuit a first security bit memory location in which is stored a first security data bit, the first security data bit having a first value when the first security bit memory location is unprogrammed and the first security data bit having a second value when the first security bit memory location is programmed;
(b) providing within the VLSI circuit a second security bit memory location in which is stored a second security data bit, the second security data bit having the first value when the second security bit memory location is unprogrammed and the second security data bit having the second value when the second security bit memory location is programmed; and,
(c) preventing, by the VLSI circuit, any device outside the VLSI circuit from directly accessing the programmable read-only memory locations when a selection means selects neither the first security data bit nor the second security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
9. A method as in claim 8 additionally comprising the step of:
(d) preventing, by the VLSI circuit, any device outside the VLSI circuit from directly accessing the programmable read-only memory locations when a test bit, within the VLSI circuit, has a first test bit value.
10. A method as in claim 8 additionally comprising the step of:
(d) preventing a programming voltage from being provided to the programmable read-only memory locations when the selection means selects no security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
US07/965,635 1992-10-23 1992-10-23 Verifiable security circuitry for preventing unauthorized access to programmed read only memory Expired - Lifetime US5465341A (en)

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US07/965,635 US5465341A (en) 1992-10-23 1992-10-23 Verifiable security circuitry for preventing unauthorized access to programmed read only memory
DE69303827T DE69303827T2 (en) 1992-10-23 1993-10-25 REVISABLE SECURITY CIRCUIT TO PREVENT UNAUTHORIZED ACCESS TO A PROM
PCT/US1993/010189 WO1994010687A1 (en) 1992-10-23 1993-10-25 Verifiable security circuitry for preventing unauthorized access to programmed read only memory
JP6511219A JPH08503093A (en) 1992-10-23 1993-10-25 Verifiable security circuitry to prevent unauthorized access to programmable read-only memory
EP93925027A EP0665979B1 (en) 1992-10-23 1993-10-25 Verifiable security circuitry for preventing unauthorized access to programmed read only memory

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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5642480A (en) * 1995-09-28 1997-06-24 Motorola, Inc. Method and apparatus for enhanced security of a data processor
US5657444A (en) * 1995-08-03 1997-08-12 National Semiconductor Corporation Microprocessor with secure programmable read only memory circuit
US5745676A (en) * 1995-12-04 1998-04-28 International Business Machines Corporation Authority reduction and restoration method providing system integrity for subspace groups and single address spaces during program linkage
US5748940A (en) * 1995-08-17 1998-05-05 Compaq Computer Corporation Secure updating of non-volatile memory
US5923841A (en) * 1995-10-18 1999-07-13 Samsung Electronics Co., Ltd. Computer system having security functions and a security method
US5960172A (en) * 1995-12-30 1999-09-28 Samsung Electronics Co., Ltd. Digital computer system security device
US6002609A (en) * 1997-07-09 1999-12-14 Kabushiki Kaisha Toshiba Semiconductor device having a security circuit for preventing illegal access
US6035368A (en) * 1996-11-15 2000-03-07 U.S. Philips Corporation Protection method against eeprom-directed intrusion into a mobile communication device that has a processor, and a device having such protection mechanism
US6049876A (en) * 1998-02-09 2000-04-11 Motorola, Inc. Data processing system and method which detect unauthorized memory accesses
US6339815B1 (en) * 1998-08-14 2002-01-15 Silicon Storage Technology, Inc. Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space
WO2002011289A1 (en) * 2000-07-28 2002-02-07 Atmel Corporation Secure programmable logic device
US6523099B1 (en) 1998-03-19 2003-02-18 Sony Corporation Integrated circuit with output inhibit feature and a control port to receive an inhibit release password
KR20040078418A (en) * 2003-03-04 2004-09-10 주식회사 하이닉스반도체 One time programable(OTP) memory device
US7076667B1 (en) * 1999-07-09 2006-07-11 Fujitsu Limited Storage device having secure test process
US20080089160A1 (en) * 2006-10-11 2008-04-17 Elpida Memory, Inc. Semiconductor device
US20090292903A1 (en) * 2008-05-24 2009-11-26 Via Technologies, Inc Microprocessor providing isolated timers and counters for execution of secure code
US8819839B2 (en) 2008-05-24 2014-08-26 Via Technologies, Inc. Microprocessor having a secure execution mode with provisions for monitoring, indicating, and managing security levels
US20180204613A1 (en) * 2013-07-25 2018-07-19 Renesas Electronics Corporation Semiconductor integrated circuit device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7810152B2 (en) 2002-05-08 2010-10-05 Broadcom Corporation System and method for securely controlling access to device functions
US7681043B1 (en) 2002-05-08 2010-03-16 Broadcom Corporation System and method for configuring device features via programmable memory
US6711684B1 (en) * 1999-06-08 2004-03-23 General Instrument Corporation Variable security code download for an embedded processor
JP2005032020A (en) 2003-07-07 2005-02-03 Matsushita Electric Ind Co Ltd Storage device

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4480318A (en) * 1982-02-18 1984-10-30 Fairchild Camera & Instrument Corp. Method of programming of junction-programmable read-only memories
US4503387A (en) * 1982-12-30 1985-03-05 Harris Corporation A.C. Testing of logic arrays
US4590552A (en) * 1982-06-30 1986-05-20 Texas Instruments Incorporated Security bit for designating the security status of information stored in a nonvolatile memory
EP0231041A1 (en) * 1986-01-20 1987-08-05 Koninklijke Philips Electronics N.V. Non-volatile, programmable semiconductor memory
US4719599A (en) * 1983-10-31 1988-01-12 Nec Corporation Programmable read-only memory device provided with test cells
US4731760A (en) * 1986-05-05 1988-03-15 Motorola, Inc. On-chip test circuitry for an ECL PROM
EP0378306A2 (en) * 1989-01-12 1990-07-18 General Instrument Corporation Of Delaware Secure integrated circuit chip with conductive field
US4972372A (en) * 1987-07-21 1990-11-20 Fujitsu Limited Programmable device and method of testing programmable device
US4974208A (en) * 1985-04-23 1990-11-27 Hitachi, Ltd. Microcomputer incorporating a nonvolatile semiconductor memory
US5175840A (en) * 1985-10-02 1992-12-29 Hitachi, Ltd. Microcomputer having a PROM including data security and test circuitry
US5293610A (en) * 1989-08-04 1994-03-08 Motorola, Inc. Memory system having two-level security system for enhanced protection against unauthorized access
US5315553A (en) * 1991-06-10 1994-05-24 Texas Instruments Incorporated Memory circuit test system using separate ROM having test values stored therein

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4480318A (en) * 1982-02-18 1984-10-30 Fairchild Camera & Instrument Corp. Method of programming of junction-programmable read-only memories
US4590552A (en) * 1982-06-30 1986-05-20 Texas Instruments Incorporated Security bit for designating the security status of information stored in a nonvolatile memory
US4503387A (en) * 1982-12-30 1985-03-05 Harris Corporation A.C. Testing of logic arrays
US4719599A (en) * 1983-10-31 1988-01-12 Nec Corporation Programmable read-only memory device provided with test cells
US4974208A (en) * 1985-04-23 1990-11-27 Hitachi, Ltd. Microcomputer incorporating a nonvolatile semiconductor memory
US5175840A (en) * 1985-10-02 1992-12-29 Hitachi, Ltd. Microcomputer having a PROM including data security and test circuitry
EP0231041A1 (en) * 1986-01-20 1987-08-05 Koninklijke Philips Electronics N.V. Non-volatile, programmable semiconductor memory
US4731760A (en) * 1986-05-05 1988-03-15 Motorola, Inc. On-chip test circuitry for an ECL PROM
US4972372A (en) * 1987-07-21 1990-11-20 Fujitsu Limited Programmable device and method of testing programmable device
EP0378306A2 (en) * 1989-01-12 1990-07-18 General Instrument Corporation Of Delaware Secure integrated circuit chip with conductive field
US5293610A (en) * 1989-08-04 1994-03-08 Motorola, Inc. Memory system having two-level security system for enhanced protection against unauthorized access
US5315553A (en) * 1991-06-10 1994-05-24 Texas Instruments Incorporated Memory circuit test system using separate ROM having test values stored therein

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
L. Phillipson, et al., A Communication Structure for a Multiprocessor Computer with Distributed Global Memory, Proc. 10th Annual Intl. Conf. on Computer Architecture , 1983, Stockholm, SE, pp. 334 339. *
L. Phillipson, et al., A Communication Structure for a Multiprocessor Computer with Distributed Global Memory, Proc. 10th Annual Intl. Conf. on Computer Architecture, 1983, Stockholm, SE, pp. 334-339.

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5657444A (en) * 1995-08-03 1997-08-12 National Semiconductor Corporation Microprocessor with secure programmable read only memory circuit
US6085299A (en) * 1995-08-17 2000-07-04 Compaq Computer Corporation Secure updating of non-volatile memory
US5748940A (en) * 1995-08-17 1998-05-05 Compaq Computer Corporation Secure updating of non-volatile memory
US5642480A (en) * 1995-09-28 1997-06-24 Motorola, Inc. Method and apparatus for enhanced security of a data processor
US5923841A (en) * 1995-10-18 1999-07-13 Samsung Electronics Co., Ltd. Computer system having security functions and a security method
US5745676A (en) * 1995-12-04 1998-04-28 International Business Machines Corporation Authority reduction and restoration method providing system integrity for subspace groups and single address spaces during program linkage
US5960172A (en) * 1995-12-30 1999-09-28 Samsung Electronics Co., Ltd. Digital computer system security device
US6035368A (en) * 1996-11-15 2000-03-07 U.S. Philips Corporation Protection method against eeprom-directed intrusion into a mobile communication device that has a processor, and a device having such protection mechanism
US6002609A (en) * 1997-07-09 1999-12-14 Kabushiki Kaisha Toshiba Semiconductor device having a security circuit for preventing illegal access
US6049876A (en) * 1998-02-09 2000-04-11 Motorola, Inc. Data processing system and method which detect unauthorized memory accesses
US6523099B1 (en) 1998-03-19 2003-02-18 Sony Corporation Integrated circuit with output inhibit feature and a control port to receive an inhibit release password
US6339815B1 (en) * 1998-08-14 2002-01-15 Silicon Storage Technology, Inc. Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space
US7076667B1 (en) * 1999-07-09 2006-07-11 Fujitsu Limited Storage device having secure test process
WO2002011289A1 (en) * 2000-07-28 2002-02-07 Atmel Corporation Secure programmable logic device
KR20040078418A (en) * 2003-03-04 2004-09-10 주식회사 하이닉스반도체 One time programable(OTP) memory device
US20080089160A1 (en) * 2006-10-11 2008-04-17 Elpida Memory, Inc. Semiconductor device
US7796456B2 (en) * 2006-10-11 2010-09-14 Elpida Memory, Inc. Semiconductor device
US20090292903A1 (en) * 2008-05-24 2009-11-26 Via Technologies, Inc Microprocessor providing isolated timers and counters for execution of secure code
US8793803B2 (en) 2008-05-24 2014-07-29 Via Technologies, Inc. Termination of secure execution mode in a microprocessor providing for execution of secure code
US20090292929A1 (en) * 2008-05-24 2009-11-26 Via Technologies, Inc Initialization of a microprocessor providing for execution of secure code
US20090293132A1 (en) * 2008-05-24 2009-11-26 Via Technologies, Inc Microprocessor apparatus for secure on-die real-time clock
US8370641B2 (en) 2008-05-24 2013-02-05 Via Technologies, Inc. Initialization of a microprocessor providing for execution of secure code
US8522354B2 (en) * 2008-05-24 2013-08-27 Via Technologies, Inc. Microprocessor apparatus for secure on-die real-time clock
US8607034B2 (en) 2008-05-24 2013-12-10 Via Technologies, Inc. Apparatus and method for disabling a microprocessor that provides for a secure execution mode
US8615799B2 (en) 2008-05-24 2013-12-24 Via Technologies, Inc. Microprocessor having secure non-volatile storage access
US8762687B2 (en) 2008-05-24 2014-06-24 Via Technologies, Inc. Microprocessor providing isolated timers and counters for execution of secure code
US20090292894A1 (en) * 2008-05-24 2009-11-26 Via Technologies, Inc Microprocessor having internal secure memory
US8819839B2 (en) 2008-05-24 2014-08-26 Via Technologies, Inc. Microprocessor having a secure execution mode with provisions for monitoring, indicating, and managing security levels
US8838924B2 (en) 2008-05-24 2014-09-16 Via Technologies, Inc. Microprocessor having internal secure memory
US8910276B2 (en) 2008-05-24 2014-12-09 Via Technologies, Inc. Apparatus and method for precluding execution of certain instructions in a secure execution mode microprocessor
US8978132B2 (en) 2008-05-24 2015-03-10 Via Technologies, Inc. Apparatus and method for managing a microprocessor providing for a secure execution mode
US9002014B2 (en) 2008-05-24 2015-04-07 Via Technologies, Inc. On-die cryptographic apparatus in a secure microprocessor
US20180204613A1 (en) * 2013-07-25 2018-07-19 Renesas Electronics Corporation Semiconductor integrated circuit device
US10304527B2 (en) * 2013-07-25 2019-05-28 Renesas Electronics Corporation Semiconductor integrated circuit device
US10580484B2 (en) 2013-07-25 2020-03-03 Renesas Electronics Corporation Semiconductor integrated circuit device

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WO1994010687A1 (en) 1994-05-11
DE69303827D1 (en) 1996-08-29
EP0665979B1 (en) 1996-07-24
DE69303827T2 (en) 1997-02-13
JPH08503093A (en) 1996-04-02

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