US5398245A - Packet processing method and apparatus - Google Patents

Packet processing method and apparatus Download PDF

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Publication number
US5398245A
US5398245A US07/771,769 US77176991A US5398245A US 5398245 A US5398245 A US 5398245A US 77176991 A US77176991 A US 77176991A US 5398245 A US5398245 A US 5398245A
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data packet
data
header
high speed
cache memory
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US07/771,769
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Edward S. Harriman, Jr.
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Avaya Holdings Ltd
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Bay Networks Inc
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Priority to US07/771,769 priority Critical patent/US5398245A/en
Application filed by Bay Networks Inc filed Critical Bay Networks Inc
Assigned to WELLFLEET COMMUNICATIONS, INC. reassignment WELLFLEET COMMUNICATIONS, INC. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: HARRIMAN, EDWARD S., JR.
Priority to DE69228758T priority patent/DE69228758T2/en
Priority to EP92921294A priority patent/EP0606368B1/en
Priority to AU27563/92A priority patent/AU2756392A/en
Priority to JP50693093A priority patent/JP3286320B2/en
Priority to PCT/US1992/007950 priority patent/WO1993007692A1/en
Publication of US5398245A publication Critical patent/US5398245A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9042—Separate storage for different parts of the packet, e.g. header and payload
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers

Definitions

  • the invention relates generally to a method and apparatus for data communications; and more particularly, to a method and apparatus for processing and transferring data packets in a bridge or router circuit.
  • a potential bottleneck occurs when data packets need to be transmitted between two networks, for example, using a bridge or router circuitry.
  • the circuitry must be fast enough not only to simply forward the data packet, but in addition to process the data packet headers so that a new header, identifying, for example, the next routing destination, can be generated and prepended to the packet data.
  • the resulting "strain" on a bridge or router CPU, and the controlling software can be substantial.
  • the data packet is typically stored in DRAM memory, the constant accesses to the stored packet by the CPU for certain required information can prove to be a bottleneck in the system.
  • One obvious solution to the bottleneck issue is to store the entire data packet in high speed static memory. This poses significant cost problems since high speed static memory is relatively expensive; and accordingly, a large capacity memory, able to store many data packets, becomes the major cost expense for a product.
  • the invention thus relates to a method and apparatus for processing a data packet for delivery to a designated location, the packet having a selected protocol wherein a header of the packet includes at least one of destination identification data, protocol data, and source identification data.
  • the method of the invention features the steps of receiving successive packets from a data source channel, storing at least a portion of the header of each packet in a high speed data cache, storing at least the remainder of each data packet (and preferably the entire data packet) in a slower speed memory, accessing each header portion of each packet in the high speed data cache for protocol and the destination processing of the data packet, and forwarding a newly generated data packet to a next packet destination.
  • the method further features the steps of storing each header portion of the data packet at an address which is identified by the location in the slower memory of the remainder of the associated data packet.
  • the apparatus of the invention features circuitry for receiving successive packets from the data source channel, a high speed data cache and a slower speed memory, circuitry for storing at least a header portion of each packet in the high speed data cache and for storing at least the remainder (and preferably all) of each packet in the slower speed mass memory, circuitry for accessing each header portion of each packet in the data cache for protocol and destination processing of the data packet, and circuitry for forwarding a generated new data packet to a next packet destination.
  • the apparatus further features circuitry for storing each header portion of a data packet at an address which is identified by the location in slow memory of the remaining portion of the associated data packet.
  • FIG. 1 is a block diagram of a system for delivering packets between nodes in a network
  • FIG. 2 is a more detailed block diagram of a router or bridge circuit for the apparatus illustrated in FIG. 1;
  • FIG. 3 illustrates in a more detail, the portion of the router or bridge to which the invention is directed.
  • a data packet networking system 10 includes a plurality of nodes A 1 , A 1 , . . . A x , D 1 , D 2 , . . . , D z which are interconnected with each other through routing or bridge circuitries B 1 , C 1 , C 2 , . . . C y .
  • the routing and bridge circuitries receive data from the nodes and transfer that data either to other nodes or to other bridges and routers on the way to a final destination node.
  • the bridge and routing circuitry are programmed with the configuration of the network and accordingly know the available paths for forwarding data to the final destination.
  • a router or bridge circuitry 12 receives data over a channel receiver 14.
  • the channel receiver operates to store the data packet in a storage memory 16 while at the same time advising a controller 18 of the arrival of the packet.
  • the controller can receive, for example, the entire data packet to determine its structure.
  • the structure typically includes a header at the beginning of the data packet, the data itself, and an error check (typically a CRC error check) at the end of the data packet by which the receiver can check the integrity of the data which is being received.
  • the controller after examining the header, can also determine the protocol being used, if more than one protocol is available over the input channel, and the eventual destination and source node for the data packet.
  • the CPU operates to generate a new header for the data, appends the new header to the remaining portion of the data packet and directs the now reconstructed header and data combination out over a channel transmitter 20 onto another network for transmission to the final node or to the next router/bridge along its path.
  • An error check word is calculated in the transmitter and is appended to the end of the data packet.
  • the present invention is directed to a more efficient method and apparatus for handling the data packet processing in the router/bridge circuit.
  • the router includes a slower memory circuitry 26, a high speed cache memory 28, the CPU controller 18, address translation and control circuitries 30 and 32, and controllable driver circuitries 34, 36, 38, 40, 42, 44, 46, and 48. All of the drivers are unidirectional except for the bidirectional driver circuitry 48.
  • CPU 18, address and control circuitry 32, and drivers 42, 44, 46, and 48 form a processing element 50, which connects to the input/output address and bus lines 52 and 54 respectively and to the data cache 28. It is expected that in a preferred embodiment of the invention, there can be a plurality of processing elements; and that each of the processing elements 50 can operate upon a different data packet, in parallel, with the data cache 28 being fast enough to service, simultaneously, all of the processing elements 50.
  • the address translation and control circuits 30, 32 are preset by the CPU 18 to recognize, using the lower order bits on the address line, the bytes of information in the packet which are to be stored, according to the protocol used, in the cache memory 28.
  • the stored bytes need not be adjacent to each other in the packet, but will all belong to the packet header, in the illustrated embodiment.
  • Address and control circuit 30, during packet reception receives address data from link interfaces 60 over address bus lines 52.
  • the address data is also provided to the slower memory 26.
  • the address is translated using a stored memory array table in a random access memory of the address translation circuitry 30 and a corresponding cache line select address, based upon a high order portion of the address is output over lines 62 to the multiported cache memory 28.
  • the data drivers 36 are selectively enabled, depending upon the low order portion of the address (as described below), and cause that portion of the incoming data packet which is to be stored in cache to be loaded into the cache memory at the line address specified over lines 62.
  • the entire data packet in the illustrated embodiment, is also stored in buffer memory 26 through drivers 40 at an address corresponding to the address available over the input/output lines 52.
  • the data packet information is available over lines 54 and the packet is stored in its entirety in buffer memory 26.
  • Buffer memory 26 also includes sufficient control circuitry at 26a for decoding the address information over lines 52 and receiving and storing the entire data packet in a buffer assigned to the most significant bits of that data address.
  • the information stored in cache memory 28 includes at least an identification of the source and destination of the data packet, the protocol being used if the protocol is not already known to the bridge/router circuitry, and/or other required header information which will be needed to enable the processor 50 to generate a new header and pass the data packet on to the next receiving node of the network.
  • the entire data packet is stored in buffer memory 26, typically a dynamic RAM (DRAM), while selected header data (that which is typically used by the CPU), is stored in fast cache memory 28 and is made available to the CPU as required as follows.
  • the header data is selected using the translate and control circuitry 30 and need not be contiguous in the header. That circuitry, at turn-on, is initialized by the CPU to recognize by the low order bits of the address data, those bytes of the header which are to be "cached". Those bytes need not be contiguous in the data packet.
  • circuitry 30 Upon recognition of an address corresponding to header data to be stored, circuitry 30 asserts the "hit" line 63 and places the correct address on data input lines 62. The data is then read by, and stored in, cache 28.
  • any of the processors 50 can access cache 28 to recover the header information contained therein.
  • the processor 50 through its CPU 18, requests data over lines 70 using an address which corresponds to the address on input/output address lines 52.
  • the address translation circuit 32 like address translation circuit 30, translates that address into a cache select line address over lines 65. If the address is valid and corresponds to data stored in cache, the data drivers 44 or 46 are activated by the "hit" signal over a line 72 and the CPU either reads data from the cache memory for processing or writes data into the cache memory for use as part of a new header for the data packet. Note that if there is no "hit" and the header data is not available in cache, then the CPU will either read the data from buffer memory 26 or write data to buffer memory 26 through data drivers 48 and address drivers 42.
  • the data cache 28, as seen above, is a multiple port memory.
  • the cache is a true multi-port memory; that is, simultaneous reads and/or writes are serviced in parallel, thereby eliminating any performance degradation.
  • true N-port memories or multiplexed port memories can be used.
  • multiple caches which are really just a specific implementation of a single large cache can also be implemented.
  • the cache 28 services each of the demands placed upon it, that is, from address translation circuitry 30, or from one of the address translation circuits 32 of a processing element 50. If cache 28 is a multiplexed implementation, and is servicing one of those processing elements 50, any other request is stayed until the earlier, and on-going, request has been serviced. Thereafter, the multiplexed cache memory 28 will service the next received request.
  • the CPU controller causes the header information to be written, typically to cache memory, ("hit" is asserted) through drivers 44, and can also, and alternatively, cause previously written header information to be read from cache memory, through drivers 42, to the CPU.
  • header data can be read from cache memory, through drivers 46 and 48 for access to the data bus 54.
  • the buffer memory 26 also under CPU control, can provide the remainder of data from its memory, over the data output lines, through connected driver 38.
  • the CPU adds, through driver 48, the error check bits so that the receiving node(s) for this packet will have all of the information necessary to check the integrity of the incoming data.
  • the buffer layout and therefore the header address, is known to the system and allows the address translation circuitry to be fixed at installation time.
  • the buffer layout also allows all sides of the packet header cache to run independently and enables the cache to anticipate the CPU requirements rather than responding thereto.
  • the use of a multiport memory for cache 28 eliminates bus arbitration overhead and enables, with the use of the address translation circuitry, the use of commercial multiport memories and comparison logic.

Abstract

A method and apparatus for processing a data packet, for delivery to a designated location, store selective portions of the packet header in a high speed cache memory to increase processing speed and hence throughput for a packet delivery system. The apparatus and method receive the packets from a data channel source and store portions of the header in cache, and at least the remainder of each data packet is stored in a slower speed memory. A CPU accesses the stored header portion of each packet in cache for necessary protocol and destination information processing of the data packet. The header portions are then overwritten with new data and combined with the remainder of the data packet stored in slower speed memory for transmission to the next packet destination. Preferably, the address at which the remainder portions are stored in slower speed memory determine the cache addresses at which the header portion is stored in high speed cache memory.

Description

BACKGROUND OF THE INVENTION
The invention relates generally to a method and apparatus for data communications; and more particularly, to a method and apparatus for processing and transferring data packets in a bridge or router circuit.
As networks have increased substantially in throughput during the recent few years, so that a standard FDDI network now operates at one hundred megabits per second, a potential bottleneck occurs when data packets need to be transmitted between two networks, for example, using a bridge or router circuitry. The circuitry must be fast enough not only to simply forward the data packet, but in addition to process the data packet headers so that a new header, identifying, for example, the next routing destination, can be generated and prepended to the packet data. The resulting "strain" on a bridge or router CPU, and the controlling software, can be substantial. In particular, since the data packet is typically stored in DRAM memory, the constant accesses to the stored packet by the CPU for certain required information can prove to be a bottleneck in the system. One obvious solution to the bottleneck issue is to store the entire data packet in high speed static memory. This poses significant cost problems since high speed static memory is relatively expensive; and accordingly, a large capacity memory, able to store many data packets, becomes the major cost expense for a product.
It is therefore an object of the invention to increase the throughput processing of data packets without incurring substantially increased memory costs, while maintaining high system reliability. Another object of the invention is high speed access to the data packet information.
SUMMARY OF THE INVENTION
The invention thus relates to a method and apparatus for processing a data packet for delivery to a designated location, the packet having a selected protocol wherein a header of the packet includes at least one of destination identification data, protocol data, and source identification data. The method of the invention features the steps of receiving successive packets from a data source channel, storing at least a portion of the header of each packet in a high speed data cache, storing at least the remainder of each data packet (and preferably the entire data packet) in a slower speed memory, accessing each header portion of each packet in the high speed data cache for protocol and the destination processing of the data packet, and forwarding a newly generated data packet to a next packet destination.
The method further features the steps of storing each header portion of the data packet at an address which is identified by the location in the slower memory of the remainder of the associated data packet.
The apparatus of the invention features circuitry for receiving successive packets from the data source channel, a high speed data cache and a slower speed memory, circuitry for storing at least a header portion of each packet in the high speed data cache and for storing at least the remainder (and preferably all) of each packet in the slower speed mass memory, circuitry for accessing each header portion of each packet in the data cache for protocol and destination processing of the data packet, and circuitry for forwarding a generated new data packet to a next packet destination.
The apparatus further features circuitry for storing each header portion of a data packet at an address which is identified by the location in slow memory of the remaining portion of the associated data packet.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, features, and advantages of the invention will be apparent from the following description taken together with the drawings in which:
FIG. 1 is a block diagram of a system for delivering packets between nodes in a network;
FIG. 2 is a more detailed block diagram of a router or bridge circuit for the apparatus illustrated in FIG. 1; and
FIG. 3 illustrates in a more detail, the portion of the router or bridge to which the invention is directed.
DESCRIPTION OF A PREFERRED EMBODIMENT
Referring to FIG. 1, a data packet networking system 10 includes a plurality of nodes A1, A1, . . . Ax, D1, D2, . . . , Dz which are interconnected with each other through routing or bridge circuitries B1, C1, C2, . . . Cy. The routing and bridge circuitries receive data from the nodes and transfer that data either to other nodes or to other bridges and routers on the way to a final destination node. In typical operation, the bridge and routing circuitry are programmed with the configuration of the network and accordingly know the available paths for forwarding data to the final destination.
In typical operation, referring to FIG. 2, a router or bridge circuitry 12 receives data over a channel receiver 14. The channel receiver operates to store the data packet in a storage memory 16 while at the same time advising a controller 18 of the arrival of the packet. The controller can receive, for example, the entire data packet to determine its structure. The structure typically includes a header at the beginning of the data packet, the data itself, and an error check (typically a CRC error check) at the end of the data packet by which the receiver can check the integrity of the data which is being received. The controller, after examining the header, can also determine the protocol being used, if more than one protocol is available over the input channel, and the eventual destination and source node for the data packet. The CPU operates to generate a new header for the data, appends the new header to the remaining portion of the data packet and directs the now reconstructed header and data combination out over a channel transmitter 20 onto another network for transmission to the final node or to the next router/bridge along its path. An error check word is calculated in the transmitter and is appended to the end of the data packet.
The present invention is directed to a more efficient method and apparatus for handling the data packet processing in the router/bridge circuit. Referring to FIG. 3, in accordance with the illustrated embodiment of the invention, the router includes a slower memory circuitry 26, a high speed cache memory 28, the CPU controller 18, address translation and control circuitries 30 and 32, and controllable driver circuitries 34, 36, 38, 40, 42, 44, 46, and 48. All of the drivers are unidirectional except for the bidirectional driver circuitry 48.
CPU 18, address and control circuitry 32, and drivers 42, 44, 46, and 48 form a processing element 50, which connects to the input/output address and bus lines 52 and 54 respectively and to the data cache 28. It is expected that in a preferred embodiment of the invention, there can be a plurality of processing elements; and that each of the processing elements 50 can operate upon a different data packet, in parallel, with the data cache 28 being fast enough to service, simultaneously, all of the processing elements 50.
In operation, the address translation and control circuits 30, 32 are preset by the CPU 18 to recognize, using the lower order bits on the address line, the bytes of information in the packet which are to be stored, according to the protocol used, in the cache memory 28. The stored bytes need not be adjacent to each other in the packet, but will all belong to the packet header, in the illustrated embodiment. Address and control circuit 30, during packet reception, receives address data from link interfaces 60 over address bus lines 52. The address data is also provided to the slower memory 26. The address is translated using a stored memory array table in a random access memory of the address translation circuitry 30 and a corresponding cache line select address, based upon a high order portion of the address is output over lines 62 to the multiported cache memory 28. Correspondingly, the data drivers 36 are selectively enabled, depending upon the low order portion of the address (as described below), and cause that portion of the incoming data packet which is to be stored in cache to be loaded into the cache memory at the line address specified over lines 62.
Simultaneously, the entire data packet, in the illustrated embodiment, is also stored in buffer memory 26 through drivers 40 at an address corresponding to the address available over the input/output lines 52. The data packet information is available over lines 54 and the packet is stored in its entirety in buffer memory 26. Buffer memory 26 also includes sufficient control circuitry at 26a for decoding the address information over lines 52 and receiving and storing the entire data packet in a buffer assigned to the most significant bits of that data address. The information stored in cache memory 28 includes at least an identification of the source and destination of the data packet, the protocol being used if the protocol is not already known to the bridge/router circuitry, and/or other required header information which will be needed to enable the processor 50 to generate a new header and pass the data packet on to the next receiving node of the network.
Thus, when the data packet is first received, the entire data packet is stored in buffer memory 26, typically a dynamic RAM (DRAM), while selected header data (that which is typically used by the CPU), is stored in fast cache memory 28 and is made available to the CPU as required as follows. The header data is selected using the translate and control circuitry 30 and need not be contiguous in the header. That circuitry, at turn-on, is initialized by the CPU to recognize by the low order bits of the address data, those bytes of the header which are to be "cached". Those bytes need not be contiguous in the data packet. Upon recognition of an address corresponding to header data to be stored, circuitry 30 asserts the "hit" line 63 and places the correct address on data input lines 62. The data is then read by, and stored in, cache 28.
Once the data packet has been received and is properly in both the buffer memory 26 and cache memory 28, any of the processors 50 can access cache 28 to recover the header information contained therein. Thus, the processor 50, through its CPU 18, requests data over lines 70 using an address which corresponds to the address on input/output address lines 52. The address translation circuit 32, like address translation circuit 30, translates that address into a cache select line address over lines 65. If the address is valid and corresponds to data stored in cache, the data drivers 44 or 46 are activated by the "hit" signal over a line 72 and the CPU either reads data from the cache memory for processing or writes data into the cache memory for use as part of a new header for the data packet. Note that if there is no "hit" and the header data is not available in cache, then the CPU will either read the data from buffer memory 26 or write data to buffer memory 26 through data drivers 48 and address drivers 42.
The data cache 28, as seen above, is a multiple port memory. In the preferred embodiment of the invention, the cache is a true multi-port memory; that is, simultaneous reads and/or writes are serviced in parallel, thereby eliminating any performance degradation. In other implementations of the data cache, true N-port memories or multiplexed port memories can be used. Further, multiple caches which are really just a specific implementation of a single large cache can also be implemented. In all of these embodiments, the cache 28 services each of the demands placed upon it, that is, from address translation circuitry 30, or from one of the address translation circuits 32 of a processing element 50. If cache 28 is a multiplexed implementation, and is servicing one of those processing elements 50, any other request is stayed until the earlier, and on-going, request has been serviced. Thereafter, the multiplexed cache memory 28 will service the next received request.
Thus, in operation, the CPU controller causes the header information to be written, typically to cache memory, ("hit" is asserted) through drivers 44, and can also, and alternatively, cause previously written header information to be read from cache memory, through drivers 42, to the CPU. Further, under CPU control, header data can be read from cache memory, through drivers 46 and 48 for access to the data bus 54. The buffer memory 26 also under CPU control, can provide the remainder of data from its memory, over the data output lines, through connected driver 38. At the end of the data packet, the CPU adds, through driver 48, the error check bits so that the receiving node(s) for this packet will have all of the information necessary to check the integrity of the incoming data.
In accordance with the preferred embodiment of the invention, the buffer layout, and therefore the header address, is known to the system and allows the address translation circuitry to be fixed at installation time. The buffer layout also allows all sides of the packet header cache to run independently and enables the cache to anticipate the CPU requirements rather than responding thereto. Further, the use of a multiport memory for cache 28 eliminates bus arbitration overhead and enables, with the use of the address translation circuitry, the use of commercial multiport memories and comparison logic.
Additions, subtractions, and other modifications of the described embodiment will be apparent to those of ordinary skill of the art and are within the scope of the following claims.

Claims (14)

What is claimed is:
1. A method for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein said header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising the steps of
receiving successive data packets from a data source channel,
storing at least a portion of said header of each data packet in a high speed data cache memory,
storing at least said remainder portion of said each data packet in a slower speed memory,
accessing each header of said each data packet in said high speed data cache memory for protocol and destination processing of said each data packet, and
forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of said each data packet.
2. The method of claim 1 further comprising the step of
storing said header of said each data packet at an address identifying the location in said slower speed memory of said remainder portion of said each data packet.
3. The method of claim 1 further comprising the step of
identifying, from an address in said slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored.
4. The method of claim 1 further comprising the steps of
providing plural port access to said high speed data cache memory from at least an input/output data bus and a CPU based processor,
reading said stored header directly from said high speed data cache memory by said processor, and
writing to said high speed data cache memory from said processor for modifying said header.
5. The method of claim 1 further comprising the step of
storing non-adjacent portions of said header in said high speed data cache memory.
6. The method of claim 1 further comprising the step of
selecting portions of said header for storage in said high speed data cache memory depending upon the address in said slower speed memory into which said remainder portion is stored.
7. A method for processing a data packet for delivery to a designated destination, said data packet having a selected protocol and including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising the steps of
receiving successive data packets from a data source channel,
storing non-contiguous portions of the header of each data packet in a high speed data cache memory,
storing at least said remainder portion of said each data packet in a slower speed memory,
selecting portions of said header of said each data packet for storage in said high speed data cache memory depending upon the address in the slower speed memory into which an associated remainder portion is stored,
identifying, from an address in the slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which the selected portion corresponding to said associated remainder portion is stored,
accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said each data packet, said accessing step comprising
providing plural port access to said high speed data cache memory from at least an input/output data bus and a CPU based processor,
reading said stored header directly from said high speed data cache memory by said processor, and
writing to said high speed data cache memory from said processor for modifying said header, and
forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of the data packet.
8. An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising
means for receiving successive data packets from a data source channel,
a high speed data cache memory,
a slower speed memory,
means for storing at least a portion of said header of each data packet in said high speed data cache memory,
means for storing at least said remainder portion of said each data packet in said slower speed memory,
means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of the data packet, and
means for forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of said data packet.
9. The apparatus of claim 8 further comprising
means for storing each said header portion of a data packet at an address identifying the location in said slower speed memory of the remainder portion of the associated data packet.
10. The apparatus of claim 8 further comprising
means for identifying from an address in said slower speed memory at which each said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored.
11. The apparatus of claim 8 further comprising
means for providing plural port access to said high speed data cache memory from input/output data bus and a CPU based processor,
means for reading said stored header directly from said high speed data cache memory by said processor, and
means for writing to said high speed data cache memory from said processor for modifying said header.
12. The apparatus of claim 8 further comprising
means for storing non-adjacent portions of said header in said high speed data cache memory.
13. The apparatus of claim 8 further comprising
means for selecting portions of said header for storage in said high speed data cache memory depending upon the address in slow memory into which said remainder portion is stored.
14. An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising
means for receiving successive data packets from a data source channel,
a multi-port high speed data cache memory,
means for connecting said high speed data cache memory to an input/output data bus and a CPU based processor,
a slower speed memory,
means for storing non-contiguous portions of said header of each data packet in said high speed data cache memory,
means for storing at least said remainder portion of said each data packet in said slower speed memory,
means for selecting portions of said header for storage in said high speed data cache memory depending upon the address in said slower speed memory into which said remainder portion is stored,
means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said data packet, said accessing means having
means for identifying from an address in said slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored,
means for reading said stored header directly from said high speed data cache memory by said processor, and
means for writing to said high speed data cache memory from said processor for modifying said header, and
means for forwarding a new data packet to a next data packet destination based on the protocol and destination processing of said data packet.
US07/771,769 1991-10-04 1991-10-04 Packet processing method and apparatus Expired - Lifetime US5398245A (en)

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PCT/US1992/007950 WO1993007692A1 (en) 1991-10-04 1992-09-22 Packet processing method and apparatus
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EP92921294A EP0606368B1 (en) 1991-10-04 1992-09-22 Packet processing method and apparatus
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Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0742677A2 (en) * 1995-05-08 1996-11-13 Fujitsu Limited Header converting method
US5634005A (en) * 1992-11-09 1997-05-27 Kabushiki Kaisha Toshiba System for automatically sending mail message by storing rule according to the language specification of the message including processing condition and processing content
US5752078A (en) * 1995-07-10 1998-05-12 International Business Machines Corporation System for minimizing latency data reception and handling data packet error if detected while transferring data packet from adapter memory to host memory
US5768515A (en) * 1996-07-08 1998-06-16 Microsoft Corporation Method for generating and storing two segments of HTTP message headers with different lifetimes and combining them to form a single response header
US5778414A (en) * 1996-06-13 1998-07-07 Racal-Datacom, Inc. Performance enhancing memory interleaver for data frame processing
EP0853404A2 (en) * 1997-01-14 1998-07-15 Digital Vision Laboratories Corporation Device and method for data relay
US5790554A (en) * 1995-10-04 1998-08-04 Bay Networks, Inc. Method and apparatus for processing data packets in a network
US5948079A (en) * 1997-12-19 1999-09-07 Advanced Micro Devices, Inc. System for non-sequential transfer of data packet portions with respective portion descriptions from a computer network peripheral device to host memory
US6032190A (en) * 1997-10-03 2000-02-29 Ascend Communications, Inc. System and method for processing data packets
EP0987859A2 (en) * 1998-09-09 2000-03-22 DeTeMobil, Deutsche Telekom Mobilfunk GmbH Method for the processing of traffic-related switching data in switching nodes of communications networks
US6049543A (en) * 1996-12-27 2000-04-11 Motorola, Inc. Transcoder for use in an ATM-based communications system
US6157644A (en) * 1997-10-07 2000-12-05 Northern Telecom Limited Method and apparatus for accelerating OSI layer 3 routers
WO2001005123A1 (en) * 1999-07-13 2001-01-18 Alteon Web Systems, Inc. Apparatus and method to minimize incoming data loss
US20010053150A1 (en) * 2000-05-24 2001-12-20 David Clear Packet processor with programmable application logic
US6347347B1 (en) * 1999-07-15 2002-02-12 3Com Corporation Multicast direct memory access storing selected ones of data segments into a first-in-first-out buffer and a memory simultaneously when enabled by a processor
US6366961B1 (en) * 1999-03-03 2002-04-02 Nokia Telecommunications, Oy Method and apparatus for providing mini packet switching in IP based cellular access networks
US6401171B1 (en) * 1998-02-27 2002-06-04 Cisco Technology, Inc. Method and device for storing an IP header in a cache memory of a network node
US20020186701A1 (en) * 1996-10-31 2002-12-12 Kaplan Allen D. Multi-protocol telecommunications routing optimization
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US20050100019A1 (en) * 2003-11-10 2005-05-12 Sahita Ravi L. Rule based packet processing engine
US20050169291A1 (en) * 2002-04-30 2005-08-04 Key Kenneth M. System and method for operating a packet buffer in an intermediate node
US6985974B1 (en) 2002-04-08 2006-01-10 Marvell Semiconductor Israel Ltd. Memory interface controller for a network device
US20060064548A1 (en) * 2001-03-21 2006-03-23 Nec Electronics Corporation Cache memory device
US7031296B1 (en) 1995-09-29 2006-04-18 Nortel Networks Limited Method and apparatus for managing the flow of data within a switching device
US7222188B1 (en) 1995-12-08 2007-05-22 Nortel Networks Limited Method and apparatus for forwarding traffic between locally attached networks using level 3 addressing information
US7404040B2 (en) * 2004-12-30 2008-07-22 Intel Corporation Packet data placement in a processor cache
US7468977B1 (en) 1995-07-12 2008-12-23 Nortel Networks Limited LAN/ATM switch having local packet switching and an ATM core fabric
USRE40634E1 (en) 1996-09-26 2009-02-10 Verint Americas Voice interaction analysis module
US20100150158A1 (en) * 2000-05-24 2010-06-17 Jim Cathey Programmable Packet Processor With Flow Resolution Logic
US8902890B2 (en) 2011-05-27 2014-12-02 International Business Machines Corporation Memory saving packet modification
US9036499B2 (en) 1996-10-31 2015-05-19 Patentmarks Communications, Llc Multi-protocol telecommunications routing optimization
US9047417B2 (en) 2012-10-29 2015-06-02 Intel Corporation NUMA aware network interface
US10684973B2 (en) 2013-08-30 2020-06-16 Intel Corporation NUMA node peripheral switch

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3473975B2 (en) * 1993-09-08 2003-12-08 株式会社日立製作所 Network system and communication method in network
US5509006A (en) * 1994-04-18 1996-04-16 Cisco Systems Incorporated Apparatus and method for switching packets using tree memory
US5519704A (en) * 1994-04-21 1996-05-21 Cisco Systems, Inc. Reliable transport protocol for internetwork routing
US6430196B1 (en) 1998-05-01 2002-08-06 Cisco Technology, Inc. Transmitting delay sensitive information over IP over frame relay
US6771642B1 (en) 1999-01-08 2004-08-03 Cisco Technology, Inc. Method and apparatus for scheduling packets in a packet switch
US6735207B1 (en) 2000-06-13 2004-05-11 Cisco Technology, Inc. Apparatus and method for reducing queuing memory access cycles using a distributed queue structure
US6850980B1 (en) 2000-06-16 2005-02-01 Cisco Technology, Inc. Content routing service protocol

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910731A (en) * 1987-07-15 1990-03-20 Hitachi, Ltd. Switching system and method of construction thereof
US4937814A (en) * 1988-04-29 1990-06-26 American Telephone And Telegraph Company Junction switch for packet switching
US4947388A (en) * 1988-04-06 1990-08-07 Hitachi, Ltd. Cell switching system of asynchronous transfer mode
US4969149A (en) * 1988-07-14 1990-11-06 U.S. Philips Corporation Switching network for a switching system
US5062106A (en) * 1989-03-14 1991-10-29 Kokusai Denshin Denwa Co., Ltd. ATM exchange system
US5101402A (en) * 1988-05-24 1992-03-31 Digital Equipment Corporation Apparatus and method for realtime monitoring of network sessions in a local area network
US5130977A (en) * 1989-06-30 1992-07-14 Inmos Limited Message routing
US5140583A (en) * 1989-06-30 1992-08-18 Inmos Limited Message routing
US5140582A (en) * 1989-08-22 1992-08-18 Fujitsu Limited Packet switching system having bus matrix switch

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0375807A1 (en) * 1988-12-30 1990-07-04 Hans Binder Method and apparatus for manufacturing lamellar wood from timber

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910731A (en) * 1987-07-15 1990-03-20 Hitachi, Ltd. Switching system and method of construction thereof
US4947388A (en) * 1988-04-06 1990-08-07 Hitachi, Ltd. Cell switching system of asynchronous transfer mode
US4937814A (en) * 1988-04-29 1990-06-26 American Telephone And Telegraph Company Junction switch for packet switching
US5101402A (en) * 1988-05-24 1992-03-31 Digital Equipment Corporation Apparatus and method for realtime monitoring of network sessions in a local area network
US4969149A (en) * 1988-07-14 1990-11-06 U.S. Philips Corporation Switching network for a switching system
US5062106A (en) * 1989-03-14 1991-10-29 Kokusai Denshin Denwa Co., Ltd. ATM exchange system
US5130977A (en) * 1989-06-30 1992-07-14 Inmos Limited Message routing
US5140583A (en) * 1989-06-30 1992-08-18 Inmos Limited Message routing
US5140582A (en) * 1989-08-22 1992-08-18 Fujitsu Limited Packet switching system having bus matrix switch

Cited By (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5634005A (en) * 1992-11-09 1997-05-27 Kabushiki Kaisha Toshiba System for automatically sending mail message by storing rule according to the language specification of the message including processing condition and processing content
EP0742677A3 (en) * 1995-05-08 1999-09-15 Fujitsu Limited Header converting method
EP0742677A2 (en) * 1995-05-08 1996-11-13 Fujitsu Limited Header converting method
US5752078A (en) * 1995-07-10 1998-05-12 International Business Machines Corporation System for minimizing latency data reception and handling data packet error if detected while transferring data packet from adapter memory to host memory
US7468977B1 (en) 1995-07-12 2008-12-23 Nortel Networks Limited LAN/ATM switch having local packet switching and an ATM core fabric
US7031296B1 (en) 1995-09-29 2006-04-18 Nortel Networks Limited Method and apparatus for managing the flow of data within a switching device
US5790554A (en) * 1995-10-04 1998-08-04 Bay Networks, Inc. Method and apparatus for processing data packets in a network
US7222188B1 (en) 1995-12-08 2007-05-22 Nortel Networks Limited Method and apparatus for forwarding traffic between locally attached networks using level 3 addressing information
US5778414A (en) * 1996-06-13 1998-07-07 Racal-Datacom, Inc. Performance enhancing memory interleaver for data frame processing
US5768515A (en) * 1996-07-08 1998-06-16 Microsoft Corporation Method for generating and storing two segments of HTTP message headers with different lifetimes and combining them to form a single response header
USRE43255E1 (en) 1996-09-26 2012-03-20 Verint Americas, Inc. Machine learning based upon feedback from contact center analysis
USRE43386E1 (en) 1996-09-26 2012-05-15 Verint Americas, Inc. Communication management system for network-based telephones
USRE40634E1 (en) 1996-09-26 2009-02-10 Verint Americas Voice interaction analysis module
USRE41534E1 (en) 1996-09-26 2010-08-17 Verint Americas Inc. Utilizing spare processing capacity to analyze a call center interaction
USRE43183E1 (en) 1996-09-26 2012-02-14 Cerint Americas, Inc. Signal monitoring apparatus analyzing voice communication content
USRE43324E1 (en) 1996-09-26 2012-04-24 Verint Americas, Inc. VOIP voice interaction monitor
US20020186701A1 (en) * 1996-10-31 2002-12-12 Kaplan Allen D. Multi-protocol telecommunications routing optimization
US7307956B2 (en) 1996-10-31 2007-12-11 Connectel, Llc Multi-protocol telecommunications routing optimization
US9036499B2 (en) 1996-10-31 2015-05-19 Patentmarks Communications, Llc Multi-protocol telecommunications routing optimization
US9806988B2 (en) 1996-10-31 2017-10-31 Patentmarks Communications, Llc Multi-protocol telecommunications routing optimization
US6049543A (en) * 1996-12-27 2000-04-11 Motorola, Inc. Transcoder for use in an ATM-based communications system
EP0853404A2 (en) * 1997-01-14 1998-07-15 Digital Vision Laboratories Corporation Device and method for data relay
EP0853404A3 (en) * 1997-01-14 1999-09-29 Digital Vision Laboratories Corporation Device and method for data relay
US6032190A (en) * 1997-10-03 2000-02-29 Ascend Communications, Inc. System and method for processing data packets
US6157644A (en) * 1997-10-07 2000-12-05 Northern Telecom Limited Method and apparatus for accelerating OSI layer 3 routers
US5948079A (en) * 1997-12-19 1999-09-07 Advanced Micro Devices, Inc. System for non-sequential transfer of data packet portions with respective portion descriptions from a computer network peripheral device to host memory
US6401171B1 (en) * 1998-02-27 2002-06-04 Cisco Technology, Inc. Method and device for storing an IP header in a cache memory of a network node
EP0987859A2 (en) * 1998-09-09 2000-03-22 DeTeMobil, Deutsche Telekom Mobilfunk GmbH Method for the processing of traffic-related switching data in switching nodes of communications networks
EP0987859A3 (en) * 1998-09-09 2002-10-30 T-Mobile Deutschland GmbH Method for the processing of traffic-related switching data in switching nodes of communications networks
US6366961B1 (en) * 1999-03-03 2002-04-02 Nokia Telecommunications, Oy Method and apparatus for providing mini packet switching in IP based cellular access networks
WO2001005123A1 (en) * 1999-07-13 2001-01-18 Alteon Web Systems, Inc. Apparatus and method to minimize incoming data loss
US6347347B1 (en) * 1999-07-15 2002-02-12 3Com Corporation Multicast direct memory access storing selected ones of data segments into a first-in-first-out buffer and a memory simultaneously when enabled by a processor
US7693149B2 (en) 2000-05-24 2010-04-06 Alcatel-Lucent Usa Inc. Programmable packet processor with flow resolution logic
EP1158726A3 (en) * 2000-05-24 2004-05-12 Alcatel Internetworking (PE), Inc. Programmable packet processor with data flow resolution logic
US20060251069A1 (en) * 2000-05-24 2006-11-09 Jim Cathey Programmable Packet Processor with Flow Resolution Logic
US20010053150A1 (en) * 2000-05-24 2001-12-20 David Clear Packet processor with programmable application logic
US7075926B2 (en) 2000-05-24 2006-07-11 Alcatel Internetworking, Inc. (Pe) Programmable packet processor with flow resolution logic
US20100150158A1 (en) * 2000-05-24 2010-06-17 Jim Cathey Programmable Packet Processor With Flow Resolution Logic
US20020085560A1 (en) * 2000-05-24 2002-07-04 Jim Cathey Programmable packet processor with flow resolution logic
US8724632B2 (en) 2000-05-24 2014-05-13 Alcatel Lucent Programmable packet processor with flow resolution logic
US8300534B2 (en) 2000-05-24 2012-10-30 Alcatel Lucent Programmable packet processor with flow resolution logic
EP1158724A3 (en) * 2000-05-24 2004-06-23 Alcatel Internetworking (PE), Inc. Packet processor with programmable application logic
US20060064548A1 (en) * 2001-03-21 2006-03-23 Nec Electronics Corporation Cache memory device
US7185149B2 (en) * 2001-03-21 2007-02-27 Nec Electronics Corporation Selective storage in a cache memory device
US6985974B1 (en) 2002-04-08 2006-01-10 Marvell Semiconductor Israel Ltd. Memory interface controller for a network device
US8180966B2 (en) 2002-04-30 2012-05-15 Cisco Technology, Inc. System and method for operating a packet buffer in an intermediate node
US20050169291A1 (en) * 2002-04-30 2005-08-04 Key Kenneth M. System and method for operating a packet buffer in an intermediate node
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US20050100019A1 (en) * 2003-11-10 2005-05-12 Sahita Ravi L. Rule based packet processing engine
US7404040B2 (en) * 2004-12-30 2008-07-22 Intel Corporation Packet data placement in a processor cache
US8902890B2 (en) 2011-05-27 2014-12-02 International Business Machines Corporation Memory saving packet modification
US8982886B2 (en) 2011-05-27 2015-03-17 International Business Machines Corporation Memory saving packet modification
US9047417B2 (en) 2012-10-29 2015-06-02 Intel Corporation NUMA aware network interface
US10684973B2 (en) 2013-08-30 2020-06-16 Intel Corporation NUMA node peripheral switch
US11593292B2 (en) 2013-08-30 2023-02-28 Intel Corporation Many-to-many PCIe switch

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JP3286320B2 (en) 2002-05-27
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DE69228758T2 (en) 1999-12-02
AU2756392A (en) 1993-05-03
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WO1993007692A1 (en) 1993-04-15
EP0606368A1 (en) 1994-07-20

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