US5386156A - Programmable function unit with programmable fast ripple logic - Google Patents
Programmable function unit with programmable fast ripple logic Download PDFInfo
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- US5386156A US5386156A US08/113,154 US11315493A US5386156A US 5386156 A US5386156 A US 5386156A US 11315493 A US11315493 A US 11315493A US 5386156 A US5386156 A US 5386156A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
Definitions
- This invention relates to programmable logic devices in general, and has particular applicability to field programmable gate arrays which utilize programmable function units (PFUs).
- PFUs programmable function units
- FIG. 1 depicts a programmable function unit (PFU) (also termed in the art a configurable logic block).
- PFU programmable function unit
- Reference numeral 13 denotes an 8-bit look-up table which has three inputs denoted by reference numerals 19, 21, and 23, respectively A 0 , B 0 , and the output of multiplexer 15.
- Multiplexer 15 receives inputs C in and C 0 denoted by reference numerals 17 and 35, respectively.
- the output of look-up table 13 is carried on line 25, denoted by Output 0 .
- Look-up table 13 is pre-programmed to perform a predetermined function of the three inputs on lines 19, 21 and 23, and to provide an output designated Output 0 on line 25.
- look-up tables such as table 13, perform general combinatorial or control logic, RAM or data path functions based upon the inputs A 0 , B 0 and C 0 .
- additional inputs to look-up table (LUT) 13 may be provided, and the size of the look-up table increased. For example, if one more input is provided, the LUT 13 may be a 16 bit LUT.
- fast-carry logic In order to increase the speed of data path functions, fast-carry logic is implemented.
- This hard-wired fast-carry operation is provided by a hard-wired logic 27 which has three inputs A 0 and B 0 and C in , reference numerals 19, 21 and 17, respectively.
- This hard-wired carry logic 27 may also receive additional signals used to implement higher-level functions.
- multiplexer 15 selects C in as the third input to LUT 13.
- block 28 receives three inputs, A 0 (19), B 0 (21), and C in (17) and produces Output 0 together with a carry-out signal 18 produced by hard-wired logic 27 as a function of A 0 (19), B 0 (21), and C in , (17).
- This carry-out signal may be used as the carry-in signal to the next block 29.
- each block, 28, can perform a single bit of a fast data path operation.
- blocks such as 28, 29 can be cascaded as needed, thereby creating an n-bit data path function.
- Typical FPGA PFUs may contain one to eight blocks configured similar to block 28 and linked by carry signals in a manner akin to signal 18 between blocks 28 and 29.
- the logic employed in reference numeral 27 is termed "fast-carry logic.”
- One disadvantage to the configuration depicted in FIG. 1 is that the logic in block 27 is hard-wired. Consequently, there is no flexibility in determining the output (e.g., 18) of the fast-carry operation.
- logic function 27 may consume a significant amount of silicon real estate.
- a programmable function unit (PFU) well adapted for use in a field programmable gate array (FPGA) is disclosed.
- the PFU utilizes programmable fast ripple logic.
- a programmable generator and a programmable propagator are each implemented in look-up tables in each block.
- a multiplexer under control of the propagator determines whether to transmit the carry-out from the previous block or to transmit the generator signal.
- FIG. 1 is a schematic diagram of a prior art programmable function unit
- FIGS. 2-4 are schematic diagrams of an illustrative embodiment of the present invention.
- An advantage of the present invention is that it permits the fast-carry logic to be programmable.
- the logic can perform ripple-type functions other than a fast-carry.
- reference numeral 120 denotes a 16-bit look-up table which may be partitioned into two eight-bit look-up tables 122 and 124, respectively, depending upon the mode of operation desired. (By contrast, the system of FIG. 1 contains only one look-up table per block.) As will be explained below, each 16 bit look-up table can be utilized (together with a multiplexer) to perform any function of four inputs (when not in the ripple mode).
- carry-in signal 117 is multiplexed in multiplexer 115 with input signal C 0 denoted by reference numeral 125.
- the output of look-up table 124, denoted by reference numeral 125, is Out 0 .
- the output of look-up table 122, denoted by reference numeral 130 is a propagate signal, PROP 0 .
- PROP 0 is used as a programmable propagate signal.
- Programmable signal 130 is input to multiplexer 128.
- the propagate signal controls multiplexer 128 to determine whether carry-in signal 117 should be "propagated,"i.e., passed through as a carry-out signal 134. (As will be explained below, the carry-out signal of one block becomes the carry-in signal of another block.)
- Look-up table 132 provides a means for generating such a signal, 135.
- look-up table 132 is an 8-bit look-up table.
- inputs to look-up table 132 are signal A 0 denoted by reference numeral 119, signal B 0 denoted by reference numeral 121, and carry-in signal denoted by reference numeral 117 (which are the same inputs to look-up tables 122 and 124).
- Look-up table 132 then produces a "generate" signal 135 which is input to multiplexer 128.
- reference numeral 132 may designate a four-bit look-up table which calculates a generate signal based only upon A 0 and B 0 .
- look-up tables 122 and 124 may be each used to calculate a function of three inputs, A 0 , B 0 , and C 0 (no use is made of C in signal 117 because when the ripple control signal 143 is off ("0"), multiplexer 115 transmits signal C 0 125 and suppresses C in 117.
- the output of look-up table 122 is carried on signal 130 to multiplexer 126.
- the output of look-up table 124 is carried on signal 125, also to multiplexer 126.
- the control signal for multiplexer 126 is received from the output 140 of OR gate 141.
- Inputs to OR gate 141 are signal D 0 142 and ripple mode signal 143. If ripple control signal 143 is off ("0"), the output of OR gate 141 is D 0 . Multiplexer 126 then provides output 145 which is thereby any function of four inputs A 0 , B 0 , C 0 , and D 0 .
- PFU Output 0 is based upon look-up tables 122 and 124, both of which have inputs A 0 , B 0 , and C 0 , as well as the signal D 0 which controls the multiplexer 126.
- a second advantage is that the look-up table creating the propagate function 130 is used in both ripple mode and non-ripple mode.
- the look-up table 132 used to create the generate function is only used during ripple mode.
- FIG. 3 depicts a configuration similar to that shown in FIG. 2.
- programmable look-up table 132 has been replaced by hard-wired logic 200 having inputs A 0 119, B 0 121, and C in 117.
- the general PFU output and propagate portions of the circuit of FIG. 3 are the same as FIG. 2. However, the generate portion of the circuit is hard-wired to perform only a small number of functions.
- FIG. 4 illustrates an embodiment with four blocks with hard-wired combinatorial generate logic, 401, 402, 403 and 404.
- the general PFU output, generate, and propagate functions for each block are similar to those described in detail in connection with FIG. 2.
- the circuit of FIG. 4 features a very fast PFU carry-out on output 311.
- the PFU C in signal 417 is propagated immediately to the PFU C out signal 311 through multiplexer 302 without passing through the fast carry logic in each block, thus decreasing the PFU C in to PFU C out delay. If any of the four propagate signals are "0", then the multiplexer 302 selects the carry out from the last stage 817, thus producing the PFU C out signal 311 in the same manner as in FIG. 3.
Abstract
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US08/113,154 US5386156A (en) | 1993-08-27 | 1993-08-27 | Programmable function unit with programmable fast ripple logic |
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US08/113,154 US5386156A (en) | 1993-08-27 | 1993-08-27 | Programmable function unit with programmable fast ripple logic |
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Cited By (50)
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EP0707382A3 (en) * | 1994-09-20 | 1996-05-22 | Xilinx Inc | |
US5559450A (en) * | 1995-07-27 | 1996-09-24 | Lucent Technologies Inc. | Field programmable gate array with multi-port RAM |
US5570039A (en) * | 1995-07-27 | 1996-10-29 | Lucent Technologies Inc. | Programmable function unit as parallel multiplier cell |
US5623217A (en) * | 1996-02-26 | 1997-04-22 | Lucent Technologies Inc. | Field programmable gate array with write-port enabled memory |
WO1997044730A1 (en) * | 1996-05-20 | 1997-11-27 | Atmel Corporation | Field programmable gate array with distributed ram and increased cell utilization |
US5753545A (en) * | 1994-12-01 | 1998-05-19 | Hughes Electronics Corporation | Effective constant doping in a graded compositional alloy |
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US5818255A (en) * | 1995-09-29 | 1998-10-06 | Xilinx, Inc. | Method and circuit for using a function generator of a programmable logic device to implement carry logic functions |
WO1998051013A1 (en) * | 1997-05-09 | 1998-11-12 | Xilinx, Inc. | Method and structure for providing fast conditional sum in a field programmable gate array |
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US5926036A (en) * | 1991-09-03 | 1999-07-20 | Altera Corporation | Programmable logic array circuits comprising look up table implementation of fast carry adders and counters |
US6049224A (en) * | 1997-10-15 | 2000-04-11 | Lucent Technologies Inc. | Programmable logic device with logic cells having a flexible input structure |
US6118300A (en) * | 1998-11-24 | 2000-09-12 | Xilinx, Inc. | Method for implementing large multiplexers with FPGA lookup tables |
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US6288570B1 (en) | 1993-09-02 | 2001-09-11 | Xilinx, Inc. | Logic structure and circuit for fast carry |
US6288568B1 (en) | 1996-11-22 | 2001-09-11 | Xilinx, Inc. | FPGA architecture with deep look-up table RAMs |
US6292019B1 (en) * | 1999-05-07 | 2001-09-18 | Xilinx Inc. | Programmable logic device having configurable logic blocks with user-accessible input multiplexers |
US6297665B1 (en) | 1996-11-22 | 2001-10-02 | Xilinx, Inc. | FPGA architecture with dual-port deep look-up table RAMS |
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US6323682B1 (en) | 1996-11-22 | 2001-11-27 | Xilinx, Inc. | FPGA architecture with wide function multiplexers |
US6359466B1 (en) * | 1997-09-16 | 2002-03-19 | Vantis Corporation | Circuitry to provide fast carry |
US6359469B1 (en) * | 1996-04-09 | 2002-03-19 | Altera Corporation | Logic element for a programmable logic integrated circuit |
US6359468B1 (en) | 1999-03-04 | 2002-03-19 | Altera Corporation | Programmable logic device with carry look-ahead |
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US6603332B2 (en) * | 1999-02-25 | 2003-08-05 | Xilinx, Inc. | Configurable logic block for PLD with logic gate for combining output with another configurable logic block |
US6724810B1 (en) | 2000-11-17 | 2004-04-20 | Xilinx, Inc. | Method and apparatus for de-spreading spread spectrum signals |
US20050140389A1 (en) * | 2003-11-21 | 2005-06-30 | Infineon Technologies Ag | Logic basic cell and logic basic cell arrangement |
US20060001445A1 (en) * | 2004-07-02 | 2006-01-05 | Tatung Co., Ltd. | Programmable logic block for designing an asynchronous circuit |
EP1659693A2 (en) * | 1995-06-07 | 2006-05-24 | Altera Corporation | Coarse-Grained Look-Up Table Integrated Circuit |
US20070244957A1 (en) * | 2004-11-08 | 2007-10-18 | Jason Redgrave | Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations |
US20070241781A1 (en) * | 2005-03-15 | 2007-10-18 | Brad Hutchings | Variable width management for a memory of a configurable IC |
US20070244960A1 (en) * | 2004-11-08 | 2007-10-18 | Herman Schmit | Configurable IC's with large carry chains |
US20080100336A1 (en) * | 2005-03-15 | 2008-05-01 | Brad Hutchings | Hybrid Logic/Interconnect Circuit in a Configurable IC |
US20080129335A1 (en) * | 2005-03-15 | 2008-06-05 | Brad Hutchings | Configurable IC with interconnect circuits that have select lines driven by user signals |
US20090327987A1 (en) * | 2008-06-26 | 2009-12-31 | Steven Teig | Timing operations in an IC with configurable circuits |
US20100001759A1 (en) * | 2007-03-20 | 2010-01-07 | Steven Teig | Configurable ic having a routing fabric with storage elements |
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Publication number | Priority date | Publication date | Assignee | Title |
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US5926036A (en) * | 1991-09-03 | 1999-07-20 | Altera Corporation | Programmable logic array circuits comprising look up table implementation of fast carry adders and counters |
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DE102004056322B4 (en) * | 2003-11-21 | 2012-07-19 | Infineon Technologies Ag | Logic Ground Cell and Logic Ground Cell Arrangement |
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US20110163781A1 (en) * | 2004-06-30 | 2011-07-07 | Andre Rohe | Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit |
US8415973B2 (en) | 2004-06-30 | 2013-04-09 | Tabula, Inc. | Configurable integrated circuit with built-in turns |
US8350591B2 (en) | 2004-06-30 | 2013-01-08 | Tabula, Inc. | Configurable IC's with dual carry chains |
US8281273B2 (en) | 2004-06-30 | 2012-10-02 | Tabula, Inc. | Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit |
US20110202586A1 (en) * | 2004-06-30 | 2011-08-18 | Steven Teig | Configurable ic's with dual carry chains |
US20060001445A1 (en) * | 2004-07-02 | 2006-01-05 | Tatung Co., Ltd. | Programmable logic block for designing an asynchronous circuit |
US7307450B2 (en) * | 2004-07-02 | 2007-12-11 | Tatung Company | Programmable logic block for designing an asynchronous circuit |
US20070244957A1 (en) * | 2004-11-08 | 2007-10-18 | Jason Redgrave | Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations |
US7743085B2 (en) | 2004-11-08 | 2010-06-22 | Tabula, Inc. | Configurable IC with large carry chains |
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