US5375080A - Performing arithmetic on composite operands to obtain a binary outcome for each multi-bit component - Google Patents
Performing arithmetic on composite operands to obtain a binary outcome for each multi-bit component Download PDFInfo
- Publication number
- US5375080A US5375080A US07/993,213 US99321392A US5375080A US 5375080 A US5375080 A US 5375080A US 99321392 A US99321392 A US 99321392A US 5375080 A US5375080 A US 5375080A
- Authority
- US
- United States
- Prior art keywords
- data item
- component data
- component
- bit
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002131 composite material Substances 0.000 title claims abstract description 66
- 238000012545 processing Methods 0.000 claims description 66
- 238000000034 method Methods 0.000 claims description 53
- 238000003860 storage Methods 0.000 description 13
- 238000013500 data storage Methods 0.000 description 10
- 230000009467 reduction Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000012937 correction Methods 0.000 description 2
- 238000010191 image analysis Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 241000405965 Scomberomorus brasiliensis Species 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000003702 image correction Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
- G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
Definitions
- T 1 +1 two thresholds can be applied, (T 1 +1) and T 2 , where T 2 >T 1 .
- the binary outcome can be ON only if the result with T 2 is OFF and the result with (T 1 +1) is ON.
- the binary outcome can be obtained by inverting the result from T 2 and then ANDing with the result from (T 1 +1).
- Another way to determine whether a component's value is in a range is to subtract T 1 , set all buffer bits, and subtract T 2 -T 1 from the result of the first subtraction. If a component's buffer bit is OFF, the component is in the range bounded by T 1 and T 2 .
- FIG. 3 is a flow chart showing general acts in obtaining flag bits by performing an arithmetic operation in parallel.
- FIG. 7 is a schematic flow diagram showing operations that implement the acts in FIG. 3 to obtain zero flag bits with arithmetic and logic operations.
- a “data storage medium” or “storage medium” is a physical medium that can store data. Examples of data storage media include magnetic media such as floppy disks, optical media such as CD-ROMs, and semiconductor media such as semiconductor ROMs and RAMs. As used herein, “storage medium” covers one or more distinct units of a medium that together store a body of data. For example, a set of floppy disks storing a single body of data would be a storage medium.
- a "binary outcome operation” is an operation that obtains a binary result that depends on the numerical value of an operand.
- a "processing position" is a part of a processor or processing circuitry that can perform an operation on one bit.
- a binary number can be represented as a sum of powers of two. Each bit in the binary number indicates presence or absence of a particular power of two in the sum. Therefore, the "most significant bit” or “MSB” of a binary number is the bit that indicates presence or absence of the largest power of two and the "least significant bit” or “LSB” is the bit that indicates presence or absence of the smallest power of two. For example, if the binary number includes K bits and the powers of two in the sum range from 2 0 to 2 K-1 , the MSB indicates whether the binary number is at least as great as 2 K-1 and the LSB indicates whether the binary number is even or odd. In general, the MSB can indicate a binary number's sign, or, if sign is not ambiguous, whether the number is in the upper or lower half of a range of possible values.
- the act in box 172 forms first and second composite operands, with each pair of data items obtained in box 170 being divided, one in the first composite operand and the other in the second.
- Each composite operand includes component data items and a buffer bit adjacent the most significant bit of each component data item; if the component data items were obtained from previous image processing operations, they may be received in box 170 in composite operands having this form.
- Paired component data items are aligned with each other and of the same length so that an arithmetic operation that subtracts the second operand from the first operand subtracts each component data item in the second operand from its paired component data item in the first operand.
- the buffer bits are similarly aligned and have the value one in the first operand and zero in the second operand. As noted in relation to FIG. 4, if an equivalent addition is performed, all buffer bits should have the value zero.
- FIGS. 6 and 7 illustrate two implementations of the general act described in relation to FIG. 3 that obtain flag bits that indicate whether the result of an arithmetic operation is zero.
- flag bits are obtained by reduction.
- flag bits are obtained by an additional operation in parallel.
- an XOR operation is performed on operand 180 and operand 200, in which bits 202, 204, and 206 and all other bits aligned with buffer bits have the value ON and all bits not aligned with buffer bits have the value OFF.
- the XOR operation therefore produces operand 210, in which data items 212, 214, and 216 have the same values respectively as data items 182, 184, and 186 in operand 180, but in which buffer bits 222, 224, and 226 are the inverses respectively of buffer bits 192, 194, and 196.
- Bit 242 is obtained by ORing bits 232 and 234; bit 244 by ORing bits 236 and 237; and bit 246 by ORing bits 238 and 239. Bits 242, 244, and 246 are flag bits indicating that resulting data item 184 indicated a zero result while data items 182 and 186 indicated results not equal to zero.
- the act in box 344 then performs another operation as described in relation to FIG. 4 to obtain a second operand with a sign flag bit for each component data item.
- This operation subtracts the constant value (T 2 -T 1 ) from each component's resulting data item in the first operand, as modified by box 342.
- a component's flag bit in the second operand indicates whether the component is in the range between T 1 and T 2 , where T 2 >T 1 . If a component is in the range, its sign flag bit in the second operand has the value zero, because of a borrow signal. If the component is above or below the range, its sign flag bit in the second operand has the value one.
- FIG. 9 the implementation of FIG. 9 could be used with open or closed ranges.
- the invention has been described in relation to implementations that operate on data relating to images, but might also be implemented to operate on data that do not relate to an image.
Abstract
Description
Claims (27)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/993,213 US5375080A (en) | 1992-12-18 | 1992-12-18 | Performing arithmetic on composite operands to obtain a binary outcome for each multi-bit component |
EP93309862A EP0602887B1 (en) | 1992-12-18 | 1993-12-08 | Performing arithmetic on composite operands |
DE69328071T DE69328071T2 (en) | 1992-12-18 | 1993-12-08 | Performing arithmetic on compiled operands |
JP31778293A JP3637923B2 (en) | 1992-12-18 | 1993-12-17 | Method for operating a processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/993,213 US5375080A (en) | 1992-12-18 | 1992-12-18 | Performing arithmetic on composite operands to obtain a binary outcome for each multi-bit component |
Publications (1)
Publication Number | Publication Date |
---|---|
US5375080A true US5375080A (en) | 1994-12-20 |
Family
ID=25539249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/993,213 Expired - Lifetime US5375080A (en) | 1992-12-18 | 1992-12-18 | Performing arithmetic on composite operands to obtain a binary outcome for each multi-bit component |
Country Status (4)
Country | Link |
---|---|
US (1) | US5375080A (en) |
EP (1) | EP0602887B1 (en) |
JP (1) | JP3637923B2 (en) |
DE (1) | DE69328071T2 (en) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5519649A (en) * | 1993-06-04 | 1996-05-21 | Nippon Steel Corporation | Micro-processor having rapid condition comparison function |
US5651121A (en) * | 1992-12-18 | 1997-07-22 | Xerox Corporation | Using mask operand obtained from composite operand to perform logic operation in parallel with composite operand |
US5655131A (en) * | 1992-12-18 | 1997-08-05 | Xerox Corporation | SIMD architecture for connection to host processor's bus |
US5907842A (en) * | 1995-12-20 | 1999-05-25 | Intel Corporation | Method of sorting numbers to obtain maxima/minima values with ordering |
US6009451A (en) * | 1996-11-22 | 1999-12-28 | Lucent Technologies Inc. | Method for generating barrel shifter result flags directly from input data |
US6036350A (en) * | 1995-12-20 | 2000-03-14 | Intel Corporation | Method of sorting signed numbers and solving absolute differences using packed instructions |
US6934728B2 (en) | 2001-06-01 | 2005-08-23 | Microchip Technology Incorporated | Euclidean distance instructions |
US6937084B2 (en) | 2001-06-01 | 2005-08-30 | Microchip Technology Incorporated | Processor with dual-deadtime pulse width modulation generator |
US6952711B2 (en) | 2001-06-01 | 2005-10-04 | Microchip Technology Incorporated | Maximally negative signed fractional number multiplication |
US6976158B2 (en) | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Repeat instruction with interrupt |
US6975679B2 (en) | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Configuration fuses for setting PWM options |
US6985986B2 (en) | 2001-06-01 | 2006-01-10 | Microchip Technology Incorporated | Variable cycle interrupt disabling |
US7003543B2 (en) * | 2001-06-01 | 2006-02-21 | Microchip Technology Incorporated | Sticky z bit |
US7007172B2 (en) | 2001-06-01 | 2006-02-28 | Microchip Technology Incorporated | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection |
US7020788B2 (en) | 2001-06-01 | 2006-03-28 | Microchip Technology Incorporated | Reduced power option |
US20080133628A1 (en) * | 2006-12-05 | 2008-06-05 | Abhijit Giri | System and method for an efficient comparision operation of multi-bit vectors in a digital logic circuit |
US7467178B2 (en) | 2001-06-01 | 2008-12-16 | Microchip Technology Incorporated | Dual mode arithmetic saturation processing |
US7966480B2 (en) | 2001-06-01 | 2011-06-21 | Microchip Technology Incorporated | Register pointer trap to prevent errors due to an invalid pointer value in a register |
US8577182B1 (en) | 2010-07-13 | 2013-11-05 | Google Inc. | Method and system for automatically cropping images |
US9070182B1 (en) | 2010-07-13 | 2015-06-30 | Google Inc. | Method and system for automatically cropping images |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1892589B (en) * | 1995-08-31 | 2011-02-23 | 英特尔公司 | Apparatus for performing multimedia application operation, system and method for implementing the operation |
GB2362731B (en) | 2000-05-23 | 2004-10-06 | Advanced Risc Mach Ltd | Parallel processing of multiple data values within a data word |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4161784A (en) * | 1978-01-05 | 1979-07-17 | Honeywell Information Systems, Inc. | Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands |
US4474882A (en) * | 1980-10-09 | 1984-10-02 | Daicel Chemical Industries, Ltd. | Microbiological process for the preparation of unsaturated dicarboxylic acids |
US4742552A (en) * | 1983-09-27 | 1988-05-03 | The Boeing Company | Vector image processing system |
US4789957A (en) * | 1986-03-28 | 1988-12-06 | Texas Instruments Incorporated | Status output for a bit slice ALU |
US4811266A (en) * | 1986-11-05 | 1989-03-07 | Honeywell Bull Inc. | Multifunction arithmetic indicator |
EP0431961A2 (en) * | 1989-12-08 | 1991-06-12 | Xerox Corporation | Image reduction/enlargement technique |
US5038313A (en) * | 1989-01-31 | 1991-08-06 | Nec Corporation | Floating-point processor provided with high-speed detector of overflow and underflow exceptional conditions |
EP0460970A2 (en) * | 1990-06-08 | 1991-12-11 | Xerox Corporation | Dense aggregative hierarchical techniques for data analysis |
EP0464601A2 (en) * | 1990-06-25 | 1992-01-08 | Nec Corporation | Arithmetic operation system |
EP0486143A2 (en) * | 1990-11-15 | 1992-05-20 | International Business Machines Corporation | Parallel processing of data |
US5129092A (en) * | 1987-06-01 | 1992-07-07 | Applied Intelligent Systems,Inc. | Linear chain of parallel processors and method of using same |
-
1992
- 1992-12-18 US US07/993,213 patent/US5375080A/en not_active Expired - Lifetime
-
1993
- 1993-12-08 EP EP93309862A patent/EP0602887B1/en not_active Expired - Lifetime
- 1993-12-08 DE DE69328071T patent/DE69328071T2/en not_active Expired - Lifetime
- 1993-12-17 JP JP31778293A patent/JP3637923B2/en not_active Expired - Lifetime
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4161784A (en) * | 1978-01-05 | 1979-07-17 | Honeywell Information Systems, Inc. | Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands |
US4474882A (en) * | 1980-10-09 | 1984-10-02 | Daicel Chemical Industries, Ltd. | Microbiological process for the preparation of unsaturated dicarboxylic acids |
US4742552A (en) * | 1983-09-27 | 1988-05-03 | The Boeing Company | Vector image processing system |
US4789957A (en) * | 1986-03-28 | 1988-12-06 | Texas Instruments Incorporated | Status output for a bit slice ALU |
US4811266A (en) * | 1986-11-05 | 1989-03-07 | Honeywell Bull Inc. | Multifunction arithmetic indicator |
US5129092A (en) * | 1987-06-01 | 1992-07-07 | Applied Intelligent Systems,Inc. | Linear chain of parallel processors and method of using same |
US5038313A (en) * | 1989-01-31 | 1991-08-06 | Nec Corporation | Floating-point processor provided with high-speed detector of overflow and underflow exceptional conditions |
EP0431961A2 (en) * | 1989-12-08 | 1991-06-12 | Xerox Corporation | Image reduction/enlargement technique |
EP0460970A2 (en) * | 1990-06-08 | 1991-12-11 | Xerox Corporation | Dense aggregative hierarchical techniques for data analysis |
US5280547A (en) * | 1990-06-08 | 1994-01-18 | Xerox Corporation | Dense aggregative hierarhical techniques for data analysis |
EP0464601A2 (en) * | 1990-06-25 | 1992-01-08 | Nec Corporation | Arithmetic operation system |
EP0486143A2 (en) * | 1990-11-15 | 1992-05-20 | International Business Machines Corporation | Parallel processing of data |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5651121A (en) * | 1992-12-18 | 1997-07-22 | Xerox Corporation | Using mask operand obtained from composite operand to perform logic operation in parallel with composite operand |
US5655131A (en) * | 1992-12-18 | 1997-08-05 | Xerox Corporation | SIMD architecture for connection to host processor's bus |
US5519649A (en) * | 1993-06-04 | 1996-05-21 | Nippon Steel Corporation | Micro-processor having rapid condition comparison function |
US5907842A (en) * | 1995-12-20 | 1999-05-25 | Intel Corporation | Method of sorting numbers to obtain maxima/minima values with ordering |
US6036350A (en) * | 1995-12-20 | 2000-03-14 | Intel Corporation | Method of sorting signed numbers and solving absolute differences using packed instructions |
US6128614A (en) * | 1995-12-20 | 2000-10-03 | Intel Corporation | Method of sorting numbers to obtain maxima/minima values with ordering |
US6009451A (en) * | 1996-11-22 | 1999-12-28 | Lucent Technologies Inc. | Method for generating barrel shifter result flags directly from input data |
US6985986B2 (en) | 2001-06-01 | 2006-01-10 | Microchip Technology Incorporated | Variable cycle interrupt disabling |
US7243372B2 (en) | 2001-06-01 | 2007-07-10 | Microchip Technology Incorporated | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection |
US6952711B2 (en) | 2001-06-01 | 2005-10-04 | Microchip Technology Incorporated | Maximally negative signed fractional number multiplication |
US6976158B2 (en) | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Repeat instruction with interrupt |
US6975679B2 (en) | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Configuration fuses for setting PWM options |
US6934728B2 (en) | 2001-06-01 | 2005-08-23 | Microchip Technology Incorporated | Euclidean distance instructions |
US7003543B2 (en) * | 2001-06-01 | 2006-02-21 | Microchip Technology Incorporated | Sticky z bit |
US7007172B2 (en) | 2001-06-01 | 2006-02-28 | Microchip Technology Incorporated | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection |
US7020788B2 (en) | 2001-06-01 | 2006-03-28 | Microchip Technology Incorporated | Reduced power option |
US6937084B2 (en) | 2001-06-01 | 2005-08-30 | Microchip Technology Incorporated | Processor with dual-deadtime pulse width modulation generator |
US7966480B2 (en) | 2001-06-01 | 2011-06-21 | Microchip Technology Incorporated | Register pointer trap to prevent errors due to an invalid pointer value in a register |
US7467178B2 (en) | 2001-06-01 | 2008-12-16 | Microchip Technology Incorporated | Dual mode arithmetic saturation processing |
US20080133628A1 (en) * | 2006-12-05 | 2008-06-05 | Abhijit Giri | System and method for an efficient comparision operation of multi-bit vectors in a digital logic circuit |
US8037120B2 (en) * | 2006-12-05 | 2011-10-11 | Analog Devices, Inc. | System and method for an efficient comparison operation of multi-bit vectors in a digital logic circuit |
US8577182B1 (en) | 2010-07-13 | 2013-11-05 | Google Inc. | Method and system for automatically cropping images |
US9070182B1 (en) | 2010-07-13 | 2015-06-30 | Google Inc. | Method and system for automatically cropping images |
US9355432B1 (en) | 2010-07-13 | 2016-05-31 | Google Inc. | Method and system for automatically cropping images |
US9552622B2 (en) | 2010-07-13 | 2017-01-24 | Google Inc. | Method and system for automatically cropping images |
Also Published As
Publication number | Publication date |
---|---|
JP3637923B2 (en) | 2005-04-13 |
EP0602887B1 (en) | 2000-03-15 |
DE69328071T2 (en) | 2000-07-13 |
DE69328071D1 (en) | 2000-04-20 |
EP0602887A1 (en) | 1994-06-22 |
JPH06222906A (en) | 1994-08-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5375080A (en) | Performing arithmetic on composite operands to obtain a binary outcome for each multi-bit component | |
US5651121A (en) | Using mask operand obtained from composite operand to perform logic operation in parallel with composite operand | |
US5408670A (en) | Performing arithmetic in parallel on composite operands with packed multi-bit components | |
US5437045A (en) | Parallel processing with subsampling/spreading circuitry and data transfer circuitry to and from any processing unit | |
Schrack | Finding neighbors of equal size in linear quadtrees and octrees in constant time | |
Duff | Review of the CLIP image processing system | |
Sternberg | Parallel architectures for image processing | |
EP0328063B1 (en) | Absolute value calculating circuit having a single adder | |
Klaiber et al. | A resource-efficient hardware architecture for connected component analysis | |
Choudhary et al. | Connected component labeling on coarse grain parallel computers: an experimental study | |
US5402533A (en) | Method and apparatus for approximating a signed value between two endpoint values in a three-dimensional image rendering device | |
US5428804A (en) | Edge crossing circuitry for SIMD architecture | |
Banerji | A novel implementation method for addition and subtraction in residue number systems | |
Nakano et al. | Hardware n choose k counters with applications to the partial exhaustive search | |
WO2022266842A1 (en) | Multi-thread data processing method and apparatus | |
KR900002631B1 (en) | Image data processing method and apparatus | |
JPH05225331A (en) | Image processing method | |
JP2840706B2 (en) | Image processing method | |
JP3611898B2 (en) | Image processing device | |
RU2050594C1 (en) | Device for monitoring of contours of two-dimensional objects | |
Le et al. | Computational-RAM implementation of mean-average scalable vector quantization for real-time progressive image transmission | |
Chung et al. | A neighbor-finding algorithm for bincode-based images on reconfigurable meshes | |
JPH01302475A (en) | Labeling system for image data | |
Wong et al. | A new scalable systolic array processor architecture for simultaneous discrete convolution of k different (nxn) filter coefficient planes with a single image plane | |
Schmidt et al. | KPROC—an instruction systolic architecture for parallel prefix applications |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: XEROX CORPORATION, CONNECTICUT Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:DAVIES, DANIEL;REEL/FRAME:006378/0450 Effective date: 19921217 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: BANK ONE, NA, AS ADMINISTRATIVE AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:013153/0001 Effective date: 20020621 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, AS COLLATERAL AGENT, TEXAS Free format text: SECURITY AGREEMENT;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:015134/0476 Effective date: 20030625 Owner name: JPMORGAN CHASE BANK, AS COLLATERAL AGENT,TEXAS Free format text: SECURITY AGREEMENT;ASSIGNOR:XEROX CORPORATION;REEL/FRAME:015134/0476 Effective date: 20030625 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: XEROX CORPORATION, CONNECTICUT Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A. AS SUCCESSOR-IN-INTEREST ADMINISTRATIVE AGENT AND COLLATERAL AGENT TO JPMORGAN CHASE BANK;REEL/FRAME:066728/0193 Effective date: 20220822 |