US5338974A - RF power transistor package - Google Patents

RF power transistor package Download PDF

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US5338974A
US5338974A US08/032,227 US3222793A US5338974A US 5338974 A US5338974 A US 5338974A US 3222793 A US3222793 A US 3222793A US 5338974 A US5338974 A US 5338974A
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leads
input
output
ground
lead
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US08/032,227
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David S. Wisherd
Howard D. Bartlow
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Spectrian Corp
P-Wave Holdings LLC
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Spectrian Corp
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Assigned to P-WAVE HOLDINGS, LLC reassignment P-WAVE HOLDINGS, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: POWERWAVE TECHNOLOGIES, INC.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • This invention relates generally to transistor packages, and particularly the invention relates to RF, microwave, and high-power transistor packages and transistors where high gain and maximum stability must be obtained.
  • FIG. 1A is an exploded perspective view of a conventional RF power transistor package including a ceramic substrate 2, transistor 3, cover 4, leads 5 extending from the substrate 2, and wire bonds 6 connecting the transistor to the leads.
  • FIG. 1B is a plan view of the lead structure for the RF power transistor package.
  • the leads are bonded to and extend from the ceramic substrate shown by dotted line 10.
  • the transistor is mounted on a pad or island 12 centrally disposed (approximately) on the substrate and electrically isolated from the leads.
  • An input lead 14 is positioned between ground leads 16, 18 on one side of the island 12, and an output lead 20 is positioned between the ground leads 16, 18 on the opposite side of the island 12.
  • Wire bonds selectively connect the transistor emitter, base, and collector to the input, output, and ground leads.
  • This lead frame has been in use for many years, but a major drawback of the lead structure lies in the current path length between the transistor ground leads.
  • the present invention reduces ground resistance and inductance, reduced input and output inductance, and improves stability and gain by providing shorter current paths in ground lead structures.
  • a plurality of input leads and a plurality of output leads are provided in the new structure with ground leads provided between input leads and between output leads.
  • the current path between leads is reduced with an attendant reduction in resistance and inductance of the current path.
  • the use of a plurality of input leads and a plurality of output leads reduces the input and output inductances, respectively.
  • FIG. 1A is an exploded perspective view of a conventional RF power transistor and package
  • FIG. 1B is a plan view of the lead structure in the conventional RF power transistor.
  • FIG. 2 is a plan view of a lead structure for an RF power transistor package in accordance with one embodiment of the invention.
  • FIG. 3 and FIG. 4 illustrate current paths in the lead structures of FIG. 1 and FIG. 2, respectively.
  • FIG. 5 is a plan view of a lead structure in accordance with another embodiment of the invention.
  • FIG. 6 and FIG. 7 are schematics of two port networks for use and analysis of the effects of current path length.
  • FIG. 2 is a plan view of a lead structure in accordance of one embodiment of the invention.
  • a ceramic substrate 10 as indicated by broken lines and an island or pad 12 is centrally disposed (approximately) on the ceramic substrate for receiving the semiconductor chip.
  • two input leads 24 extend from one side of the ceramic substrate with an input ground lead 26 therebetween.
  • the ground leads 28, 30 are provided on either end of the ceramic substrate 10.
  • a pair of output leads 34 extend from the opposite side of the ceramic substrate 10 with an output ground lead 32 therebetween.
  • the ground leads 28, 30 extend across the ends of the ceramic substrate.
  • the ceramic substrates 10 and islands 12 are the same size.
  • the current path lengths between the transistor and package ground are reduced by 65-70%.
  • FIGS. 3 and 4 the length of the longest possible current path from the island to ground is illustrated.
  • the island widths of the two embodiments are identical, so the current path of interest is the horizontal direction.
  • the longest current path of the prior art is shown in FIG. 3 and designated by the numeral 40 with current flow indicated by the arrows. Assuming a common starting reference point for common lead current, i.e., at the top of the package at the starting points of the common lead buslines, the length of the path is from the center line to either side of the package, or a length of 0.160 inch.
  • FIG. 4 shows the improvements embodied in the configuration of FIG. 2.
  • the starting points for the current path length are indicated by the arrows.
  • the island width of both the prior art and the invention is 0.300 inch, but the current path length of the embodiment of FIG. 2 is 0.053 inch, compared to 0.160 inch for the prior art lead structure of FIG. 1.
  • the path length is reduced by a factor of 3. Accordingly, both resistance and inductance of these current paths are reduced by a factor of 3, thus improving stability and gain of the transistor.
  • FIG. 5 is a plan view of another embodiment of the invention with the ceramic substrate again labeled 10 and the island labeled 12.
  • the number of input leads 50 can be increased to any number with input ground leads 52 provided between the adjacent input leads.
  • the output leads 54 are increased by a like number with output ground leads 56 provided between adjacent output leads.
  • the end ground leads 58, 60 are provided at either end of the ceramic package.
  • FIG. 6 shows two-port networks that are connected in series. If the arbitrary two-port networks of FIG. 6 are replaced with the networks used in FIG. 7, a model of the transistor package is obtained. The current path to ground, as seen by the transistor, is modeled by the resistor/inductor combination in FIG. 7. Thus, the current path may be modeled as variable series feedback of a two-port network. As the current path length is increased, the magnitude of the series feedback also increases.
  • the gain of the two-port network increases as the series feedback is reduced.
  • the improved RF and microwave power transistor package yields a shorter current path (lower series feedback), and hence increased gain over the conventional design.
  • the transistor in FIG. 7 is reconfigured to a common-base transistor, reduction of the series feedback impedance yields increased stability.
  • the improved power RF and microwave transistor package yields improved stability and gain.
  • a further benefit of this invention is significantly reduced cost of the package when compared with prior art RF transistor packages, as well as thermal impedance improvements of about 30% or more.

Abstract

An RF power transistor is mounted on a ceramic substrate with a plurality of input leads extending from one edge of the substrate, a plurality of output leads extending from an opposite edge of the substrate, a plurality of input ground leads with ground leads positioned between adjacent input leads, and a plurality of output ground leads with ground lead positioned between adjacent output leads. All ground leads are ohmically connected with the current paths between adjacent ground leads reduced in length.

Description

BACKGROUND OF THE INVENTION
This invention relates generally to transistor packages, and particularly the invention relates to RF, microwave, and high-power transistor packages and transistors where high gain and maximum stability must be obtained.
FIG. 1A is an exploded perspective view of a conventional RF power transistor package including a ceramic substrate 2, transistor 3, cover 4, leads 5 extending from the substrate 2, and wire bonds 6 connecting the transistor to the leads.
FIG. 1B is a plan view of the lead structure for the RF power transistor package. The leads are bonded to and extend from the ceramic substrate shown by dotted line 10. The transistor is mounted on a pad or island 12 centrally disposed (approximately) on the substrate and electrically isolated from the leads. An input lead 14 is positioned between ground leads 16, 18 on one side of the island 12, and an output lead 20 is positioned between the ground leads 16, 18 on the opposite side of the island 12. Wire bonds selectively connect the transistor emitter, base, and collector to the input, output, and ground leads. This lead frame has been in use for many years, but a major drawback of the lead structure lies in the current path length between the transistor ground leads.
SUMMARY OF THE INVENTION
The present invention reduces ground resistance and inductance, reduced input and output inductance, and improves stability and gain by providing shorter current paths in ground lead structures. A plurality of input leads and a plurality of output leads are provided in the new structure with ground leads provided between input leads and between output leads. Thus, the current path between leads is reduced with an attendant reduction in resistance and inductance of the current path. Further, the use of a plurality of input leads and a plurality of output leads reduces the input and output inductances, respectively.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawing.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1A is an exploded perspective view of a conventional RF power transistor and package, and FIG. 1B is a plan view of the lead structure in the conventional RF power transistor.
FIG. 2 is a plan view of a lead structure for an RF power transistor package in accordance with one embodiment of the invention.
FIG. 3 and FIG. 4 illustrate current paths in the lead structures of FIG. 1 and FIG. 2, respectively.
FIG. 5 is a plan view of a lead structure in accordance with another embodiment of the invention.
FIG. 6 and FIG. 7 are schematics of two port networks for use and analysis of the effects of current path length.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
FIG. 2 is a plan view of a lead structure in accordance of one embodiment of the invention. Again, a ceramic substrate 10 as indicated by broken lines and an island or pad 12 is centrally disposed (approximately) on the ceramic substrate for receiving the semiconductor chip. In this embodiment, two input leads 24 extend from one side of the ceramic substrate with an input ground lead 26 therebetween. Again, the ground leads 28, 30 are provided on either end of the ceramic substrate 10. Similarly, a pair of output leads 34 extend from the opposite side of the ceramic substrate 10 with an output ground lead 32 therebetween. The ground leads 28, 30 extend across the ends of the ceramic substrate.
In the prior art structure of FIG. 1 and the embodiment of the invention in FIG. 2, the ceramic substrates 10 and islands 12 are the same size. However, since the single input and output leads of FIG. 1 are now replaced by a pair of input and output leads in FIG. 2, the current path lengths between the transistor and package ground are reduced by 65-70%. Referring to FIGS. 3 and 4, the length of the longest possible current path from the island to ground is illustrated. The island widths of the two embodiments are identical, so the current path of interest is the horizontal direction. The longest current path of the prior art is shown in FIG. 3 and designated by the numeral 40 with current flow indicated by the arrows. Assuming a common starting reference point for common lead current, i.e., at the top of the package at the starting points of the common lead buslines, the length of the path is from the center line to either side of the package, or a length of 0.160 inch.
FIG. 4 shows the improvements embodied in the configuration of FIG. 2. Using the same designation 40 as in FIG. 3, the starting points for the current path length are indicated by the arrows. Note that the island width of both the prior art and the invention is 0.300 inch, but the current path length of the embodiment of FIG. 2 is 0.053 inch, compared to 0.160 inch for the prior art lead structure of FIG. 1. Thus, the path length is reduced by a factor of 3. Accordingly, both resistance and inductance of these current paths are reduced by a factor of 3, thus improving stability and gain of the transistor.
FIG. 5 is a plan view of another embodiment of the invention with the ceramic substrate again labeled 10 and the island labeled 12. The number of input leads 50 can be increased to any number with input ground leads 52 provided between the adjacent input leads. Similarly, the output leads 54 are increased by a like number with output ground leads 56 provided between adjacent output leads. The end ground leads 58, 60 are provided at either end of the ceramic package.
Using simple two-port analysis, the effects of current path length may be evaluated. FIG. 6 shows two-port networks that are connected in series. If the arbitrary two-port networks of FIG. 6 are replaced with the networks used in FIG. 7, a model of the transistor package is obtained. The current path to ground, as seen by the transistor, is modeled by the resistor/inductor combination in FIG. 7. Thus, the current path may be modeled as variable series feedback of a two-port network. As the current path length is increased, the magnitude of the series feedback also increases.
In a common-emitter configuration, the gain of the two-port network increases as the series feedback is reduced. from the previous current flow analysis, the improved RF and microwave power transistor package yields a shorter current path (lower series feedback), and hence increased gain over the conventional design.
If the transistor in FIG. 7 is reconfigured to a common-base transistor, reduction of the series feedback impedance yields increased stability. Thus, regardless of the transistor topology, the improved power RF and microwave transistor package yields improved stability and gain.
A further benefit of this invention is significantly reduced cost of the package when compared with prior art RF transistor packages, as well as thermal impedance improvements of about 30% or more.
There has been described an improved RF power transistor package and lead structure which improves gain and stability of an RF power transistor. While the invention has been described with reference to specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of invention as defined by the appended claims.

Claims (13)

What is claimed is:
1. A lead structure for an RF power transistor comprising:
a ceramic substrate having opposing sides and opposing ends,
an approximately centrally disposed pad for mounting a semiconductor chip on one side of said substrate,
a plurality of input leads attached to and extending from said ceramic substrate on one side of said substrate,
a plurality of input ground leads attached to and extending from said ceramic substrate with an input ground lead positioned between all adjacent input leads,
a plurality of output leads attached to and extending from said ceramic substrate on an opposite side of said substrate, and
a plurality of output ground leads attached to and extending from said ceramic substrate with an output ground lead positioned between all adjacent output leads.
2. The lead structure as defined by claim 1 and further including two integral input and output ground leads extending from said ceramic substrate at said opposing ends of said ceramic substrate and integral with all of said plurality of input ground leads and said plurality of output ground leads.
3. The lead structure as defined by claim 2 and including two input leads and two output leads, an input ground lead between said two input leads, and an output ground lead between said two output leads.
4. The lead structure as defined by claim 3 wherein said two integral input and output ground leads are ohmically connected with said input ground lead and with said output ground lead.
5. The lead structure as defined by claim 2 wherein said plurality of input leads exceeds two in number and said plurality of output leads exceeds two in number.
6. The lead structure as defined by claim 5 wherein said two integral input and output ground leads are ohmically connected with said plurality of input ground leads and said plurality of output ground leads.
7. The lead structure as defined by claim 6 wherein the number of input leads is n, and the number of input ground leads is n+1 whereby input ground leads are provided at each end of said plurality of input leads.
8. The lead structure as defined by claim 7 wherein the number of output leads is n, and the number of output ground leads is n+1 whereby output ground leads are provided at each end of said plurality of output leads.
9. The lead structure as defined by claim 1 wherein the number of input leads is n, and the number of input ground leads is n+1 whereby input ground leads are provided at each end of said plurality of input leads.
10. The lead structure as defined by claim 1 wherein the number of output leads is n, and the number of output ground leads is n+1 whereby output ground leads are provided at each end of said plurality of output leads.
11. The lead structure as defined by claim 1 and including a semiconductor transistor mounted on said approximately centrally disposed pad.
12. The lead structure as defined by claim 7 and further including wire bonds selectively interconnecting said transistor to said plurality of input leads, said plurality of output leads, and said plurality of ground leads.
13. The lead structure as defined by claim 8 and further including a cover affixed to said ceramic substrate for encapsulating said semiconductor transistor.
US08/032,227 1993-03-17 1993-03-17 RF power transistor package Expired - Lifetime US5338974A (en)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631476A (en) * 1994-08-02 1997-05-20 Sgs-Thomson Microelectronics S.R.L. MOS-technology power device chip and package assembly
WO1997032395A1 (en) * 1996-02-28 1997-09-04 California Micro Devices Corporation Methods and apparatus for improving frequency response of integrated rc filters
US5838070A (en) * 1995-12-28 1998-11-17 Sanyo Electric Co., Ltd. Apparatus having a substrate and electronic circuit solder-connected with the substrate
US5949649A (en) * 1998-04-28 1999-09-07 Spectrian, Inc. High power semiconductor device having bolt-down ceramic platform
US20020017714A1 (en) * 1998-07-31 2002-02-14 Kang Rim Choi Electrically isolated power semiconductor package
US20030197255A1 (en) * 2001-09-20 2003-10-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6727585B2 (en) 2001-05-04 2004-04-27 Ixys Corporation Power device with a plastic molded package and direct bonded substrate
US6731002B2 (en) 2001-05-04 2004-05-04 Ixys Corporation High frequency power device with a plastic molded package and direct bonded substrate
US8193091B2 (en) * 2002-01-09 2012-06-05 Panasonic Corporation Resin encapsulated semiconductor device and method for manufacturing the same

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US5760662A (en) * 1996-02-28 1998-06-02 California Micro Devices Corporation Methods and apparatus for improving frequency response of integrated RC filters with additional ground pins
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US20020017714A1 (en) * 1998-07-31 2002-02-14 Kang Rim Choi Electrically isolated power semiconductor package
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US6727585B2 (en) 2001-05-04 2004-04-27 Ixys Corporation Power device with a plastic molded package and direct bonded substrate
US6731002B2 (en) 2001-05-04 2004-05-04 Ixys Corporation High frequency power device with a plastic molded package and direct bonded substrate
US20030197255A1 (en) * 2001-09-20 2003-10-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6867484B2 (en) * 2001-09-20 2005-03-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US8193091B2 (en) * 2002-01-09 2012-06-05 Panasonic Corporation Resin encapsulated semiconductor device and method for manufacturing the same

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