US5295250A - Microprocessor having barrel shifter and direct path for directly rewriting output data of barrel shifter to its input - Google Patents
Microprocessor having barrel shifter and direct path for directly rewriting output data of barrel shifter to its input Download PDFInfo
- Publication number
- US5295250A US5295250A US07/659,606 US65960691A US5295250A US 5295250 A US5295250 A US 5295250A US 65960691 A US65960691 A US 65960691A US 5295250 A US5295250 A US 5295250A
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- United States
- Prior art keywords
- barrel shifter
- register
- data
- shift
- rewrite
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 238000003780 insertion Methods 0.000 abstract description 15
- 230000037431 insertion Effects 0.000 abstract description 15
- 238000000605 extraction Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
Definitions
- the present invention relates to a microprocessor and, more particularly, to a technique for performing high-speed processing of instructions (to be referred to as bit field operation instructions hereinafter) to perform extraction, insertion, and comparison of consecutive bit strings (to be referred to as bit fields hereinafter) in word data.
- bit field operation instructions to perform extraction, insertion, and comparison of consecutive bit strings
- a microprocessor has bit field operation instructions, as macro instructions, to perform extraction, insertion, and comparison of bit fields.
- bit field operation instructions are executed by operating a barrel shifter using a microprogram.
- FIG. 4 shows a conventional barrel shifter. Referring to FIG.
- reference numeral 101 denotes a data bus in a microprocessor; 102 and 103, registers (to be respectively referred to as an SFT0 and an SFT1 hereinafter) for holding input data; 104, a selector (to be referred to as a BSEL hereinafter) as a main body of the barrel shifter; 105, a register (to be referred to as an SFTOUT hereinafter) for holding output data from the barrel shifter; 106, a control section of the barrel shifter; 107, a microinstruction latch (to be referred to as an MI hereinafter) for storing microinstructions to operate the control section 106; 108, a register (to be referred to as an SFTOP hereinafter) for holding a shift amount to be supplied to the barrel shifter; 109, a register (to be referred to as an SFTOPR hereinafter) for holding various types of shift operations (e.g., "logic left shift", “logic right shift", "arithmetic
- FIG. 5 shows a microprogram used to perform a shift instruction in the barrel shifter in FIG. 4. Referring to FIG. 5, the following operations are performed in the respective steps:
- First step setting a shift amount COUNT in the SFTOP 108, and setting a shift type in the SFTOPR 109
- Second step setting data SRC (to be shifted) in the SFT0 102 and the SFT1 103
- Third step extracting a shift result from the SFTOUT 105, storing it in a destination DST, and terminating the microprogram
- SFTOPR is a control instruction to set a value in the SETOPR 109 shown in FIG. 4. More specifically, "SFTOPR” includes: SHL . . . logic left shift; SHR . . . logic right shift; SAL . . . arithmetic left shift; SAR . . .arithmetic right shift; ROL . . . left rotate; and ROR . . . right rotate.
- "END" represents the end of a microprogram
- " "represents transfer of data to a register.
- "SFTIN"in the second step is a virtual register for indirectly designating the SFT0 102 and the SFT1 103.
- the value of the data SRC (to be shifted) is stored in the SFT0 102 and the SFT1 103 in accordance with the value of the SFTOPR 109, as shown in FIG. 7.
- values can be independently set in the SFT0 102 and the SFT1 103.
- "SFT0" and SFT1" are to be described in the microprogram in place of "SFTIN".
- FIG. 6 is a timing chart of the barrel shifter in the execution of the microprogram shown in FIG. 5.
- Signal names in FIG. 6 correspond to signal names in FIG. 4, although "CLOCK”, “SFTUOP”, and “SFTDIR” are not shown in FIG. 4.
- "CLOCK” indicates a clock.
- SFTUOP is the absolute value of "SFTOP”. If the value of "SFTOP” is negative, it indicates a shift direction (left or right) opposite to a direction designated by "SFTOPR”.
- SFTDIR indicates a final shift direction determined by the signs of "SFTOPR” and "SFTOP". In this conventional system, the positive/negative sign of "SFTOP" influences a shift direction.
- SFTDIR is directly determined by "SFTOPR”
- SFTUOP and "SFTOP” are set to be the same value.
- the BSEL 104 regards the SFT0 102 and the SFT1 103 as linked data of two words (e.g., 64 bits), extracts consecutive one-word data (e.g., 32 bits) from a specific bit position in the two-word data, and stores it in the SFTOUT 105.
- This one-word data is determined in accordance with the values of "SFTUOP" and "SFTDIR", as shown in FIG. 8.
- Bit field operation instructions can be performed by the above-described barrel shifter.
- insertion of a bit field will be considered as an example.
- Bit field insertion is an operation of inserting data of consecutive several bits (LEN bits) extracted from one-word data SRC in a range of consecutive LEN bits starting from a given bit position (bit BIT) of another one-word data DST. Assume, in this case, that lower LEN bit data is extracted from the data SRC to be inserted in the data DST.
- insertion of a bit field can be performed by the barrel shifter in accordance with a procedure shown in FIG. 9.
- FIG. 9 FIG.
- FIG. 10 shows a microprogram which describes this procedure.
- FIG. 11 is a timing chart of the execution of the microprogram. Referring to FIG. 11, the value of "SFTOUT", which is changed three times, is read out in the minimum procedure. This is the minimum procedure for inserting a bit field. That is, the minimum procedure for bit field insertion using the conventional barrel shifter has 6 steps (6 clocks), as shown in FIG. 10.
- bit field insertion using the conventional barrel requires at least 6 clocks.
- a microprogram is required to perform exception detection and the like as well as an operation of a barrel shifter. For this reason, it is difficult to perform bit field insertion using only 6 clocks.
- bit field operation instructions are required to be executed at higher speed. High-speed bit field operations cannot be performed by using the conventional barrel shifter.
- a microprocessor comprising a barrel shifter as a shift unit controlled by a microprogram and operated by microinstructions for performing extraction, insertion, and comparison of consecutive bit strings in word data, rewrite means for directly rewriting output data from the barrel shifter into an input thereof, and control means for controlling the rewrite means by using the microprogram.
- FIG. 1 is a block diagram showing a barrel shifter of a microprocessor according to the present invention
- FIG. 2 is a view showing a microprogram to execute insertion of a bit field by using the barrel shifter in FIG. 1;
- FIG. 3 is a timing chart of an operation of the barrel shifter shown in FIG. 1 in the execution of the microprogram in FIG. 2;
- FIG. 4 is a block diagram showing a barrel shifter of a conventional microprocessor
- FIG. 5 is a view showing a microprogram to execute a shift operation by using the barrel shifter in FIG. 4;
- FIG. 6 is a timing chart of an operation of the barrel shifter shown in FIG. 4 in the execution of the microprogram in FIG. 5;
- FIGS. 7A, 7B, 7C, 7D, 7E and 7F are views for explaining values to be set in "SFT0" and "SFT1" when a shift operation is performed by using the barrel shifter in FIG. 4;
- FIGS. 8(a) and 8(b) are views for explaining positions where data, as outputs from the barrel shifter in FIG. 4, are respectively extracted from the inputs SFT0 and SFT1;
- FIG. 9 is a view showing a procedure for executing bit field insertion by using the barrel shifter
- FIG. 10 is a view showing a microprogram for executing the procedure shown in FIG. 9 by using the conventional barrel shifter.
- FIG. 11 is a timing chart of an operation of the barrel shifter shown in FIG. 4 in the execution of the microprogram in FIG. 10.
- FIG. 1 shows a barrel shifter according to an embodiment of the present invention.
- Reference numerals 101 to 112 in FIG. 1 denote the same parts as those of the conventional barrel shifter in FIG. 4.
- the arrangement shown in FIG. 1 includes: a rewrite path 113 extending from an output SFTOUT 105 of the barrel shifter to inputs SFT0 102 and SFT1 103; multiplexers 114 and 115; and strobe signals SFT0S 116 and SFT1S 117 to latch the value of the SFTOUT 105 into the input SFT0 102 or the SFT1 103 through the rewrite path 113.
- the multiplexer 114 selects data to be latched in the SFT0 102 from a data bus 101 or the rewrite path 113 in accordance with a strobe signal SFT0WR 111 and the strobe signal SFT0S 116.
- the multiplexer 115 selects data to be latched in the SFT1 103 from the data bus 101 and the rewrite path 113 in accordance with a strobe signal SFT1WR 112 and the strobe signal SFT1S 117.
- the strobe signal SFT0WR 111 is generated when the following condition is designated in the microprogram:
- the strobe signal SFT1WR 112 is generated when the following condition is designated in the microprogram:
- the strobe signals SFT0S 116 and SFT1S 117 are generated when a rewrite operation with respect to the SFT0 102 or the SFT1 103 through the rewrite path is designated in the microprogram.
- Various methods of designating a rewrite operation are available. In this case, a rewrite operation is designated at the same time as a shift type SFTOPR is designated.
- a microinstruction SFTOPR designates a rewrite operation with respect to the SFT0 102 at the same time as the type of shift is changed
- a microinstruction SFTOPR designates a rewrite operation with respect to the SFT1 103 at the same time as the type of shift is changed
- a microinstruction SFTOPR (SFT01) is used to designate simultaneous rewrite operations with respect to the SFT0 102 and the SFT1 103 at the same time as the type of shift is changed.
- a microprogram for performing bit field insertion shown in FIG. 10 can be rewritten, as shown in FIG. 2.
- FIG. 3 shows a timing chart in the execution of the microprogram shown in FIG. 2.
- a shift result SFTOUT is influenced by a change in the shift type SFTOPR two clocks after the change.
- the SFTOUT is rewritten in the SFT0 or the SFT1 by rewrite designation 0.5 clocks after the change, and the SFTOUT is updated by the rewritten SFT0 or SFT1 0.5 clocks after the rewrite operation. Therefore, the description of the microprogram becomes complicated.
- bit field insertion can be performed within 5 clocks. As indicated by the timing chart in FIG. 3, according to this embodiment, insertion of a bit field can be performed without wasting even one clock.
- the first embodiment employs the method of designating a rewrite operation of output data from the barrel shifter into its input at the same time as the shift type is changed.
- a rewrite operation may be designated by transfer of data to a virtual register as in the case of data transfer to the virtual register SFTIN in a microinstruction.
- a rewrite path is additionally arranged in a conventional barrel shifter to rewrite output data therefrom into its input.
- a bit field operation instruction can be performed by most efficiently using the barrel shifter with a minimum number of steps.
Abstract
Description
SFTIN= . . .
or
SFT0= . . .
SFTIN= . . .
or
SFT1= . . .
Claims (3)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2046086A JPH03248226A (en) | 1990-02-26 | 1990-02-26 | Microprocessor |
JP2-46086 | 1990-02-26 |
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US5295250A true US5295250A (en) | 1994-03-15 |
Family
ID=12737179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US07/659,606 Expired - Fee Related US5295250A (en) | 1990-02-26 | 1991-02-21 | Microprocessor having barrel shifter and direct path for directly rewriting output data of barrel shifter to its input |
Country Status (3)
Country | Link |
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US (1) | US5295250A (en) |
EP (1) | EP0445630A3 (en) |
JP (1) | JPH03248226A (en) |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5465340A (en) * | 1992-01-30 | 1995-11-07 | Digital Equipment Corporation | Direct memory access controller handling exceptions during transferring multiple bytes in parallel |
US5473751A (en) * | 1992-05-13 | 1995-12-05 | Nec Corporation | High speed paint-out graphics device LSI and method of forming paint-out drawing |
US5497474A (en) * | 1993-02-25 | 1996-03-05 | Franklin Electronic Publishers, Incorporated | Data stream addressing |
WO1996017289A1 (en) * | 1994-12-01 | 1996-06-06 | Intel Corporation | A novel processor having shift operations |
US5535412A (en) * | 1994-08-26 | 1996-07-09 | Nec Corporation | Circular buffer controller |
US5964828A (en) * | 1997-11-13 | 1999-10-12 | Electronic Data System Corporation | Method and system for maintaining the integrity of objects |
US6052522A (en) * | 1997-10-30 | 2000-04-18 | Infineon Technologies North America Corporation | Method and apparatus for extracting data stored in concatenated registers |
US6757820B2 (en) | 1999-11-18 | 2004-06-29 | Sun Microsystems, Inc. | Decompression bit processing with a general purpose alignment tool |
US20040215681A1 (en) * | 1994-12-01 | 2004-10-28 | Lin Derrick Chu | Method and apparatus for executing packed shift operations |
US20050114631A1 (en) * | 2003-11-26 | 2005-05-26 | Sunplus Technology Co., Ltd. | Processor device capable of cross-boundary alignment of plural register data and the method thereof |
US20050138342A1 (en) * | 2003-12-19 | 2005-06-23 | Sunplus Technology Co., Ltd. | Processor-based automatic alignment device and method for data movement |
US20050138343A1 (en) * | 2003-12-19 | 2005-06-23 | Sunplus Technology Co., Ltd. | Processor-based structure and method for loading unaligned data |
US20050138344A1 (en) * | 2003-12-19 | 2005-06-23 | Sunplus Technology Co., Ltd. | Device and method for writing data in a processor to memory at unaligned location |
US20050289321A1 (en) * | 2004-05-19 | 2005-12-29 | James Hakewill | Microprocessor architecture having extendible logic |
US20070074012A1 (en) * | 2005-09-28 | 2007-03-29 | Arc International (Uk) Limited | Systems and methods for recording instruction sequences in a microprocessor having a dynamically decoupleable extended instruction pipeline |
CN106201440A (en) * | 2016-06-28 | 2016-12-07 | 上海兆芯集成电路有限公司 | The CPU of character string comparison optimization and its operational approach |
US9959247B1 (en) | 2017-02-17 | 2018-05-01 | Google Llc | Permuting in a matrix-vector processor |
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- 1991-02-21 US US07/659,606 patent/US5295250A/en not_active Expired - Fee Related
- 1991-02-26 EP EP19910102852 patent/EP0445630A3/en not_active Ceased
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Cited By (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5465340A (en) * | 1992-01-30 | 1995-11-07 | Digital Equipment Corporation | Direct memory access controller handling exceptions during transferring multiple bytes in parallel |
US5473751A (en) * | 1992-05-13 | 1995-12-05 | Nec Corporation | High speed paint-out graphics device LSI and method of forming paint-out drawing |
US5497474A (en) * | 1993-02-25 | 1996-03-05 | Franklin Electronic Publishers, Incorporated | Data stream addressing |
US5535412A (en) * | 1994-08-26 | 1996-07-09 | Nec Corporation | Circular buffer controller |
US5666298A (en) * | 1994-12-01 | 1997-09-09 | Intel Corporation | Method for performing shift operations on packed data |
WO1996017289A1 (en) * | 1994-12-01 | 1996-06-06 | Intel Corporation | A novel processor having shift operations |
US5818739A (en) * | 1994-12-01 | 1998-10-06 | Intel Corporation | Processor for performing shift operations on packed data |
US20040215681A1 (en) * | 1994-12-01 | 2004-10-28 | Lin Derrick Chu | Method and apparatus for executing packed shift operations |
US7480686B2 (en) | 1994-12-01 | 2009-01-20 | Intel Corporation | Method and apparatus for executing packed shift operations |
US6052522A (en) * | 1997-10-30 | 2000-04-18 | Infineon Technologies North America Corporation | Method and apparatus for extracting data stored in concatenated registers |
US5964828A (en) * | 1997-11-13 | 1999-10-12 | Electronic Data System Corporation | Method and system for maintaining the integrity of objects |
US6757820B2 (en) | 1999-11-18 | 2004-06-29 | Sun Microsystems, Inc. | Decompression bit processing with a general purpose alignment tool |
US20050114631A1 (en) * | 2003-11-26 | 2005-05-26 | Sunplus Technology Co., Ltd. | Processor device capable of cross-boundary alignment of plural register data and the method thereof |
US7308553B2 (en) * | 2003-11-26 | 2007-12-11 | Sunplus Technology Co., Ltd. | Processor device capable of cross-boundary alignment of plural register data and the method thereof |
US20050138343A1 (en) * | 2003-12-19 | 2005-06-23 | Sunplus Technology Co., Ltd. | Processor-based structure and method for loading unaligned data |
US20050138344A1 (en) * | 2003-12-19 | 2005-06-23 | Sunplus Technology Co., Ltd. | Device and method for writing data in a processor to memory at unaligned location |
US20050138342A1 (en) * | 2003-12-19 | 2005-06-23 | Sunplus Technology Co., Ltd. | Processor-based automatic alignment device and method for data movement |
US7308556B2 (en) * | 2003-12-19 | 2007-12-11 | Sunplus Technology Co., Ltd | Device and method for writing data in a processor to memory at unaligned location |
US7308554B2 (en) * | 2003-12-19 | 2007-12-11 | Sunplus Technology Co., Ltd. | Processor-based automatic alignment device and method for data movement |
US7308555B2 (en) * | 2003-12-19 | 2007-12-11 | Sunplus Technology Co., Ltd. | Processor-based structure and method for loading unaligned data |
US9003422B2 (en) | 2004-05-19 | 2015-04-07 | Synopsys, Inc. | Microprocessor architecture having extendible logic |
US8719837B2 (en) | 2004-05-19 | 2014-05-06 | Synopsys, Inc. | Microprocessor architecture having extendible logic |
US20050289321A1 (en) * | 2004-05-19 | 2005-12-29 | James Hakewill | Microprocessor architecture having extendible logic |
US20070074012A1 (en) * | 2005-09-28 | 2007-03-29 | Arc International (Uk) Limited | Systems and methods for recording instruction sequences in a microprocessor having a dynamically decoupleable extended instruction pipeline |
US7971042B2 (en) | 2005-09-28 | 2011-06-28 | Synopsys, Inc. | Microprocessor system and method for instruction-initiated recording and execution of instruction sequences in a dynamically decoupleable extended instruction pipeline |
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CN106201440B (en) * | 2016-06-28 | 2018-10-23 | 上海兆芯集成电路有限公司 | The central processing unit of character string comparison optimization and its operating method |
US9959247B1 (en) | 2017-02-17 | 2018-05-01 | Google Llc | Permuting in a matrix-vector processor |
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US10592583B2 (en) | 2017-02-17 | 2020-03-17 | Google Llc | Permuting in a matrix-vector processor |
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US10956537B2 (en) | 2017-02-17 | 2021-03-23 | Google Llc | Permuting in a matrix-vector processor |
US11748443B2 (en) | 2017-02-17 | 2023-09-05 | Google Llc | Permuting in a matrix-vector processor |
Also Published As
Publication number | Publication date |
---|---|
EP0445630A3 (en) | 1991-12-27 |
EP0445630A2 (en) | 1991-09-11 |
JPH03248226A (en) | 1991-11-06 |
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