US4849365A - Selective integrated circuit interconnection - Google Patents
Selective integrated circuit interconnection Download PDFInfo
- Publication number
- US4849365A US4849365A US07/156,378 US15637888A US4849365A US 4849365 A US4849365 A US 4849365A US 15637888 A US15637888 A US 15637888A US 4849365 A US4849365 A US 4849365A
- Authority
- US
- United States
- Prior art keywords
- region
- major surface
- emitter region
- integrated circuit
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/01—Bipolar transistors-ion implantation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/055—Fuse
Abstract
Description
Claims (2)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/156,378 US4849365A (en) | 1988-02-16 | 1988-02-16 | Selective integrated circuit interconnection |
US07/324,933 US4929995A (en) | 1988-02-16 | 1989-03-17 | Selective integrated circuit interconnection |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/156,378 US4849365A (en) | 1988-02-16 | 1988-02-16 | Selective integrated circuit interconnection |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/324,933 Division US4929995A (en) | 1988-02-16 | 1989-03-17 | Selective integrated circuit interconnection |
Publications (1)
Publication Number | Publication Date |
---|---|
US4849365A true US4849365A (en) | 1989-07-18 |
Family
ID=22559324
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/156,378 Expired - Lifetime US4849365A (en) | 1988-02-16 | 1988-02-16 | Selective integrated circuit interconnection |
Country Status (1)
Country | Link |
---|---|
US (1) | US4849365A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6372592B1 (en) | 1996-12-18 | 2002-04-16 | United States Of America As Represented By The Secretary Of The Navy | Self-aligned MOSFET with electrically active mask |
Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3641516A (en) * | 1969-09-15 | 1972-02-08 | Ibm | Write once read only store semiconductor memory |
US3725148A (en) * | 1970-08-31 | 1973-04-03 | D Kendall | Individual device tuning using localized solid-state reactions |
US3733690A (en) * | 1970-07-13 | 1973-05-22 | Intersil Inc | Double junction read only memory and process of manufacture |
US3781825A (en) * | 1970-05-12 | 1973-12-25 | Siemens Ag | Programmable fixed data memory utilizing schottky diodes |
US4069068A (en) * | 1976-07-02 | 1978-01-17 | International Business Machines Corporation | Semiconductor fabrication method for improved device yield by minimizing pipes between common conductivity type regions |
US4172741A (en) * | 1977-09-06 | 1979-10-30 | National Semiconductor Corporation | Method for laser trimming of bi-FET circuits |
US4203781A (en) * | 1978-12-27 | 1980-05-20 | Bell Telephone Laboratories, Incorporated | Laser deformation of semiconductor junctions |
US4387503A (en) * | 1981-08-13 | 1983-06-14 | Mostek Corporation | Method for programming circuit elements in integrated circuits |
US4403399A (en) * | 1981-09-28 | 1983-09-13 | Harris Corporation | Method of fabricating a vertical fuse utilizing epitaxial deposition and special masking |
US4534804A (en) * | 1984-06-14 | 1985-08-13 | International Business Machines Corporation | Laser process for forming identically positioned alignment marks on the opposite sides of a semiconductor wafer |
US4598462A (en) * | 1983-04-07 | 1986-07-08 | Rca Corporation | Method for making semiconductor device with integral fuse |
US4624046A (en) * | 1982-01-04 | 1986-11-25 | Fairchild Camera & Instrument Corp. | Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM |
US4635345A (en) * | 1985-03-14 | 1987-01-13 | Harris Corporation | Method of making an intergrated vertical NPN and vertical oxide fuse programmable memory cell |
US4651409A (en) * | 1984-02-09 | 1987-03-24 | Ncr Corporation | Method of fabricating a high density, low power, merged vertical fuse/bipolar transistor |
US4651408A (en) * | 1984-01-05 | 1987-03-24 | Northern Telecom Limited | Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies |
US4665295A (en) * | 1984-08-02 | 1987-05-12 | Texas Instruments Incorporated | Laser make-link programming of semiconductor devices |
US4674176A (en) * | 1985-06-24 | 1987-06-23 | The United States Of America As Represented By The United States Department Of Energy | Planarization of metal films for multilevel interconnects by pulsed laser heating |
US4783424A (en) * | 1981-09-03 | 1988-11-08 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of making a semiconductor device involving simultaneous connection and disconnection |
-
1988
- 1988-02-16 US US07/156,378 patent/US4849365A/en not_active Expired - Lifetime
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3641516A (en) * | 1969-09-15 | 1972-02-08 | Ibm | Write once read only store semiconductor memory |
US3781825A (en) * | 1970-05-12 | 1973-12-25 | Siemens Ag | Programmable fixed data memory utilizing schottky diodes |
US3733690A (en) * | 1970-07-13 | 1973-05-22 | Intersil Inc | Double junction read only memory and process of manufacture |
US3725148A (en) * | 1970-08-31 | 1973-04-03 | D Kendall | Individual device tuning using localized solid-state reactions |
US4069068A (en) * | 1976-07-02 | 1978-01-17 | International Business Machines Corporation | Semiconductor fabrication method for improved device yield by minimizing pipes between common conductivity type regions |
US4172741A (en) * | 1977-09-06 | 1979-10-30 | National Semiconductor Corporation | Method for laser trimming of bi-FET circuits |
US4203781A (en) * | 1978-12-27 | 1980-05-20 | Bell Telephone Laboratories, Incorporated | Laser deformation of semiconductor junctions |
US4387503A (en) * | 1981-08-13 | 1983-06-14 | Mostek Corporation | Method for programming circuit elements in integrated circuits |
US4783424A (en) * | 1981-09-03 | 1988-11-08 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of making a semiconductor device involving simultaneous connection and disconnection |
US4403399A (en) * | 1981-09-28 | 1983-09-13 | Harris Corporation | Method of fabricating a vertical fuse utilizing epitaxial deposition and special masking |
US4624046A (en) * | 1982-01-04 | 1986-11-25 | Fairchild Camera & Instrument Corp. | Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM |
US4598462A (en) * | 1983-04-07 | 1986-07-08 | Rca Corporation | Method for making semiconductor device with integral fuse |
US4651408A (en) * | 1984-01-05 | 1987-03-24 | Northern Telecom Limited | Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies |
US4651409A (en) * | 1984-02-09 | 1987-03-24 | Ncr Corporation | Method of fabricating a high density, low power, merged vertical fuse/bipolar transistor |
US4534804A (en) * | 1984-06-14 | 1985-08-13 | International Business Machines Corporation | Laser process for forming identically positioned alignment marks on the opposite sides of a semiconductor wafer |
US4665295A (en) * | 1984-08-02 | 1987-05-12 | Texas Instruments Incorporated | Laser make-link programming of semiconductor devices |
US4635345A (en) * | 1985-03-14 | 1987-01-13 | Harris Corporation | Method of making an intergrated vertical NPN and vertical oxide fuse programmable memory cell |
US4674176A (en) * | 1985-06-24 | 1987-06-23 | The United States Of America As Represented By The United States Department Of Energy | Planarization of metal films for multilevel interconnects by pulsed laser heating |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6372592B1 (en) | 1996-12-18 | 2002-04-16 | United States Of America As Represented By The Secretary Of The Navy | Self-aligned MOSFET with electrically active mask |
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