US4675555A - IC input buffer emitter follower with current source value dependent upon connection length for equalizing signal delay - Google Patents

IC input buffer emitter follower with current source value dependent upon connection length for equalizing signal delay Download PDF

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US4675555A
US4675555A US06/813,941 US81394185A US4675555A US 4675555 A US4675555 A US 4675555A US 81394185 A US81394185 A US 81394185A US 4675555 A US4675555 A US 4675555A
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constant current
input signal
emitter follower
input
current sources
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Yoshinori Okajima
Masaki Ohiwa
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Fujitsu VLSI Ltd
Fujitsu Ltd
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Fujitsu VLSI Ltd
Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01825—Coupling arrangements, impedance matching circuits

Definitions

  • the present invention relates to a semiconductor device, and more particularly, to the improvement of a signal input portion of an emitter-coupled logic (ECL) integrated circuit.
  • ECL emitter-coupled logic
  • the chip area of an advanced ECL integrated circuit is often increased, and therefore, some connection lines between a plurality of input signal pads and a plurality of input signal buffers such as address buffers become long. Consequently, if the distance between an input signal pad and an emitter follower transistor used as a signal input portion is large, for example, the input capacitance of an input signal is increased due to the parasitic capacitance of a long connection therebetween, thus increasing the access time.
  • the emitter follower transistor of the signal input portion is in proximity to the input signal pad, while a current source of the signal input portion is left on the circuit side of the input signal buffer, thereby reducing the input capacitance for an input signal.
  • the current flowing through the emitter follower is increased, the potential fall due to the resistance of signal paths is large so that the post input stage circuits may not operate normally.
  • the propagation speed of the input signal level becomes large due to the parasitic capacitance, thereby reducing the access time.
  • An object of the present invention is to minimize the potential fall of signal level due to the resistance of the signal path in a long connection line, and to minimize the delay in the access time.
  • a constant current source is provided in proximity to the emitter follower and is connected thereto, and a current value of the constant current source is changed in accordance with connection line length, i.e., the parasitic capacitance between the emitter follower and the input signal buffer. That is, the larger the connection line length, the greater the current value of the constant current source.
  • connection line between the emitter follower and the input signal buffer is greatly reduced, reduction in potential due to the connection resistance is reduced, i.e., the reduction of a signal level is lessened. Also, since the current value of the constant current source is increased when the parasitic capacitance is large, the delay in the fall of the signal level is reduced.
  • FIG. 1 is a partial layout diagram of a general semiconductor device
  • FIGS. 2 and 3 are circuit diagrams showing prior art semiconductor devices
  • FIG. 4 is a timing diagram showing the operation of the circuit of FIG. 3;
  • FIG. 5 is a circuit diagram illustrating an embodiment of the semiconductor device according to the present invention.
  • FIGS. 6A and 6B are circuit diagrams of the constant current sources I il of FIG. 5;
  • FIGS. 7A, 7B, 8A and 8B are layout diagrams of FIGS. 6A and 6B.
  • FIG. 9 is a circuit diagram illustrating a second embodiment of the semiconductor device according to the present invention.
  • FIG. 1 which illustrates a general semiconductor device such as an ECL memory device
  • a plurality of pads P 1 through P 7 are connected via connection lines or conductor L 0 through L 7 to a signal input portion such as address buffers BUF.
  • a signal input portion such as address buffers BUF.
  • some of the connection lines L 0 through L 7 become long.
  • the connection line L 0 between the pad P 0 and the address buffers BUF is relatively short, but the connection line L 7 between the pad P 7 and the address buffers BUF is very long.
  • the signal input portion includes emitter followers, diodes, current sources, and the like, other than the address buffers BUF.
  • FIG. 1 The device of FIG. 1 will be explained in detail with reference to FIGS. 2 and 3.
  • emitter followers Q 01 , . . ., and Q 71 , diodes D 01 , . . ., and D 71 , and constant current sources I 01 , . . ., and I 71 are linked between the pads P 0 , . . ., and P 7 , and the address buffers BUF 0 , . . ., and BUF 7 .
  • Each of the address buffers BUF 0 , . . ., and BUF 7 has the same configuration.
  • the address buffer BUF 0 comprises two transistors Q 02 and Q 03 , and a constant current source I 02 , to form a current switch.
  • the diode D 01 serves as a level shift means so that the center of the input amplitude of a signal applied to the base of the transistor Q 02 conforms to a reference potential V ref0 applied to the base of the transistor Q 03 , thereby improving the operation speed of the address buffers.
  • V ref0 a reference potential
  • the change of the output signal A 0 from high to low is delayed as compared with the change of the output signal A 0 from low to high. This delay is reduced by the diode D 0 .
  • V EE designates a power supply voltage such as -5 V.
  • the distance between the pad P 1 and the emitter follower Q 01 is relatively small, and accordingly, the input capacitance encountered by an address signal applied to the pad P 1 is small due to the parasitic capacitance C p0 of the short connection line L 0 , thus reducing the access time.
  • the distance between the pad P 7 and the emitter follower Q 171 is relatively long, and accordingly, the input capacitance of an address signal applied to the pad P 7 is large due to the parasitic capacitance C P7 of the long connection line L 7 , thus increasing the access time.
  • the emitter followers Q 01 , . . ., and Q 71 are provided in proximity to the pads P 0 , . . ., and P 7 , respectively, and are connected thereto. That is, in this case, the input capacitance at the post input stage of each of the pads P0 , ..., and P 7 is reduced by 1/ ⁇ ( ⁇ represents the current amplification factor of the emitter follower such as Q 01 )
  • the constant current sources I 01 through I 71 are provided in proximity to the emitter followers Q 01 through Q 71 , respectively.
  • the current values of the constant current sources can be reduced even when the length of the connections lines L 0 through L 7 is large. Even in this case, however, the access time is dependent upon the length of the connection lines L 0 through L 7 which should be charged or discharged.
  • the current values of the constant current sources I 01 through I 71 are determined in accordance with the length of the connection lines L 0 through L 7 , i.e., the parasitic capacitances C P0 through C P7 , respectively. That is, the ability of the emitter followers Q01 through Q 71 to charge the lines are changed in accordance with the parasitic capacitances C P0 through C P7 . For example, when the length of the connection line such as L 0 is small, the current value of the constant current source I 01 is small, and when the length of the connection line such as L 7 is large, the constant current source I 07 is large.
  • the constant current source I 01 is comprised of a transistor Q R having a base to which a definite voltage V RB is applied, and a resistor R.
  • the constant current source I 71 is comprised of a transistor Q R having a base to which the definite voltage V RB is applied, and five resistors R. That is, the current value of the constant current source is determined in accordance with the number of resistors R. For example, as shown in FIGS. 7A and 7B, the number of resistors R is substantially determined by the number to contacts of the resistors R. Also, as shown in FIGS. 8A and 8B, the number of resistors R can be determined by changing the connection pattern of the transistor Q IR and the resistors R.
  • the current values of the constant current sources I 01 through I 71 are changed in accordance with the parasitic capacitances C P0 through C P7 , respectively.
  • This change of the current values of the constant current sources slightly affects the base-emitter voltage V BE of the emitter followers Q 01 through Q 71 .
  • the high and low levels of an address signal at the base of the transistor Q 02 (or Q 72 ) are slightly changed, and accordingly, the center of the amplitude of the address signal at the base of the transistor Q 02 (or Q 72 ) is shifted from the reference potential V ref0 (or V ref7 ).
  • the reference potential such as V ref0 is changed in accordance with the current value of the constant current source such as I 01 , so that the center of the amplitude of the address signal at the base of the transistor such as Q 02 conforms to the reference potential such as V ref0 , thereby improving the operation of the address buffers.
  • the circuits on the circuit side of reference potential V ref0 through V ref7 have the same configuration as the circuits on the circuit side of the address signals.
  • transistors Q 01 ' through Q 71 ', diodes D 01 ' through D 71 ', and constant current sources I 0 ' through I 71 ' corresponding to the transistors Q 01 through Q 71 , the diodes D 01 through D 71 and the constant current sources I 01 through I 71 are provided for the reference potentials V ref0 through V ref7 .
  • a reference potential V R ⁇ (-1.3 V) is applied to the bases of the emitter followers Q 01 , through Q 71 '.
  • the current value of the constant current source such as I 01 ' on the circuit side of the reference potential be the same as the current value of the corresponding constant current source I 01 on the address signal circuit side.
  • the fluctuation in the base-emitter voltage V BE of each of the emitter followers Q 01 through Q 71 is the same as the fluctuation in the base-emitter voltage V BE of each of the emitter followers Q 01 ' through Q 71 ', and as a result, the fluctuation in the comparison operation between the base potential of the transistor such as Q 02 and the base potential of the transistor such as Q 03 is eliminated.
  • the number of diode stages such as D 01 ', . . ., and D 71 ' is increased or decreased as occasion demands.
  • an address signal is used as an input signal.
  • the present invention can be applied to various signals (external clock signals) other than address signals.
  • the reduction in signal level due to the long connection line can be avoided, and in addition, the reduction in access time can be avoided.

Abstract

In a semiconductor device including a plurality of input signal pads (P0, . . . , P7); a plurality of emitter followers (Q01, . . . , Q71) are connected to the input signal pads (P0, . . . , P7); a plurality of input signal buffers (BUF0, . . . , BUF7) are connected to the emitter followers (Q01, . . . , Q71); and a plurality of constant current sources (I01, . . . , I71) are connected to the emitter followers (Q01, . . . , Q71). The emitter followers (Q01, . . . , Q71) are in proximity to the input signal pads (P0, . . . , P7), and the constant current sources (I0, . . . , I7) are in proximity to the emitter followers (Q01, . . . , Q71) . The current values of the constant current sources (I01, . . . , I71 ) are determined in accordance with the length of the corresponding connections between the emitter followers (Q01, . . . , Q71) and the input signal buffers (BUF0, . . . , BUF7).

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to the improvement of a signal input portion of an emitter-coupled logic (ECL) integrated circuit.
2 Description of the Related Art
The chip area of an advanced ECL integrated circuit is often increased, and therefore, some connection lines between a plurality of input signal pads and a plurality of input signal buffers such as address buffers become long. Consequently, if the distance between an input signal pad and an emitter follower transistor used as a signal input portion is large, for example, the input capacitance of an input signal is increased due to the parasitic capacitance of a long connection therebetween, thus increasing the access time.
To avoid this, in the prior art only the emitter follower transistor of the signal input portion is in proximity to the input signal pad, while a current source of the signal input portion is left on the circuit side of the input signal buffer, thereby reducing the input capacitance for an input signal. In this case, however, if the current flowing through the emitter follower is increased, the potential fall due to the resistance of signal paths is large so that the post input stage circuits may not operate normally. Contrary to this, if the current flowing through the emitter follower is decreased, the propagation speed of the input signal level becomes large due to the parasitic capacitance, thereby reducing the access time. Thus, in this case, it is impossible to satisfy the two conditions regarding the potential fall and the propagation speed of the signal level.
SUMMARY OF THE INVENTION
An object of the present invention is to minimize the potential fall of signal level due to the resistance of the signal path in a long connection line, and to minimize the delay in the access time.
According to the present invention, a constant current source is provided in proximity to the emitter follower and is connected thereto, and a current value of the constant current source is changed in accordance with connection line length, i.e., the parasitic capacitance between the emitter follower and the input signal buffer. That is, the larger the connection line length, the greater the current value of the constant current source.
Thus, since the current flowing through the connection line between the emitter follower and the input signal buffer is greatly reduced, reduction in potential due to the connection resistance is reduced, i.e., the reduction of a signal level is lessened. Also, since the current value of the constant current source is increased when the parasitic capacitance is large, the delay in the fall of the signal level is reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawings, wherein:
FIG. 1 is a partial layout diagram of a general semiconductor device;
FIGS. 2 and 3 are circuit diagrams showing prior art semiconductor devices;
FIG. 4 is a timing diagram showing the operation of the circuit of FIG. 3;
FIG. 5 is a circuit diagram illustrating an embodiment of the semiconductor device according to the present invention;
FIGS. 6A and 6B are circuit diagrams of the constant current sources Iil of FIG. 5;
FIGS. 7A, 7B, 8A and 8B are layout diagrams of FIGS. 6A and 6B; and
FIG. 9 is a circuit diagram illustrating a second embodiment of the semiconductor device according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In FIG. 1, which illustrates a general semiconductor device such as an ECL memory device, a plurality of pads P1 through P7 are connected via connection lines or conductor L0 through L7 to a signal input portion such as address buffers BUF. As the integration of the device is advanced or increased to reduce the size of the address buffers BUF, some of the connection lines L0 through L7 become long. For example, in FIG. 1, the connection line L0 between the pad P0 and the address buffers BUF is relatively short, but the connection line L7 between the pad P7 and the address buffers BUF is very long. Note that the signal input portion includes emitter followers, diodes, current sources, and the like, other than the address buffers BUF.
The device of FIG. 1 will be explained in detail with reference to FIGS. 2 and 3.
In FIG. 2, emitter followers Q01, . . ., and Q71, diodes D01, . . ., and D71, and constant current sources I01, . . ., and I71 are linked between the pads P0, . . ., and P7, and the address buffers BUF0, . . ., and BUF7. Each of the address buffers BUF0, . . ., and BUF7 has the same configuration. For example, the address buffer BUF0 comprises two transistors Q02 and Q03, and a constant current source I02, to form a current switch. Note that the diode D01 serves as a level shift means so that the center of the input amplitude of a signal applied to the base of the transistor Q02 conforms to a reference potential Vref0 applied to the base of the transistor Q03, thereby improving the operation speed of the address buffers. For example, if the center of the input amplitude of the signal applied to the base of the transistor Q02 is too high as compared with the reference potential Vref0, i.e., if the high level of the signal applied to the base of the transistor Q02 is too high as compared with the reference potential Vref0, the change of the output signal A0 from high to low is delayed as compared with the change of the output signal A0 from low to high. This delay is reduced by the diode D0. However, note that the number of such diode stages may be increased or decreased as occasion demands. Also, VEE designates a power supply voltage such as -5 V.
In FIG. 2, the distance between the pad P1 and the emitter follower Q01 is relatively small, and accordingly, the input capacitance encountered by an address signal applied to the pad P1 is small due to the parasitic capacitance Cp0 of the short connection line L0, thus reducing the access time. On the other hand, the distance between the pad P7 and the emitter follower Q171 is relatively long, and accordingly, the input capacitance of an address signal applied to the pad P7 is large due to the parasitic capacitance CP7 of the long connection line L7, thus increasing the access time.
In order to reduce the input capacitance for an address signal, in FIG. 3, the emitter followers Q01, . . ., and Q71 are provided in proximity to the pads P0, . . ., and P7, respectively, and are connected thereto. That is, in this case, the input capacitance at the post input stage of each of the pads P0 , ..., and P7 is reduced by 1/β (β represents the current amplification factor of the emitter follower such as Q01)
In FIG. 3, however, when the emitter current of the emitter follower Q71, i.e., the current I71 is increased, the reduction in potential due to the resistance of the connection line L7 is large since the connection L7 is long, and as a result, the signal level is greatly reduced so that the post-stage circuit which, in this case, is the address buffer BUF7 does not operate normally. Contrary to this, when the emitter current I71 of the emitter follower Q71 is small, the fall at the signal level is slow due to the parasitic capacitance CP7 as shown in FIG. 4, thereby increasing the access time.
In FIG. 5, which illustrates an embodiment of the semiconductor device according to the present invention, the constant current sources I01 through I71 are provided in proximity to the emitter followers Q01 through Q71, respectively. As a result, since a current required for driving the address buffer such as BUF0, . . ., and BUF7 is small, the current values of the constant current sources can be reduced even when the length of the connections lines L0 through L7 is large. Even in this case, however, the access time is dependent upon the length of the connection lines L0 through L7 which should be charged or discharged. Therefore, the current values of the constant current sources I01 through I71 are determined in accordance with the length of the connection lines L0 through L7 , i.e., the parasitic capacitances CP0 through CP7, respectively. That is, the ability of the emitter followers Q01 through Q71 to charge the lines are changed in accordance with the parasitic capacitances CP0 through CP7. For example, when the length of the connection line such as L0 is small, the current value of the constant current source I01 is small, and when the length of the connection line such as L7 is large, the constant current source I07 is large.
As shown in FIG. 6A, the constant current source I01 is comprised of a transistor QR having a base to which a definite voltage VRB is applied, and a resistor R. Also, as shown in FIG. 6B, the constant current source I71 is comprised of a transistor QR having a base to which the definite voltage VRB is applied, and five resistors R. That is, the current value of the constant current source is determined in accordance with the number of resistors R. For example, as shown in FIGS. 7A and 7B, the number of resistors R is substantially determined by the number to contacts of the resistors R. Also, as shown in FIGS. 8A and 8B, the number of resistors R can be determined by changing the connection pattern of the transistor QIR and the resistors R.
In FIG. 5, the current values of the constant current sources I01 through I71 are changed in accordance with the parasitic capacitances CP0 through CP7, respectively. This change of the current values of the constant current sources slightly affects the base-emitter voltage VBE of the emitter followers Q01 through Q71. As a result, the high and low levels of an address signal at the base of the transistor Q02 (or Q72) are slightly changed, and accordingly, the center of the amplitude of the address signal at the base of the transistor Q02 (or Q72) is shifted from the reference potential Vref0 (or Vref7).
In FIG. 9, which illustrates another embodiment of the semiconductor device according to the present invention, the reference potential such as Vref0 is changed in accordance with the current value of the constant current source such as I01, so that the center of the amplitude of the address signal at the base of the transistor such as Q02 conforms to the reference potential such as Vref0, thereby improving the operation of the address buffers. For this purpose, the circuits on the circuit side of reference potential Vref0 through Vref7 have the same configuration as the circuits on the circuit side of the address signals. That is, transistors Q01 ' through Q71 ', diodes D01 ' through D71 ', and constant current sources I0 ' through I71 ' corresponding to the transistors Q01 through Q71, the diodes D01 through D71 and the constant current sources I01 through I71 are provided for the reference potentials Vref0 through Vref7. Also, a reference potential VRφ (-1.3 V) is applied to the bases of the emitter followers Q01, through Q71 '. Herem it is important that the current value of the constant current source such as I01 ' on the circuit side of the reference potential be the same as the current value of the corresponding constant current source I01 on the address signal circuit side. Thus, the fluctuation in the base-emitter voltage VBE of each of the emitter followers Q01 through Q71 is the same as the fluctuation in the base-emitter voltage VBE of each of the emitter followers Q01 ' through Q71 ', and as a result, the fluctuation in the comparison operation between the base potential of the transistor such as Q02 and the base potential of the transistor such as Q03 is eliminated.
Also, in FIG. 9, the number of diode stages such as D01 ', . . ., and D71 ' is increased or decreased as occasion demands.
Note that, in the above-mentioned embodiments, an address signal is used as an input signal. However, the present invention can be applied to various signals (external clock signals) other than address signals.
As explained above, according to the present invention, the reduction in signal level due to the long connection line can be avoided, and in addition, the reduction in access time can be avoided.

Claims (7)

We claim:
1. A semiconductor device, comprising:
a plurality of input signal pads;
a plurality of emitter follower transistors for receiving input signals, each provided in proximity to one of said input signal pads and connected thereto, and having an output;
a plurality of input signal buffers;
a plurality of connection lines each linked between the output of one of said emitter follower transistors and one of said input signal buffers and each having a length; and
a plurality of constant current sources, each provided in proximity to one of said emitter foller transistors and connected thereto, the current values provided by said constant current sources being determined in accordance with the length of the corresponding connection lines, so that the current values of said constant current sources become larger as the corresponding connection lines become longer.
2. A device as set forth in claim 1, further comprising comparison reference potential adjusting means for adjsuting comparison reference potentials applied to said input signal buffers in accordance with the current values provided by said constant current sources, thereby substantially setting the center of the amplitude of signals applied to said input signal buffers at the corresponding comparison reference potentials, said input signal buffers comprising gates having threshold voltages determined by the corresponding comparison reference potentials.
3. A device as set forth in claim 2, wherein said comparison reference potential adjusting means comprises:
a plurality of reference emitter follower transistors, connected to corresponding input signal buffers, for receiving a reference potential; and
a plurality of reference constant current sources, each connected to corresponding reference emitter follower transistors and having the same current value as the corresponding one of said constant current sources.
4. A device as set forth in claim 1, further comprising a plurality of level shift means coupled between corresponding said emitter follower transistors and said constant current sources.
5. A device as set forth in claim 3, wherein each of said constant current sources comprises:
a source transistor, connected to corresponding emitter follower transistor, for receiving a reference potential; and
a plurality of resistors in parallel, connected to said source transistor, the number of said resistors determining the current value of said constant current sources.
6. A semiconductor device, comprising:
input signal buffers;
conductors of different lengths connected to corresponding input signal buffers and each conductor having a buffer end and an input pad end;
input pads;
current supply means, connected between respective input pads and conductors, for providing current to said conductors in dependence on length, each current supply means comprising:
an emitter follower transistor connected between a corresponding input pad and the input pad end of a corresponding conductor; and
a constant current source connected to the input pad end of the corresponding conductor and providing current with a magnitude in dependence on conductor length.
7. A device as set forth in claim 6, wherein said constant current source comprises:
a source transistor connected to the input pad end of said conductor;
a resistor connected to said source transistor having a resistance dependent on conductor length.
US06/813,941 1984-12-28 1985-12-27 IC input buffer emitter follower with current source value dependent upon connection length for equalizing signal delay Expired - Lifetime US4675555A (en)

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JP59274560A JPH0656876B2 (en) 1984-12-28 1984-12-28 Semiconductor device
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US6198309B1 (en) 1999-03-31 2001-03-06 Applied Micro Circuits Corporation Emitter follower output with programmable current
US6300802B1 (en) 1999-02-19 2001-10-09 Applied Micro Circuits Corporation Output buffer with programmable voltage swing

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US4812684A (en) * 1987-02-23 1989-03-14 Hitachi, Ltd. Multiphase clock distribution for VLSI chip
US5467043A (en) * 1993-02-01 1995-11-14 Nec Corporation Signal level converting circuit for liquid crystal display device receiving analog color signal
US5376830A (en) * 1993-09-17 1994-12-27 International Business Machines Corporation High frequency slope compensation circuit for current programmed converter
US5521809A (en) * 1993-09-17 1996-05-28 International Business Machines Corporation Current share circuit for DC to DC converters
US5563540A (en) * 1993-09-17 1996-10-08 International Business Machines Corporation Electronic switch having programmable means to reduce noise coupling
US6300802B1 (en) 1999-02-19 2001-10-09 Applied Micro Circuits Corporation Output buffer with programmable voltage swing
US6198309B1 (en) 1999-03-31 2001-03-06 Applied Micro Circuits Corporation Emitter follower output with programmable current

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KR900006317B1 (en) 1990-08-28
EP0192907B1 (en) 1989-09-20
EP0192907A1 (en) 1986-09-03
JPS61156762A (en) 1986-07-16
DE3573196D1 (en) 1989-10-26
JPH0656876B2 (en) 1994-07-27
KR860005442A (en) 1986-07-23

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