US4672412A - High fill-factor ac-coupled x-y addressable Schottky photodiode array - Google Patents
High fill-factor ac-coupled x-y addressable Schottky photodiode array Download PDFInfo
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14649—Infrared imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H01L27/14862—CID imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14875—Infrared CCD or CID imagers
Definitions
- the present invention relates to Schottky barrier infrared imaging arrays and, more particularly, to such arrays having increased fill-factor and capable of X-Y addressable readout.
- a single cell or picture element (pixel) of such an array e.g., comprises a Schottky photodiode including a thin (e.g., 100 angstrom) layer of a metal silicide such as platinum silicide (PtSi) or palladium silicide (PdSi) formed on a semiconductor substrate.
- a metal silicide such as platinum silicide (PtSi) or palladium silicide (PdSi) formed on a semiconductor substrate.
- PtSi platinum silicide
- PdSi palladium silicide
- the diode is reverse biased, defining in the semiconductor material underneath the Schottky metal electrode a depletion region wherein majority carriers (i.e., holes) are depleted and a positive charge appears on the Schottky metal electrode.
- majority carriers i.e., holes
- Infrared photons striking the Schottky metal electrode generate electronhole pairs and the excited holes cross the Schottky barrier (having a barrier height represented by ⁇ SB ) into the silicon.
- the photodiode is thus, in effect, discharged as the depletion region decreases in volume and the excess positive charges on the Schottky metal electrode decrease in number.
- Schottky photodiode arrays have a number of inherent advantages and unique characteristics compared to other types of infrared imagers such as metal-insulator-semiconductor (MIS) capacitors or ordinary junction diodes.
- MIS metal-insulator-semiconductor
- One fundamental advantage is that it is much easier to achieve response to infrared radiation (e.g., wavelength in the range of 3 to 10 microns) while still employing silicon integrated circuit fabrication processes which are well developed in the art. This advantage arises from the fact that the spectral response is determined primarily by the physics of the barrier transition process and not by the photoabsorption process.
- the cut-off wavelength, in microns is a function of the Schottky barrier height ⁇ SB in accordance with the expression (1.24/ ⁇ SB ), where ⁇ SB is in electron volts.
- Barrier height, and thus spectral response, can be determined through such design choices as the particular metal employed and the semiconductor conductivity type.
- the cut-off wavelength, in microns is determined in accordance with the expression (1.24/E g ), where E g is the bandgap in electron volts.
- Silicon devices respond to visible wavelength photons, e.g., having a wavelength in the order of 0.7 microns.
- semiconductor-type imaging devices e.g., MIS
- more exotic semiconductor materials must be employed, such as InSb or HgCdTe.
- Schottky barrier photodiodes when employed in arrays is that crosstalk between adjacent pixels inherently is substantially nonexistent and channel isolation between adjacent pixels is not required. This characteristic arises from the fact that the electrons, which represent the signal generated by the incident radiation, remain in the Schottky metal electrode so that the location of the electrons is well-defined.
- Schottky diode photodetectors have not heretofore been fully realized in arrays.
- Schottky photodiode arrays have previously been read out employing such elements as transfer gates and various forms of charge coupled devices (CCD's).
- CCD's charge coupled devices
- the CCD's are typically arranged in shift-register fashion to serialize readout data from an entire row or column of the photodiode array.
- the presence of these additional elements for reading out the Schottky photodiodes makes somewhat less than 30% of the chip area available for photon detection. This factor, referred to in the art as the "fill-factor", is the ratio of actual detection area to the total chip area occupied by the array.
- a Schottky photodiode has relatively low quantum efficiency, and it is important for this reason also to use efficiently all the area available.
- a conflicting requirement with a CCD readout is that the CCD must be made large enough to handle the high infrared background charge often encountered.
- a buried channel CCD is normally preferred.
- the low charge handling capacity of the buried channel CCD requires a larger area of the silicon chip and hence reduces the fill-factor.
- Schottky barrier infrared detector arrays are disclosed in the following documents: Roosild et al., U.S. Pat. No. 3,902,066; B. R. Capone et al., "Design and Characterization of A Schottky Infrared Charge-Coupled Device (IRCCD) Focal Plane Array", SPIE vol. 267--Staring Infrared Focal Plane Technology, pp. 39-45 (1981); M. Kimata et al., “Platinum Silicide Schottky-Barrier IR-CCD Image Sensors", Proceedings of the 13th Conference on Solid State Devices, Tokyo, 1981; Japanese Journal of Applied Physics, vol. 21 (1982), Supplement 21-1, pp. 231-235; and M. Cantella et al., "Solid State Focal Plane Arrays Boost IR Sensor Capabilities", Military Electronics/Countermeasures, September 1982, pp. 38-42.
- the two MIS capacitors are coupled together so that stored charge can be transferred from one capacitor to the other.
- Michon U.S. Pat. No. 3,786,263, and Michon et al.
- U.S. Pat. No. 3,085,062 both assigned to the instant assignee.
- one object of the invention is to provide a high resolution two-dimensional solid-state infrared imaging array.
- Another object is to provide a Schottky diode infrared imaging array fabricated on a silicon substrate.
- Another object is to provide a highly sensitive infrared imaging array with virtually no inherent crosstalk or lag.
- Another object is to provide a Schottky diode two-dimensional imaging array capable of high resolution readout without charge coupled devices.
- Another object is to provide a Schottky photodiode array with a high fill factor.
- a two-dimensional Schottky barrier infrared detector array comprises a semiconductor substrate of, for example, P-conductivity type silicon. A plurality of unit cells are formed on the substrate and arranged in a two-dimensional pattern of rows and columns.
- Each of the unit cells in turn includes a photosensitive Schottky barrier metal electrode formed on the semiconductor substrate defining a Schottky junction therewith, and a pair of readout electrodes, namely, a row electrode and a column electrode, electrically insulated from the Schottky electrode and capacitively coupled thereto.
- the overall array includes a set of row address lines, each corresponding to a row of unit cells and connected to the row electrodes of the unit cells of the corresponding row, and a set of column address lines, each corresponding to a column electrode of the unit cells of the corresponding column.
- a "half-select" correlated double sampling technique can be employed to effectively read out this array.
- the readout electrodes and address lines are physically arranged to significantly reduce stray capacitance, thereby increasing signal-to-noise ratio and descreasing pattern noise. (Undesirable pattern noise is normally evidenced by nonuniform readout in the presence of a uniformly black image.)
- the row and column electrodes are concentrically arranged so that, for example, the row electrode surrounds the column electrode.
- the one electrode in this example, the row electrode
- the two electrodes, i.e., the row and column electrodes are substantially coplanar at a first level above the Schottky metal electrode, being spaced from the Schottky metal electrode by an insulating layer.
- each line of one of the address line sets (i.e., each row address line) comprises separate line segments, each segment extending between adjacent electrode portions of correspondingly adjacent unit cells. These line segments are electrically connected to the electrode portions through contact windows in the address line insulating layer.
- Each line of the other of the address line sets (i.e., each column address line) extends across a plurality of unit cells through the gaps between the line segments of the one set.
- Each column address line is connected through contact windows in the address line insulating layer to the column electrodes of the underlying unit cells.
- the address lines introduce relatively low stray capacitance and there is very low overlap capacitance between the row and column lines and the electrodes.
- there is no overlap capacitance between the electrodes themselves and the only overlap capacitance in the entire array is between the column address lines and the relatively narrow portions of the row electrodes bridging the opposed electrode portions.
- a relatively thick layer of insulation for example a 10,000 angstrom SiO 2 layer, minimizes even this capacitance.
- a method of operating a Schottky photodiode having a Schottky metal barrier electrode formed on a semiconductor substrate and defining a Schottky junction therewith includes the steps of capacitively coupling to the Schottky electrode a voltage pulse of magnitude and polarity appropriate to reverse bias the photodiode with a charge quantity therein. Thereafter, the magnitude of charge remaining in the photodiode is determined at the end of the sensing and integration interval by capacitively coupling a signal from the Schottky electrode.
- FIG. 1A is a cross-sectional representation of a pair of adjacent capacitively-coupled Schottky photodiodes depicting operation before photon detection;
- FIG. 1B is a cross-sectional representation of the two photodiodes of FIG. lA during photon detection;
- FIG. 2 depicts the operation of the two photodiodes of FIG. 1A during a pulsed charging operation, or reset operation;
- FIG. 3 is a cross-sectional representation of a single unit cell of a two-dimensional Schottky barrier infrared detector array
- FIG. 4 is a plan view taken generally along lines 4--4 of FIG. 3 representing metal portions of the FIG. 3 cell;
- FIG. 5 is a view similar to FIG. 4 depicting a plurality of unit cells arranged in a two-dimensional pattern of rows and columns;
- FIG. 6 is an electrical schematic diagram depicting an array such as shown in FIG. 5 and illustrating readout circuitry therefor.
- FIGS. 1A, 1B and 2 depict in highly-schematic fashion the operation of two capacitively-coupled Schottky photodiodes 10 and 12. Each of FIGS. 1A, 1B and 2 is additionally employed to illustrate certain advantages of such Schottky photodiodes compared to charge injection devices (CID's) and capacitor-coupled junction diodes.
- CID's charge injection devices
- a P-conductivity silicon semiconductor substrate 14 has formed thereon a pair of Schottky metal barrier electrodes 16 and 18 defining Schottky junctions with semiconductor substrate 14.
- Schottky electrodes 16 and 18 comprise the diode cathodes and semiconductor substrate 14 comprises a common diode anode connected to a circuit reference point as schematically depicted at 20.
- Photodiodes 10 and 12 also include respective readout electrodes 22 and 24 capacitively coupled to corresponding Schottky metal electrodes 16 and 18.
- electrodes 22 and 24, as depicted in FIG. 1A, are nominally at zero volts, although any initial bias voltage may be applied as, e.g., to control the surface potential of the substrate.
- diodes 10 and 12 are each reverse biased, and respective depletion regions 26 and 28 are formed.
- majority carriers holes in this case of the P-conductivity semiconductor substrate 14
- excess positive charge is contained within the Schottky metal electrodes 16 and 18.
- this excess positive charge is omitted in FIGS. 1A, 1B and 2.
- electrons 32 which reflect the quantity of incident radiation 30, are as a result of the absorption of incident radiation 30, in well-defined locations, namely, within Schottky metal electrodes 16 and 18.
- depletion regions 26 and 28 were to overlap, adjacent pixels are not short-circuited. This is a direct consequence of the incapability of holes to escape from the Schottky electrode without a supply of external energy in the form of photons, for example.
- the signal charge integrated in photodiodes 10 and 12 is then capacitively sensed by use of capacitive coupling between readout electrodes 22 and 24, respectively, and Schottky electrodes 16 and 18, respectively.
- This sensing technique is depicted in FIG. 2.
- a negative voltage pulse e.g., -5 volts
- Holes 34 then rapidly return to Schottky electrodes 16 and 18 to recombine with electrons 32. Since recombination occurs nearly instantaneously in the metal (i.e., within a few nanoseconds), lag is virtually nonexistent.
- photodiodes 10 and 12 can again be charged for another integration interval with assurance that signal generated during one sensing interval does not substantially affect a subsequent sensing interval.
- the absence of crosstalk is also evident.
- the readout electrodes 22 and 24 are reset to 0 volts to establish the initial potential on the Schottky electrodes 16 and 18 as shown in FIG. 1A.
- the voltage changes on readout electrodes 22 and 24 between the FIG. 1A and FIG. 1B conditions provide the signal voltages for Schottky electrodes 16 and 18, respectively.
- a capacitively coupled junction photodiode such as has been suggested in the prior art, may be visualized by replacing Schottky metal electrodes 16 and 18 with highly-doped N-conductivity type cathode regions (N + cathodes).
- N + cathodes highly-doped N-conductivity type cathode regions
- electron current flows out of the N + cathode, i.e., is injected into the substrate. Since it is electrons which flow during reset, the device may be considered a minority carrier device inasmuch as electrons are minority carriers with respect to the P-conductivity type substrate.
- Schottky photodiodes 10 and 12 may be considered majority carrier devices inasmuch as the dominant carriers which flow during reset are holes, which are the majority carriers with respect to underlying substrate 14.
- the injected electrons may be recollected in a subsequent readout cycle, resulting in substantial lag, or migrate to neighboring pixels, resulting in significant crosstalk.
- An MIS capacitor charge-injection device may be visualized by entirely omitting Schottky metal electrodes 16 and 18.
- the charge-injection device operates substantially identically to a capacitively-coupled junction diode except that, in place of the defined N + cathode region, an N-conductivity type inversion layer is formed adjacent the semiconductive surface. During reset, electrons from this inversion layer are injected into the substrate.
- MIS charge-injection devices are minority carrier readout devices with corresponding lag and crosstalk problems.
- FIGS. 3 and 4 are enlarged views of a single Schottky photodiode unit cell 40, while FIG. 5 depicts a portion of a two-dimensional array of such unit cells.
- Each unit cell or sensing site has an exemplary size of 43 by 43 midrometers and, as will be appreciated from FIGS. 4 and 5, the fill-factor is relatively high because the sensing area and readout area are substantially overlapped.
- unit cell 40 is formed on a P-conductivity type silicon semiconductor substrate 42, common to all the other unit cells and comprising a photodiode common anode.
- Substrate 42 is connected to a circuit reference point as depicted at 44.
- a film-like photosensitive Schottky barrier metal electrode 46 is formed on semiconductor substrate 42 and defines a Schottky junction therewith.
- This Schottky electrode 46 which also may be viewed as defining a sensing site, preferably comprises platinum silicide (PtSi).
- Schottky metal electrode 46 may be formed by initially depositing a platinum film at cold substrate temperature (less than 100° C. employing an electron beam evaporation technique. Masking during this deposition process is provided by a window 48 in a silicon oxide (SiO 2 ) layer 49. The platinum film is then converted into platinum silicide by annealing at a temperature in the range of 350° C. to 650° C. In order to provide a more uniform platinum silicide film, the conventional process for forming the film may be improved by depositing platinum on a hot (in the order of 600° C.) substrate to yield a more nearly continuous and singlephase platinum silicide film.
- silicon nitride (Si 3 N 4 ) insulating layer 50 is formed directly over platinum silicide film 46.
- the thickness of silicon nitride layer 50 is chosen for an optimized noise and saturation charge, and is in the order of from 2,000 to 10,000 angstroms. Silicon nitride has the advantages of low pinhole density and excellent radiation hardness.
- Electrodes 52 and 54 are substantially coplanar at a first level above Schottky metal 46, as shown in FIG. 3. Electrodes 52 and 54 are concentrically arranged, as shown in FIG. 4, with row electrode 52, for example, comprising a pair of generally diametrically-opposed electrode portions 56 and 58, electrically interconnected by relatively narrow connecting portions 60 and 62. In addition, row electrode 52 extends beyond the platinum silicide sensing area 46 to serve as an MOS guard ring for raising the reverse breakdown voltage of the photodiode by smoothing out the depletion layer edge curvature. This extension is in the order of one micrometer.
- Insulating layer 64 is formed over the row and column electrodes 52 and 54.
- Insulating layer 64 may comprise silicon oxide (SiO 2 ) of thickness in the order of 10,000 angstroms.
- Row and column address lines 66 and 68 are formed over insulating layer 64 substantially coplanar at a second level above Schottky electrode 46 and spaced from row and column electrodes 52 and 54 by insulating layer 64.
- Each line of one of the address line sets for example row address line 66, comprises a plurality of segments, such as segments 70 and 72, as shown in FIG. 4, extending between adjacent electrode portions of corresponding adjacent unit cells 40, as may be seen in FIG. 5. Gaps are thus defined between line segment ends 73 and 74, as shown in FIG. 4. Row address line segments 70 and 72 are electrically connected to row electrode portions 56 and 58, respectively, through contact windows 76 and 78, respectively, in address line insulating layer 64 via metal extensions 80 and 82, respectively.
- Each line of the other address line sets such as column line 68, extends across a plurality of unit cells through the gaps between row line segments 70 and 72.
- Column line 68 is electrically connected through a contact window 84 to column electrode 54 via a metalized extension 86.
- the structure thus described provides relatively low address line stray capacitance and relatively low overlap capacitance, both of which are at least an order of magnitude less than in conventional electrode designs.
- the address line insulating layer 64 is relatively thick, for minimal capacitance.
- the only address line overlap occurs at points 88 (FIG. 4) where column address line 68 overlaps row electrode connecting portions 60 and 62.
- connecting portions 60 and 62 are relatively narrow, and the insulation layer 64 is relatively thick.
- FIG. 6 is an equivalent electrical schematic diagram representing the FIG. 5 array and depicting the manner in which the individual unit cells are connected for readout.
- the photodiode common anode is represented at 42
- individual photodiode cathodes are represented at 46a-46d.
- Row readout electrodes 52a-52d, respectively are capacitively coupled to respective Schottky electrodes 46a-46d
- column readout electrodes 54a-54d are capacitively coupled to respective Schottky metal electrodes 46a-46d.
- a representative row address line 90 is connected to both row electrodes 52a and 52b of the corresponding row and, through gating transistors 92 and 94, to a row drive line 96 and an output line 98, respectively.
- Another representative row address line 100 is connected to row address electrodes 52c and 52d of another row and, through gating transistors 102 and 104, to row drive line 96 and output line 98, respectively.
- Gating transistors 92, 94, 102 and 104 are activated by conventional vertical scanning circuitry 106.
- a representative column address line 108 is connected to column address electrodes 54a and 54c of the corresponding column and, through a gating transistor 110, to a column bias line 112, and through a gating transistor 111 to a column read line 113.
- Another representative column address line 114 is connected to column electrodes 54b and 54d and, through a gating transistor 116, to column bias line 112, and through a gating transistor 117 to column read line 113.
- Horizontal scanning circuitry 118 selectively activates gating transistors 110, 111, 116 and 117.
- Output line 98 is connected through a voltage amplifier 122 to a correlated double voltage sampling network comprising capacitors C 1 and C 2 , and switches S 1 and S 2 .
- a selected pixel is initially reset by applying a negative pulse by switching on the corresponding row and column read lines simultaneously.
- the selected pixel is forward biased to a potential of the order of -0.2 volt and all excess electrons and holes within the Schottky electrode of the selected pixel recombine.
- the sensing operation begins following the reset/read pulse when the photodiode cathode is reverse biased.
- a depletion region underneath the Schottky electrode of the selected pixel is formed wherein majority carriers (holes) are depleted. Excess positive charges are created in the Schottky electrode of the selected pixel.
- infrared photons absorbed in the Schottky metal cathode of the selected pixel cause generation of electron-hole pairs as described previously.
- the photodiode depletion region decreases in volume and the excess positive charges on the Schottky metal cathode decrease in number.
- the selected pixel is, in effect, discharged by an amount ⁇ q dependent upon the quantity of infrared photons striking the selected pixel.
- readout begins. Reset, sensing, integration and readout proceeds for all the pixels sequentially row-by-row, and column-by-column within each row. When the last pixel is read, the sequence is immediately repeated. Since each pixel is reset when it is read out, the integration time for all pixels is the same and equal to the frame time.
- a first row is selected for readout at the end of its one frame time of integration.
- the row capacitors 52a and 52b in the selected row are coupled through transistors 94 and 120 to the row read potential, e.g., -5 volts, and then allowed to float by opening transistor 120.
- Each pixel along the selected row is only "half-selected” because only one of the two electrodes capacitively coupled to the single Schottky metal electrode is driven to -5 volts, reducing the potential on the Schottky metal electrodes 46a and 46b by an amount of +V 1 /2.
- V r on each sensing site within the selected row then reduces to: ##EQU1## where ⁇ q is the integrated signal charge and C p is the total capacitance for each pixel. It is assumed here that for each pixel the row gate capacitance and column gate capacitance are equal. However, this is only for illustration and in practice need not be the case. Due to the half-select operation, the saturation value ⁇ q max for each pixel is given by: ##EQU2## Note that no signal charge is removed from the Schottky electrodes 46a and 46b during the "half-select" operation as long as the integrated signal charge does not exceed ⁇ q max .
- correlated double voltage sampling is used to read out each pixel of the selected row, column-by-column.
- the first sample of output line 98 voltage is taken across capacitor C 1 by momentarily closing switch S 1 .
- the first column is then pulsed negatively and brought back to its bias potential by horizontal scanner 118. This can be done by momentarily opening transistor switch 111 and closing transistor switch 110.
- Schottky photodiode readout electrodes 54a, 54c are at the more negative potential, the selected Schottky photodiode 46a is forward biased and the integrated charge on the Schottky electrode 54a thereof is removed via a recombination procedure as described previously.
- Correlated double sampling is again used to read out the accumulated change in charge on the Schottky electrode 46b of the next selected pixel.
- No signal charge is removed from the Schottky electrodes 46c and 46d in the unselected row when the column electrodes 54c and 54d are pulsed to ground potential since the unselected row electrodes 52c and 52d are at a positive potential +V 1 /2 All columns along the row are read out although this need not be the case for random access.
- transistor 94 connecting the row to the output line is opened and transistor 92 is closed connecting the row to the row bias terminal.
- the next row e.g. 100 is then chosen and read out. This continues for all rows and columns.
- the row bias and column bias are nominally at 0 volts. In actual operation, as described hereinbefore, they can be at any d.c. potential with the column read and row read potentials being more negative, e.g. 5 volts, than the column and row bias potentials, respectively.
- the photocurrent effect more specifically is a crosstalk effect due to the addition of photocharge into sites other than the chosen site while the chosen site is being read out.
- a heavy (greater than 100 times) overload in a pixel which has just been read out (i.e., already cleared and now integrating) may lead to a darkened streak in the image.
- the preferred embodiment described above utilizes concentric, planar row and column gates and planar row and column address lines. It is to be understood, however, that side-by-side row/column gates (nonconcentric), either planar or non-planar, and address lines at different levels (non-planar), or other such geometrical variations, can be adopted and still maintain the beneficial results described herein.
Abstract
Description
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US4857979A (en) * | 1988-06-20 | 1989-08-15 | Ford Aerospace & Communications Corporation | Platinum silicide imager |
US5134488A (en) * | 1990-12-28 | 1992-07-28 | David Sarnoff Research Center, Inc. | X-Y addressable imager with variable integration |
US5134489A (en) * | 1990-12-28 | 1992-07-28 | David Sarnoff Research Center, Inc. | X-Y addressable solid state imager for low noise operation |
EP0572137A1 (en) * | 1992-05-27 | 1993-12-01 | Loral Fairchild Corporation | Charge skimming and variable integration time in focal plane arrays |
US5326996A (en) * | 1992-05-27 | 1994-07-05 | Loral Fairchild Corp. | Charge skimming and variable integration time in focal plane arrays |
US7425308B2 (en) * | 1993-11-01 | 2008-09-16 | Nanogen, Inc. | Systems for the active electronic control of biological reactions |
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US20010026935A1 (en) * | 1993-11-01 | 2001-10-04 | Nanogen, Inc. | Circuits for the control of output current in an electronic device for performing active biological operations |
US6798034B2 (en) * | 2000-04-20 | 2004-09-28 | Diglrad Corporation | Technique for suppression of edge current in semiconductor devices |
US20050173774A1 (en) * | 2000-04-20 | 2005-08-11 | Digirad Corporation, A Delaware Corporation | Technique for suppression of edge current in semiconductor devices |
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US20020185654A1 (en) * | 2000-04-20 | 2002-12-12 | Digirad Corporation, A Delaware Corporation | Technique for suppression of edge current in semiconductor devices |
US20020085107A1 (en) * | 2000-12-28 | 2002-07-04 | Chen Zhiliang Julian | Image sensor array readout for simplified image compression |
US6786411B2 (en) * | 2000-12-28 | 2004-09-07 | Texas Instruments Incorporated | Image sensor array readout for simplified image compression |
US20050221571A1 (en) * | 2004-03-30 | 2005-10-06 | Irwin Richard B | Dual metal schottky diode |
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GB2412787B (en) * | 2004-03-30 | 2009-03-18 | Texas Instruments Inc | Dual metal schottky diode |
US20110193138A1 (en) * | 2008-10-24 | 2011-08-11 | Advantest Corporation | Electronic device and manufacturing method |
US8614465B2 (en) * | 2008-10-24 | 2013-12-24 | Advantest Corporation | Electronic device and manufacturing method |
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