US4649416A - Microwave transistor package - Google Patents

Microwave transistor package Download PDF

Info

Publication number
US4649416A
US4649416A US06/567,829 US56782984A US4649416A US 4649416 A US4649416 A US 4649416A US 56782984 A US56782984 A US 56782984A US 4649416 A US4649416 A US 4649416A
Authority
US
United States
Prior art keywords
disposed
substrate
insulator
plate
compartment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US06/567,829
Inventor
Michael T. Borkowski
David G. Laighton
Barry Altschul
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Priority to US06/567,829 priority Critical patent/US4649416A/en
Assigned to RAYTHEON COMPANY reassignment RAYTHEON COMPANY ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: ALTSCHUL, BARRY, BORKOWSKI, MICHAEL T., LAIGHTON, DAVID G.
Priority to CA000471318A priority patent/CA1232083A/en
Application granted granted Critical
Publication of US4649416A publication Critical patent/US4649416A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01083—Bismuth [Bi]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching

Definitions

  • This invention relates generally to microwave transistor packages and method of manufacturing such packages and more particularly microwave transistor packages having low parasitic reactance and adapted to have packaged therein impedance matching circuitry for the packaged transistor.
  • a typical microwave transistor package includes a beryllia insulator to provide a low thermal resistance from the transistor die to the package heat sink base or header.
  • the upper and lower surfaces of the beryllia insulator have gold layers for attachment to the transistor die on the upper surface and for attachment to the header on the lower surface.
  • the header also serves as the ground plane conductor.
  • the transistor typically has its collector contact formed on the bottom of the die and hence, in those configurations, requiring a grounded, or common base configuration, it is necessary to electrically connect the base electrode, formed on the upper surface of the transistor die, to the header.
  • This connector is typically done with a wire lead and it is generally desirable to use relatively short leads in order to reduce the inductive reactance of such wire lead since such reactance becomes part of the input impedance to the transistor component.
  • One technique suggested to reduce the length of the lead and hence reduce its parasitic inductive reactance is to position the beryllia between a pair of conductive rails, as discussed in U.S. Pat. No. 3,784,884, issued Jan. 8, 1974, Demir S. Zoroglu, inventor.
  • bonding wires are used to connect the transistor to the grounded rails and the length of such wires is reduced by having the height of the grounded bonding rails approximately equal to the thickness of the beryllia insulator so that the bonding surface of the rail is almost even with the transistor die.
  • relatively expensive coined bonding rails are required in such package.
  • One technique suggested to remove the requirement for the coined bonding rails discussed in U.S. Pat. No. 4,784,884, referred to above, is to provide a copper header with a pedestal having a channel formed in the upper surface thereof into which the metallized beryllium insulator is positioned as discussed in U.S. Pat. No. 4,150,393, referred to above. Also included in the package discussed in the latter patent is a toroid shaped alumina ceramic insulator which encircles the sides of the pedestal portion of the header and which has lower surfaces which rest on the lower base portion of the header. The upper surface of the insulator support metallized conductive leads to the package.
  • the alumina insulator, conductive coated beryllia insulator and metal conductive leads are brazed together in one operation to form a single unit. It is first noted, however, that, as mentioned above, in high power devices the impedance matching network should be included within the package and with the relatively small package described above, while patentee suggests that surfaces of the pedestal can be utilized to have a MOS chip capacitor attached to it, if the size of the pedestal were increased to have sufficient surface area to accomodate impedance matching devices the toroid shaped ceramic insulator would tend to splinter during brazing of the ceramic insulator to the header, since mechanical stresses during brazing cause the insulator to splinter because of the great difference between the relatively low coefficient of thermal expansion of the ceramic insulator and the relatively high thermal coefficient of expansion of the copper header.
  • the cylindrical form of the package does not allow it to be readily used with more readily available circuitry which is designed to receive rectangular packages. Further, increasing the size of the pedestal header to accomplish the impedance matching devices tends to agravate the effect of the great difference between the thermal expansion properties of the header and the ceramic on the ceramic's tendency to splinter.
  • a microwave transistor package having: a thermal and electrical conductive refractory type substrate; a ground plane plate having an open-ended compartment therein, such open-end being disposed adjacent an upper surface portion of the ground plane plate, a bottom surface of such plate being disposed on an upper, inner surface region of the substrate; the thermal coefficient of expansion of the ground plane plate being substantially greater than the thermal coefficient of expansion of the substrate; an electrical insulator, disposed within the compartment having a relatively high thermal transfer characteristic and having upper and lower conductive layers with side wall portions disposed adjacent side wall portions of the compartment; a first apertured ceramic insulating layer having conductive metallization regions disposed on the upper surface of the ceramic insulator and extending from the apertured edge of the ceramic insulator to the outer edge of the ceramic insulator, the lower surface of the ceramic insulator being disposed over a surface portion of the substrate disposed about peripheral portions of the inner surface region of the substrate; a second apertured ceramic insulating layer disposed over and aligned with the
  • the package is fabricated by brazing together, in a single step, the pair of ceramic insulating layers, the electrical insulator (typically beryllia) and the substrate.
  • the substrate and the ceramic insulating layers have substantially the same, relatively low thermal coefficients of expansion, the ceramic insulating layers will not crack during the brazing step.
  • the ground plane plate is relatively thin and can be easily provided with a compartment for the beryllia and also be made large enough to accomodate an impedance matching device on the upper surface portion of the ground plane plate adjacent the compartment; the use of the compartment enabling the use of relatively short grounding wire leads from between the upper surface of the ground plane plate and the transistor die mounted to the upper, metallized surface of the beryllia.
  • FIG. 1 is an exploded, isometric drawing of a microwave transistor package according to the invention
  • FIG. 2 is a plan view of the microwave transistor package of FIG. 1;
  • FIG. 3 is a cross-section elevation view of the package of FIG. 1, such cross-section being taken along line 3--3 of FIG. 2;
  • FIG. 4 is a plan view of the microwave transistor package of FIG. 1 having packaged therein a transistor component and electrically interconnected impedance matching devices;
  • FIG. 5 is a cross-section elevation view of the package shown in FIG. 4, such cross-section being taken along line 5--5 of FIG. 4.
  • a microwave transistor package 10 is shown to include a rectangular planar, electrically and thermally conductive substrate 12, here an 0.042 inch thick slab of a refractory material, here sintered tungsten infiltrated with copper (here Thermkon material, a product of CMW, Inc., Indianapolis, Ind. having a relatively low thermal coefficient of expansion.
  • the outer dimensions of the substrate 12 are here 0.56 inches by 0.48 inches.
  • Disposed over the substrate 12 is a 0.020 inch thick copper buffer ring 14 having a relatively large aperture 16 flanked by a pair of smaller apertures 18a and 18b.
  • the ring 14 is disposed on, and aligned with, the outer edges of the substrate 12.
  • a relatively thin, here 0.040 inch thick copper ground plane plate 20 is fabricated by constructing a laminated structure made up of a lower copper sheet 22, here 0.020 inches thick, to which is soldered an upper copper sheet 24, here also 0.020 inches thick.
  • the upper sheet 24 has a pair of rectangular apertures 24a, 24b formed therein using conventional photolithographic chemical etching techniques. It is noted that the linear thermal coefficient of expansion of the copper plate 20 (19 microinches per inch per degree centigrade) is substantially greater than the linear thermal coefficient of expansion of the refractory substrate 12 (9.5 micro-inches per inch per degree centigrade).
  • the outer dimensions of the ground plane plate 20 are here 0.225 inches by 0.375 inches and are dimensioned to allow such plate 20 to fit into the larger aperture 16 formed in buffer ring 14.
  • each of the smaller apertures 24a, 24b are here 0.118 inches by 0.048 inches. It is noted that when the upper and lower sheets 22, 24 are soldered together, a pair of rectangularly shaped open-ended compartments 23a, 23b (FIG. 2) are formed with plate 20. Further disposed adjacent the pair of compartments 23a, 23b is a relatively large portion 25 of the upper surface of the ground plane plate 20 and, as will be discussed herein after, such surface portion 25 will be used for mounting impedance matching circuitry components.
  • a pair of electrically insulating bodies 28a, 28b having relatively high thermal transfer conductivity characteristics here 0.025 inch thick beryllia (BeO) (having a linear thermal coefficient of expansion of 9 micro-inches per inch per degree centigrade) coated on the upper and lower surfaces with molybdenum-manganese-gold conductive layers 32a, 32b, respectively as shown.
  • the bodies 28a, 28b are disposed within the compartments 23a, 23b, respectively. It is noted that since the compartments 23a, 23b are herein 0.020 inches deep, that the upper surfaces of the coated beryllia bodies 28a, 28b are substantially level, or even, with the upper surface of the ground plane plate 20.
  • the electrical contacts of such transistors may be electrically connected to ground in a common, or grounded base configuration, through the use of relatively short lead wires which extend from the base contacts to the upper surface region 25 of the ground plane plate 20 adjacent to the edges of the compartments 23a, 23b.
  • a laminated apertured, ceramic (here alumina) insulator 40 (FIG. 1) is shown, the aperture exposing the upper surface of the ground plane plate 20, while the frame of the insulator 40 has the lower surface disposed on the portions of the upper surface of peripheral portions of such ring 14. It is noted that the insulator 40 is disposed over the smaller apertures 18a, 18b formed in buffer ring 14, as shown in FIG. 3.
  • the insulator 40 includes a lower alumina apertured layer 42, here about 0.025 inches thick, the peripheral edges being aligned with the peripheral edges of both the substrate 12 and the buffer ring 14.
  • the aperture 44 formed within layer 42 is aligned with, and exposes, the upper surface of ground plane plate 20 while the frame portion of layer 42 is disposed on the portion of ring 14 disposed about the smaller apertures 18a, 18b of the buffer ring 14.
  • the larger aperture 16 has disposed within it the lower copper layer 22 of ground plane plate 20, the upper layer 4, has disposed about its periphery the outer edges of the aperture 44 of lower ceramic layer 42.
  • the upper surface of ground plane plate 20 is substantially even, or level with, the upper surface 43 of the lower ceramic layer 42, as shown more clearly in FIG. 3.
  • Opposing side portions of the upper surface 43 of lower ceramic layer 42 are metallized with a suitable refractory metal, here tungsten by thick-film screening to form four conductive regions 44a, 44b, 44c, 44d (FIG. 1) which are electrically insulated from each other, and which extend longitudinally from the outer edge of the aperture formed on the surface of lower ceramic layer 42 to the outer edges of such layer 42. It is noted that two pairs of opposing conductive regions 44a, 44b, or 44c, 44d are provided with inner ends 49 disposed adjacent the upper surface of the ground plane plate 20, as shown in FIGS. 2 and 3.
  • conductive leads 48a-48d Connected to the conductive regions 44a-44d are planar gold-plated kovar material strip conductive leads 48a-48d, respectively, as shown, that are brazed to conductive layers 44a-44d. It is noted that while the outer ends 50 of the leads 44a-48d extend beyond the outer periphery of the package 10, the inner ends 52 of the leads 48a-48d are connected to the outer regions 54 of the conductive regions 44a-44d, as shown more clearly in FIG. 3.
  • the upper ceramic (here alumina) insulating layer 60 here is about 0.050 inches thick, has an aperture 62; it being noted that while this aperture 62 is aligned with the aperture 44 formed in the lower ceramic layer 42, aperture 62 is larger than the aperture in the lower layer 42.
  • the lower surface of the upper insulating layer 60 is disposed on the upper surface of the lower ceramic layer 42.
  • portions of the lower surface of upper ceramic layer 60 are disposed on the upper surface portions of the metallized conductive regions 44a-44d. It is noted, however, that the inner ends 52 of the leads 48a-48d are disposed outside of the upper ceramic layer 60, as shown in FIGS. 2 and 3.
  • a conductive layer 64 here a thick-film screened gold-plated tungsten metallization, forms the upper surface of the upper ceramic insulating layer 60, such conductive layer 64 being used for bonding, and thereby hermetically sealing a cover 68 (here either kovar or ceramic alumina) to the package 10 after the transistor devices (not shown) and impedance matching devices (not shown) have been mounted within the package 10.
  • a cover 68 here either kovar or ceramic alumina
  • the package 10 is fabricated by brazing, in a single firing, substrate 12, the ring 14, the laminated ceramic insulator 40, the laminated copper ground plane plate 20 and the pair of conductive coated beryllia bodies 28a, 28b disposed within the compartments 23a, 23b, respectively.
  • a suitable braze material not shown, (here a copper-silver alloy) seals the ceramic insulator 40 to the substrate 12. It is first noted that the substrate 12 and the alumina ceramic used in the laminated insulator 40 have approximately the same, relatively low, linear thermal coefficients of expansion (the linear thermal coefficient of expansion being 8.5 micro-inches per inch per degree centrigrade) and hence the tendency of cracking or splintering of the alumina is reduced.
  • the copper laminated ground plane plate 20 while having a relatively high thermal coefficient of expansion does expand during the firing; however, it becomes brazed to the substrate 12 and remains brazed to the substrate 12, in its expanded condition, during the subsequent cooling process.
  • the copper used in plate 20 thus, because of its excellent electrical characteristics (i.e., low resistivity) provides a good radio frequency ground adjacent to the transistor die (not shown) to be mounted on the upper conductive coated surface of the beryllia bodies 28a, 28b, and for metal oxide semiconductor (MOS) capacitors (not shown) which are impedance matching devices and which are to be mounted to surface portion 25 of the plate 20.
  • MOS metal oxide semiconductor
  • the coefficient of thermal expansion of the copper ground plane plate 20 is greater than that of substrate 12, the annealing of the copper that occurs during the braze, firing cycle combined with the low strength of the copper relative to the base results in a copper surface which expands in thermal expansion like the substrate to which it is brazed. This is important to the mounting of the MOS capacitors in that it minimizes the bond stresses which would normally develop between the capacitors and the copper because of the large coefficient of thermal expansion of the copper.
  • the package 10 is shown to have a pair of transistor devices, each one thereof comprising a plurality of parallel connected transistor cells arranged in a grounded, or common base configuration.
  • the conductive bonding wires 80 are used to connect the collector (C) contacts of the transistor (which are electrically connected to the upper metallized surface of the beryllia) to the adjacent upper portion of a pair of the metallized conductive regions 44c, 44d formed on upper surfaces of the lower insulating layer 42 of the ceramic insulator 40 (it being noted that MOS, D-C blocking capacitors 90 are disposed on such regions); also conductive leads 82 are used to connect the base (B) electrodes of the transistor to the adjacent upper surface of the ground plane plate 20; and the bonding wires 84 are used to connect the emitter electrode (E) to the MOS capacitor 88 mounted to region 25 of the ground plane plate 20.
  • the interconnected MOS capacitors 89 are coupled to the metallized conductive regions 44a, 44b formed on the upper surface of the
  • the cover 68 (FIG. 1) is soldered with gold-tin solder to the conductive layer 64 on the upper surface of upper insulator layer 44 to thereby provide a hermetically sealed package 10.

Abstract

A microwave transistor package is provided having a thermal and electrical conductive refractory type substrate. A ground plane plate is provided, such plate having an open-ended compartment therein, the open end of such compartment being disposed adjacent an upper surface portion of the ground plane plate. A bottom surface of such plate is disposed on an upper, inner surface region of the substrate. The thermal coefficient of expansion of the ground plane plate is substantially greater than the thermal coefficient of expansion of the substrate. An electrical insulator is disposed within the compartment, such insulator having a relatively high thermal transfer characteristic and having upper and lower conductive layers with side wall portions disposed adjacent side wall portions of the compartment. A first apertured ceramic insulating layer having conductive metallization regions disposed on the upper surface of the ceramic insulator extending from the apertured edge of the ceramic insulator to the outer edge of the ceramic insulator is provided. The lower surface of the ceramic insulator is disposed over the substrate and about peripheral portions of the inner surface region of the substrate. A second apertured ceramic insulating layer is disposed over and aligned with the first apertured ceramic insulating layer, the upper surface of the second ceramic insulating layer being metallized and bondable to a cover for such package. The package is fabricated by brazing together, in a single step, the pair of ceramic insulating layers, the electrical insulator and the substrate.

Description

BACKGROUND OF THE INVENTION
This invention relates generally to microwave transistor packages and method of manufacturing such packages and more particularly microwave transistor packages having low parasitic reactance and adapted to have packaged therein impedance matching circuitry for the packaged transistor.
As is known in the art, in order to provide transistor components having relatively high power, high efficiency and high gain, in many applications it is necessary to connect in parallel a large number of individual transistor cells within a hermetically sealed package. Increasing the number of cells in parallel, however. reduces the input impedance of the transistor component. For example, a typical unmatched 30 watt bi-polar transistor component having parallel connected cells at L-band has an input impedance of about 0.3 ohms, while the input impedance of a typical 100 watt component is typically less than 0.1 ohms. This relatively low impedance is clearly very difficult to impedance match to, and reproducibility suffers as the impedance to be matched becomes sensitive to component variations and manufacturing or assembly tolerances. Thus, it becomes highly desirable to provide an impedance matching network within the package, since if the matching network were outside the package relatively long lead wires would be required thereby increasing the inductive reactance which must be cancelled by the matching network.
As is also known in the art, a typical microwave transistor package includes a beryllia insulator to provide a low thermal resistance from the transistor die to the package heat sink base or header. The upper and lower surfaces of the beryllia insulator have gold layers for attachment to the transistor die on the upper surface and for attachment to the header on the lower surface. The header also serves as the ground plane conductor. The transistor typically has its collector contact formed on the bottom of the die and hence, in those configurations, requiring a grounded, or common base configuration, it is necessary to electrically connect the base electrode, formed on the upper surface of the transistor die, to the header. This connector is typically done with a wire lead and it is generally desirable to use relatively short leads in order to reduce the inductive reactance of such wire lead since such reactance becomes part of the input impedance to the transistor component. One technique suggested to reduce the length of the lead and hence reduce its parasitic inductive reactance is to position the beryllia between a pair of conductive rails, as discussed in U.S. Pat. No. 3,784,884, issued Jan. 8, 1974, Demir S. Zoroglu, inventor. As discussed in such patent, bonding wires are used to connect the transistor to the grounded rails and the length of such wires is reduced by having the height of the grounded bonding rails approximately equal to the thickness of the beryllia insulator so that the bonding surface of the rail is almost even with the transistor die. However, as described in U.S. Pat. No. 4,150,393, issued Apr. 17, 1979, Richard W. Wilson and Marcy B. Goldstein, inventors, and assigned to the same assignee as U.S. Pat. No. 3,784,884, referred to above, relatively expensive coined bonding rails are required in such package.
One technique suggested to remove the requirement for the coined bonding rails discussed in U.S. Pat. No. 4,784,884, referred to above, is to provide a copper header with a pedestal having a channel formed in the upper surface thereof into which the metallized beryllium insulator is positioned as discussed in U.S. Pat. No. 4,150,393, referred to above. Also included in the package discussed in the latter patent is a toroid shaped alumina ceramic insulator which encircles the sides of the pedestal portion of the header and which has lower surfaces which rest on the lower base portion of the header. The upper surface of the insulator support metallized conductive leads to the package. The alumina insulator, conductive coated beryllia insulator and metal conductive leads are brazed together in one operation to form a single unit. It is first noted, however, that, as mentioned above, in high power devices the impedance matching network should be included within the package and with the relatively small package described above, while patentee suggests that surfaces of the pedestal can be utilized to have a MOS chip capacitor attached to it, if the size of the pedestal were increased to have sufficient surface area to accomodate impedance matching devices the toroid shaped ceramic insulator would tend to splinter during brazing of the ceramic insulator to the header, since mechanical stresses during brazing cause the insulator to splinter because of the great difference between the relatively low coefficient of thermal expansion of the ceramic insulator and the relatively high thermal coefficient of expansion of the copper header. However, the cylindrical form of the package does not allow it to be readily used with more readily available circuitry which is designed to receive rectangular packages. Further, increasing the size of the pedestal header to accomplish the impedance matching devices tends to agravate the effect of the great difference between the thermal expansion properties of the header and the ceramic on the ceramic's tendency to splinter.
SUMMARY OF THE INVENTION
In accordance with the present invention, a microwave transistor package is provided having: a thermal and electrical conductive refractory type substrate; a ground plane plate having an open-ended compartment therein, such open-end being disposed adjacent an upper surface portion of the ground plane plate, a bottom surface of such plate being disposed on an upper, inner surface region of the substrate; the thermal coefficient of expansion of the ground plane plate being substantially greater than the thermal coefficient of expansion of the substrate; an electrical insulator, disposed within the compartment having a relatively high thermal transfer characteristic and having upper and lower conductive layers with side wall portions disposed adjacent side wall portions of the compartment; a first apertured ceramic insulating layer having conductive metallization regions disposed on the upper surface of the ceramic insulator and extending from the apertured edge of the ceramic insulator to the outer edge of the ceramic insulator, the lower surface of the ceramic insulator being disposed over a surface portion of the substrate disposed about peripheral portions of the inner surface region of the substrate; a second apertured ceramic insulating layer disposed over and aligned with the first apertured ceramic insulating layer, the upper surface of the second ceramic insulating layer being metallized and bondable to a cover for such package. The package is fabricated by brazing together, in a single step, the pair of ceramic insulating layers, the electrical insulator (typically beryllia) and the substrate. Thus, since the substrate and the ceramic insulating layers have substantially the same, relatively low thermal coefficients of expansion, the ceramic insulating layers will not crack during the brazing step. Further, while the substrate is of a refractory type material and hence impractical for machining into a channel provided pedestal, the ground plane plate is relatively thin and can be easily provided with a compartment for the beryllia and also be made large enough to accomodate an impedance matching device on the upper surface portion of the ground plane plate adjacent the compartment; the use of the compartment enabling the use of relatively short grounding wire leads from between the upper surface of the ground plane plate and the transistor die mounted to the upper, metallized surface of the beryllia.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing features of this invention as well as the invention itself may be more fully understood from the following detailed description read together with the accompanying drawings, in which:
FIG. 1 is an exploded, isometric drawing of a microwave transistor package according to the invention;
FIG. 2 is a plan view of the microwave transistor package of FIG. 1;
FIG. 3 is a cross-section elevation view of the package of FIG. 1, such cross-section being taken along line 3--3 of FIG. 2;
FIG. 4 is a plan view of the microwave transistor package of FIG. 1 having packaged therein a transistor component and electrically interconnected impedance matching devices; and
FIG. 5 is a cross-section elevation view of the package shown in FIG. 4, such cross-section being taken along line 5--5 of FIG. 4.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to FIGS. 1, 2 and 3, a microwave transistor package 10 is shown to include a rectangular planar, electrically and thermally conductive substrate 12, here an 0.042 inch thick slab of a refractory material, here sintered tungsten infiltrated with copper (here Thermkon material, a product of CMW, Inc., Indianapolis, Ind. having a relatively low thermal coefficient of expansion. The outer dimensions of the substrate 12 are here 0.56 inches by 0.48 inches. Disposed over the substrate 12 is a 0.020 inch thick copper buffer ring 14 having a relatively large aperture 16 flanked by a pair of smaller apertures 18a and 18b. The ring 14 is disposed on, and aligned with, the outer edges of the substrate 12. A relatively thin, here 0.040 inch thick copper ground plane plate 20, is fabricated by constructing a laminated structure made up of a lower copper sheet 22, here 0.020 inches thick, to which is soldered an upper copper sheet 24, here also 0.020 inches thick. The upper sheet 24 has a pair of rectangular apertures 24a, 24b formed therein using conventional photolithographic chemical etching techniques. It is noted that the linear thermal coefficient of expansion of the copper plate 20 (19 microinches per inch per degree centigrade) is substantially greater than the linear thermal coefficient of expansion of the refractory substrate 12 (9.5 micro-inches per inch per degree centigrade). The outer dimensions of the ground plane plate 20 are here 0.225 inches by 0.375 inches and are dimensioned to allow such plate 20 to fit into the larger aperture 16 formed in buffer ring 14. The dimensions of each of the smaller apertures 24a, 24b are here 0.118 inches by 0.048 inches. It is noted that when the upper and lower sheets 22, 24 are soldered together, a pair of rectangularly shaped open- ended compartments 23a, 23b (FIG. 2) are formed with plate 20. Further disposed adjacent the pair of compartments 23a, 23b is a relatively large portion 25 of the upper surface of the ground plane plate 20 and, as will be discussed herein after, such surface portion 25 will be used for mounting impedance matching circuitry components. Completing the lower portion of the package 10 are a pair of electrically insulating bodies 28a, 28b having relatively high thermal transfer conductivity characteristics, here 0.025 inch thick beryllia (BeO) (having a linear thermal coefficient of expansion of 9 micro-inches per inch per degree centigrade) coated on the upper and lower surfaces with molybdenum-manganese-gold conductive layers 32a, 32b, respectively as shown. The bodies 28a, 28b are disposed within the compartments 23a, 23b, respectively. It is noted that since the compartments 23a, 23b are herein 0.020 inches deep, that the upper surfaces of the coated beryllia bodies 28a, 28b are substantially level, or even, with the upper surface of the ground plane plate 20. In this way, as will be described hereinafter, once transistor dies (not shown) are mounted to the layer 32a on the upper conductive coated surface of the bodies 28a, 28b, the electrical contacts of such transistors, more particularly base electrode contacts, thereof, may be electrically connected to ground in a common, or grounded base configuration, through the use of relatively short lead wires which extend from the base contacts to the upper surface region 25 of the ground plane plate 20 adjacent to the edges of the compartments 23a, 23b.
Referring now to the upper portion of the package 10, a laminated apertured, ceramic (here alumina) insulator 40 (FIG. 1) is shown, the aperture exposing the upper surface of the ground plane plate 20, while the frame of the insulator 40 has the lower surface disposed on the portions of the upper surface of peripheral portions of such ring 14. It is noted that the insulator 40 is disposed over the smaller apertures 18a, 18b formed in buffer ring 14, as shown in FIG. 3. The insulator 40 includes a lower alumina apertured layer 42, here about 0.025 inches thick, the peripheral edges being aligned with the peripheral edges of both the substrate 12 and the buffer ring 14. The aperture 44 formed within layer 42 is aligned with, and exposes, the upper surface of ground plane plate 20 while the frame portion of layer 42 is disposed on the portion of ring 14 disposed about the smaller apertures 18a, 18b of the buffer ring 14. Thus, while the larger aperture 16 has disposed within it the lower copper layer 22 of ground plane plate 20, the upper layer 4, has disposed about its periphery the outer edges of the aperture 44 of lower ceramic layer 42. Thus, it is noted that the upper surface of ground plane plate 20 is substantially even, or level with, the upper surface 43 of the lower ceramic layer 42, as shown more clearly in FIG. 3.
Opposing side portions of the upper surface 43 of lower ceramic layer 42 are metallized with a suitable refractory metal, here tungsten by thick-film screening to form four conductive regions 44a, 44b, 44c, 44d (FIG. 1) which are electrically insulated from each other, and which extend longitudinally from the outer edge of the aperture formed on the surface of lower ceramic layer 42 to the outer edges of such layer 42. It is noted that two pairs of opposing conductive regions 44a, 44b, or 44c, 44d are provided with inner ends 49 disposed adjacent the upper surface of the ground plane plate 20, as shown in FIGS. 2 and 3. Connected to the conductive regions 44a-44d are planar gold-plated kovar material strip conductive leads 48a-48d, respectively, as shown, that are brazed to conductive layers 44a-44d. It is noted that while the outer ends 50 of the leads 44a-48d extend beyond the outer periphery of the package 10, the inner ends 52 of the leads 48a-48d are connected to the outer regions 54 of the conductive regions 44a-44d, as shown more clearly in FIG. 3.
The upper ceramic (here alumina) insulating layer 60, here is about 0.050 inches thick, has an aperture 62; it being noted that while this aperture 62 is aligned with the aperture 44 formed in the lower ceramic layer 42, aperture 62 is larger than the aperture in the lower layer 42. Thus, as shown in FIG. 3, it is noted that the lower surface of the upper insulating layer 60 is disposed on the upper surface of the lower ceramic layer 42. It is also noted that portions of the lower surface of upper ceramic layer 60 are disposed on the upper surface portions of the metallized conductive regions 44a-44d. It is noted, however, that the inner ends 52 of the leads 48a-48d are disposed outside of the upper ceramic layer 60, as shown in FIGS. 2 and 3. A conductive layer 64, here a thick-film screened gold-plated tungsten metallization, forms the upper surface of the upper ceramic insulating layer 60, such conductive layer 64 being used for bonding, and thereby hermetically sealing a cover 68 (here either kovar or ceramic alumina) to the package 10 after the transistor devices (not shown) and impedance matching devices (not shown) have been mounted within the package 10.
The package 10 is fabricated by brazing, in a single firing, substrate 12, the ring 14, the laminated ceramic insulator 40, the laminated copper ground plane plate 20 and the pair of conductive coated beryllia bodies 28a, 28b disposed within the compartments 23a, 23b, respectively. A suitable braze material, not shown, (here a copper-silver alloy) seals the ceramic insulator 40 to the substrate 12. It is first noted that the substrate 12 and the alumina ceramic used in the laminated insulator 40 have approximately the same, relatively low, linear thermal coefficients of expansion (the linear thermal coefficient of expansion being 8.5 micro-inches per inch per degree centrigrade) and hence the tendency of cracking or splintering of the alumina is reduced. The copper laminated ground plane plate 20, while having a relatively high thermal coefficient of expansion does expand during the firing; however, it becomes brazed to the substrate 12 and remains brazed to the substrate 12, in its expanded condition, during the subsequent cooling process. The copper used in plate 20 thus, because of its excellent electrical characteristics (i.e., low resistivity) provides a good radio frequency ground adjacent to the transistor die (not shown) to be mounted on the upper conductive coated surface of the beryllia bodies 28a, 28b, and for metal oxide semiconductor (MOS) capacitors (not shown) which are impedance matching devices and which are to be mounted to surface portion 25 of the plate 20. Though the coefficient of thermal expansion of the copper ground plane plate 20 is greater than that of substrate 12, the annealing of the copper that occurs during the braze, firing cycle combined with the low strength of the copper relative to the base results in a copper surface which expands in thermal expansion like the substrate to which it is brazed. This is important to the mounting of the MOS capacitors in that it minimizes the bond stresses which would normally develop between the capacitors and the copper because of the large coefficient of thermal expansion of the copper.
Referring now to FIGS. 4 and 5, the package 10 is shown to have a pair of transistor devices, each one thereof comprising a plurality of parallel connected transistor cells arranged in a grounded, or common base configuration. The conductive bonding wires 80 are used to connect the collector (C) contacts of the transistor (which are electrically connected to the upper metallized surface of the beryllia) to the adjacent upper portion of a pair of the metallized conductive regions 44c, 44d formed on upper surfaces of the lower insulating layer 42 of the ceramic insulator 40 (it being noted that MOS, D-C blocking capacitors 90 are disposed on such regions); also conductive leads 82 are used to connect the base (B) electrodes of the transistor to the adjacent upper surface of the ground plane plate 20; and the bonding wires 84 are used to connect the emitter electrode (E) to the MOS capacitor 88 mounted to region 25 of the ground plane plate 20. The interconnected MOS capacitors 89 are coupled to the metallized conductive regions 44a, 44b formed on the upper surface of the lower insulating layer 42.
Having eutectically attached the electrical components within the package 10, the cover 68 (FIG. 1) is soldered with gold-tin solder to the conductive layer 64 on the upper surface of upper insulator layer 44 to thereby provide a hermetically sealed package 10.
Having described a preferred embodiment of the invention, it is now evident that other embodiments incorporating its concepts will become readily apparent to one of skill in the art. It is felt, therefore, that this invention should not be restricted to the disclosed embodiment but rather should be limited only by the spirit and scope of the appended claims.

Claims (5)

What is claimed is:
1. In combination:
(a) a thermal and electrical conductive substrate;
(b) a ground plane plate having an open-ended compartment therein, the open-end of such compartment being disposed adjacent an upper surface portion of the plate, a bottom surface of such plate being disposed on, and bonded to, a first upper surface portion of the substrate, the thermal coefficient of expansion of the ground plane plate being substantially greater than the thermal coefficient of expansion of the substrate; and
(c) an electrical insulator having an aperture therethrough, such insulator having lower surface portions disposed on, and bonded to, a second upper surface portion of the substrate disposed about the first upper surface portion of the substrate, such aperture exposing the open-end of the compartment and the upper surface portion of the plate.
2. The combination recited in claim 1 including a second electrical insulator having relatively high thermal transfer characteristics and having electrical conductive layers on upper and lower surfaces thereof, such second insulator being disposed within the compartment, the upper conductive layer being substantially level with the upper surface portion of the plate.
3. The combination recited in claim 2 including impedance matching electrical components disposed on the upper surface portion of the plate.
4. A microwave transistor package comprising:
(a) a thermal and electrical conductive substrate;
(b) a ground plane plate having an open-ended compartment therein, such open-end being disposed adjacent an upper surface portion of the ground plane plate, a bottom surface of such plate being disposed on an upper, inner surface region of the substrate, the thermal coefficient of expansion of the ground plane plate being substantially greater than the thermal coefficient of expansion of the substrate;
(c) electrical insulator means for supporting a microwave transistor, said electrical insulator means being disposed within the compartment, having a relatively high thermal transfer characteristic and having upper and lower conductive layers with side wall portions disposed adjacent side wall portions of the compartment;
(d) a first apertured ceramic insulating layer having conductive metallization regions disposed on the upper surface of the ceramic insulating layer and extending from adjacent the apertured edge of the ceramic insulator to adjacent the outer edge of the ceramic insulator, the lower surface of the ceramic insulator being disposed over a surface portion of the substrate disposed about peripheral portions of the inner surface region of the substrate; and
(e) a second apertured ceramic insulating layer disposed over and aligned with the first apertured ceramic insulating layer, the upper surface of the second ceramic insulating layer being metallized and bondable to a cover for such package.
5. The package recited in claim 4 including impedance matching electrical components disposed on the upper surface portion of the plate.
US06/567,829 1984-01-03 1984-01-03 Microwave transistor package Expired - Fee Related US4649416A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US06/567,829 US4649416A (en) 1984-01-03 1984-01-03 Microwave transistor package
CA000471318A CA1232083A (en) 1984-01-03 1985-01-02 Microwave transistor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/567,829 US4649416A (en) 1984-01-03 1984-01-03 Microwave transistor package

Publications (1)

Publication Number Publication Date
US4649416A true US4649416A (en) 1987-03-10

Family

ID=24268810

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/567,829 Expired - Fee Related US4649416A (en) 1984-01-03 1984-01-03 Microwave transistor package

Country Status (2)

Country Link
US (1) US4649416A (en)
CA (1) CA1232083A (en)

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763223A (en) * 1986-12-05 1988-08-09 Babcock Display Products, Inc. Non-soldered lead apparatus
US4768075A (en) * 1985-11-15 1988-08-30 Bbc Brown, Boveri & Company, Limited Power semiconductor module
US4829348A (en) * 1984-10-19 1989-05-09 Bbc Brown, Boveri & Company Limited Disconnectable power semiconductor component
EP0444820A2 (en) * 1990-02-26 1991-09-04 Raytheon Company MMIC package and connection
US5063436A (en) * 1989-02-02 1991-11-05 Asea Brown Boveri Ltd. Pressure-contacted semiconductor component
US5105260A (en) * 1989-10-31 1992-04-14 Sgs-Thomson Microelectronics, Inc. Rf transistor package with nickel oxide barrier
US5109268A (en) * 1989-12-29 1992-04-28 Sgs-Thomson Microelectronics, Inc. Rf transistor package and mounting pad
US5126827A (en) * 1991-01-17 1992-06-30 Avantek, Inc. Semiconductor chip header having particular surface metallization
US5214498A (en) * 1990-02-26 1993-05-25 Raytheon Company MMIC package and connector
US5258646A (en) * 1990-11-16 1993-11-02 Mitsubishi Denki Kabushiki Kaisha Package for microwave IC
WO1994005038A1 (en) * 1992-08-21 1994-03-03 Olin Corporation Metal electronic package incorporating a multi-chip module
US5305947A (en) * 1990-10-26 1994-04-26 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor-mounting heat-radiative substrates and semiconductor package using the same
US5309014A (en) * 1992-04-02 1994-05-03 Motorola Inc. Transistor package
US5334874A (en) * 1991-09-13 1994-08-02 Metzler Richard A Electronic device package
US5347158A (en) * 1992-08-19 1994-09-13 Kabushiki Kaisha Toshiba Semiconductor device having a particular terminal arrangement
US5362989A (en) * 1992-12-16 1994-11-08 Alliedsignal Inc. Electrical isolation for power-saving purposes
US5760473A (en) * 1996-06-25 1998-06-02 Brush Wellman Inc. Semiconductor package having a eutectic bonding layer
US5777259A (en) * 1994-01-14 1998-07-07 Brush Wellman Inc. Heat exchanger assembly and method for making the same
US5814880A (en) * 1989-12-22 1998-09-29 Northrop Grumman Corporation Thick film copper metallization for microwave power transistor packages
US6022426A (en) * 1995-05-31 2000-02-08 Brush Wellman Inc. Multilayer laminate process
US6049127A (en) * 1997-06-14 2000-04-11 Korea Institute Of Science And Technology Hermetically sealed tungsten-copper composite package container for packaging of microwave devices
US6056186A (en) * 1996-06-25 2000-05-02 Brush Wellman Inc. Method for bonding a ceramic to a metal with a copper-containing shim
US6291878B1 (en) 1993-04-22 2001-09-18 Sundstrand Corporation Package for multiple high power electrical components
US20040026778A1 (en) * 2000-01-12 2004-02-12 International Rectifier Corporation Low cost power semiconductor module without substate
WO2004057666A3 (en) * 2002-12-19 2004-09-10 Infineon Technologies Ag Rf power transistor with internal bias feed
US20060043550A1 (en) * 2004-08-25 2006-03-02 International Rectifier Corporation Hermetic semiconductor package
US20060043609A1 (en) * 2004-08-26 2006-03-02 Brennan John M Integrated circuit with substantially perpendicular wire bonds
EP2618482A1 (en) * 2010-09-14 2013-07-24 Huawei Technologies Co., Ltd. Power amplifier, asymmetric doherty power amplifier device and base station
EP2733742A1 (en) * 2012-11-15 2014-05-21 Nxp B.V. Amplifier circuit
US20140306334A1 (en) * 2013-04-15 2014-10-16 Kabushiki Kaisha Toshiba Semiconductor package
US8885758B2 (en) 2010-06-12 2014-11-11 Huawei Technologies Co., Ltd. Data stream processing method, device, and system
US20180153045A1 (en) * 2016-11-29 2018-05-31 Molex, Llc Electronic component
CN112750582A (en) * 2020-12-31 2021-05-04 中国电子科技集团公司第五十五研究所 Self-positioning mounting and brazing method for ceramic insulator microwave packaging shell

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3683241A (en) * 1971-03-08 1972-08-08 Communications Transistor Corp Radio frequency transistor package
US3728589A (en) * 1971-04-16 1973-04-17 Rca Corp Semiconductor assembly
US3753056A (en) * 1971-03-22 1973-08-14 Texas Instruments Inc Microwave semiconductor device
US3784884A (en) * 1972-11-03 1974-01-08 Motorola Inc Low parasitic microwave package
US3936864A (en) * 1973-05-18 1976-02-03 Raytheon Company Microwave transistor package
US3946428A (en) * 1973-09-19 1976-03-23 Nippon Electric Company, Limited Encapsulation package for a semiconductor element
US3996603A (en) * 1974-10-18 1976-12-07 Motorola, Inc. RF power semiconductor package and method of manufacture
US4023198A (en) * 1974-08-16 1977-05-10 Motorola, Inc. High frequency, high power semiconductor package
US4092664A (en) * 1976-02-17 1978-05-30 Hughes Aircraft Company Carrier for mounting a semiconductor chip
US4150393A (en) * 1975-09-29 1979-04-17 Motorola, Inc. High frequency semiconductor package
US4172261A (en) * 1977-01-10 1979-10-23 Nippon Electric Co., Ltd. Semiconductor device having a highly air-tight package
US4213141A (en) * 1978-05-12 1980-07-15 Solid State Scientific Inc. Hybrid transistor

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3683241A (en) * 1971-03-08 1972-08-08 Communications Transistor Corp Radio frequency transistor package
US3753056A (en) * 1971-03-22 1973-08-14 Texas Instruments Inc Microwave semiconductor device
US3728589A (en) * 1971-04-16 1973-04-17 Rca Corp Semiconductor assembly
US3784884A (en) * 1972-11-03 1974-01-08 Motorola Inc Low parasitic microwave package
US3936864A (en) * 1973-05-18 1976-02-03 Raytheon Company Microwave transistor package
US3946428A (en) * 1973-09-19 1976-03-23 Nippon Electric Company, Limited Encapsulation package for a semiconductor element
US4023198A (en) * 1974-08-16 1977-05-10 Motorola, Inc. High frequency, high power semiconductor package
US3996603A (en) * 1974-10-18 1976-12-07 Motorola, Inc. RF power semiconductor package and method of manufacture
US4150393A (en) * 1975-09-29 1979-04-17 Motorola, Inc. High frequency semiconductor package
US4092664A (en) * 1976-02-17 1978-05-30 Hughes Aircraft Company Carrier for mounting a semiconductor chip
US4172261A (en) * 1977-01-10 1979-10-23 Nippon Electric Co., Ltd. Semiconductor device having a highly air-tight package
US4213141A (en) * 1978-05-12 1980-07-15 Solid State Scientific Inc. Hybrid transistor

Cited By (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4829348A (en) * 1984-10-19 1989-05-09 Bbc Brown, Boveri & Company Limited Disconnectable power semiconductor component
US4768075A (en) * 1985-11-15 1988-08-30 Bbc Brown, Boveri & Company, Limited Power semiconductor module
US4763223A (en) * 1986-12-05 1988-08-09 Babcock Display Products, Inc. Non-soldered lead apparatus
US5063436A (en) * 1989-02-02 1991-11-05 Asea Brown Boveri Ltd. Pressure-contacted semiconductor component
USRE37082E1 (en) 1989-10-31 2001-03-06 Stmicroelectronics, Inc. RF transistor package with nickel oxide barrier
US5105260A (en) * 1989-10-31 1992-04-14 Sgs-Thomson Microelectronics, Inc. Rf transistor package with nickel oxide barrier
US5814880A (en) * 1989-12-22 1998-09-29 Northrop Grumman Corporation Thick film copper metallization for microwave power transistor packages
USRE35845E (en) * 1989-12-29 1998-07-14 Sgs-Thomson Microelectronics, Inc. RF transistor package and mounting pad
US5109268A (en) * 1989-12-29 1992-04-28 Sgs-Thomson Microelectronics, Inc. Rf transistor package and mounting pad
EP0444820A2 (en) * 1990-02-26 1991-09-04 Raytheon Company MMIC package and connection
US5214498A (en) * 1990-02-26 1993-05-25 Raytheon Company MMIC package and connector
EP0444820A3 (en) * 1990-02-26 1992-07-08 Raytheon Company Mmic package and connection
US5305947A (en) * 1990-10-26 1994-04-26 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor-mounting heat-radiative substrates and semiconductor package using the same
US5258646A (en) * 1990-11-16 1993-11-02 Mitsubishi Denki Kabushiki Kaisha Package for microwave IC
US5126827A (en) * 1991-01-17 1992-06-30 Avantek, Inc. Semiconductor chip header having particular surface metallization
US5334874A (en) * 1991-09-13 1994-08-02 Metzler Richard A Electronic device package
US5309014A (en) * 1992-04-02 1994-05-03 Motorola Inc. Transistor package
US5347158A (en) * 1992-08-19 1994-09-13 Kabushiki Kaisha Toshiba Semiconductor device having a particular terminal arrangement
US5504372A (en) * 1992-08-21 1996-04-02 Olin Corporation Adhesively sealed metal electronic package incorporating a multi-chip module
WO1994005038A1 (en) * 1992-08-21 1994-03-03 Olin Corporation Metal electronic package incorporating a multi-chip module
US5362989A (en) * 1992-12-16 1994-11-08 Alliedsignal Inc. Electrical isolation for power-saving purposes
US6291878B1 (en) 1993-04-22 2001-09-18 Sundstrand Corporation Package for multiple high power electrical components
US5777259A (en) * 1994-01-14 1998-07-07 Brush Wellman Inc. Heat exchanger assembly and method for making the same
US6022426A (en) * 1995-05-31 2000-02-08 Brush Wellman Inc. Multilayer laminate process
US5760473A (en) * 1996-06-25 1998-06-02 Brush Wellman Inc. Semiconductor package having a eutectic bonding layer
US6056186A (en) * 1996-06-25 2000-05-02 Brush Wellman Inc. Method for bonding a ceramic to a metal with a copper-containing shim
US6049127A (en) * 1997-06-14 2000-04-11 Korea Institute Of Science And Technology Hermetically sealed tungsten-copper composite package container for packaging of microwave devices
US7122890B2 (en) 2000-01-12 2006-10-17 International Rectifier Corporation Low cost power semiconductor module without substrate
US20040026778A1 (en) * 2000-01-12 2004-02-12 International Rectifier Corporation Low cost power semiconductor module without substate
US6703703B2 (en) * 2000-01-12 2004-03-09 International Rectifier Corporation Low cost power semiconductor module without substrate
US7545033B2 (en) 2000-01-12 2009-06-09 International Rectifier Corporation Low cost power semiconductor module without substrate
WO2004057666A3 (en) * 2002-12-19 2004-09-10 Infineon Technologies Ag Rf power transistor with internal bias feed
US20060043550A1 (en) * 2004-08-25 2006-03-02 International Rectifier Corporation Hermetic semiconductor package
US8232635B2 (en) * 2004-08-25 2012-07-31 International Rectifier Corporation Hermetic semiconductor package
US20060043609A1 (en) * 2004-08-26 2006-03-02 Brennan John M Integrated circuit with substantially perpendicular wire bonds
US7109589B2 (en) * 2004-08-26 2006-09-19 Agere Systems Inc. Integrated circuit with substantially perpendicular wire bonds
US8885758B2 (en) 2010-06-12 2014-11-11 Huawei Technologies Co., Ltd. Data stream processing method, device, and system
EP2618482A1 (en) * 2010-09-14 2013-07-24 Huawei Technologies Co., Ltd. Power amplifier, asymmetric doherty power amplifier device and base station
EP2618482A4 (en) * 2010-09-14 2013-07-24 Huawei Tech Co Ltd Power amplifier, asymmetric doherty power amplifier device and base station
EP2733742A1 (en) * 2012-11-15 2014-05-21 Nxp B.V. Amplifier circuit
US9190970B2 (en) 2012-11-15 2015-11-17 Nxp B.V. Amplifier circuit
US20140306334A1 (en) * 2013-04-15 2014-10-16 Kabushiki Kaisha Toshiba Semiconductor package
US9013034B2 (en) * 2013-04-15 2015-04-21 Kabushiki Kaisha Toshiba Semiconductor package
US20180153045A1 (en) * 2016-11-29 2018-05-31 Molex, Llc Electronic component
US10237991B2 (en) * 2016-11-29 2019-03-19 Molex, Llc Electronic component
CN112750582A (en) * 2020-12-31 2021-05-04 中国电子科技集团公司第五十五研究所 Self-positioning mounting and brazing method for ceramic insulator microwave packaging shell
CN112750582B (en) * 2020-12-31 2022-08-16 中国电子科技集团公司第五十五研究所 Self-positioning rack-mounting brazing method for ceramic insulator microwave packaging shell

Also Published As

Publication number Publication date
CA1232083A (en) 1988-01-26

Similar Documents

Publication Publication Date Title
US4649416A (en) Microwave transistor package
US5075759A (en) Surface mounting semiconductor device and method
US4639760A (en) High power RF transistor assembly
US5574314A (en) Packaged semiconductor device including shielded inner walls
US4172261A (en) Semiconductor device having a highly air-tight package
US4278990A (en) Low thermal resistance, low stress semiconductor package
US4982311A (en) Package for very large scale integrated circuit
US5635751A (en) High frequency transistor with reduced parasitic inductance
US5309014A (en) Transistor package
GB2123209A (en) High-frequency circuit
US3515952A (en) Mounting structure for high power transistors
US3753056A (en) Microwave semiconductor device
EP1250717A2 (en) Ldmos power package with a plurality of ground signal paths
US4067040A (en) Semiconductor device
US5889319A (en) RF power package with a dual ground
EP0117434A1 (en) Hybrid microwave subsystem
US5465007A (en) High frequency transistor with reduced parasitic inductance
US5148264A (en) High current hermetic package
US5751555A (en) Electronic component having reduced capacitance
EP0408904A2 (en) Surface mounting semiconductor device and method
US3710202A (en) High frequency power transistor support
US5374786A (en) Ceramic wall hybrid package with washer and solid metal through wall leads
EP0131004A1 (en) Microwave packages
JPS61224427A (en) Package for high frequency integrated device
JPS61222238A (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: RAYTHEON COMPANY, LEXINGTON, MA 02173 A DE CORP.

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:BORKOWSKI, MICHAEL T.;LAIGHTON, DAVID G.;ALTSCHUL, BARRY;REEL/FRAME:004227/0774

Effective date: 19831230

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Lapsed due to failure to pay maintenance fee

Effective date: 19950315

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362