|Publication number||US4580193 A|
|Application number||US 06/691,248|
|Publication date||1 Apr 1986|
|Filing date||14 Jan 1985|
|Priority date||14 Jan 1985|
|Also published as||CA1224277A, CA1224277A1, DE3585440D1, EP0188726A2, EP0188726A3, EP0188726B1|
|Publication number||06691248, 691248, US 4580193 A, US 4580193A, US-A-4580193, US4580193 A, US4580193A|
|Inventors||John C. Edwards|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (21), Classifications (23), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to the space-efficient interconnection of integrated circuit elements of chips to a bus on a circuit substrate or board. The bus comprises a group of lines extending generally parallel which are to be connected to several chips on the board by wires which attach to pads on the chips, the wires being attached to specific pads on the bus and arching over intermediate lines of the bus.
This invention emloys existing bonding techniques for wires arched between pads of chip pads and pads of bus lines, known as wire bonding. Subsequent to such attachment, the wires are covered with a passivation material, which may be a standard material for that purpose.
U.S. Pat. No. 3,582,592 to Cooke et al is a generally similar overall teaching with respect to this invention. The lines on the circuit board in that patent are entirely straight and do not form significant groups for connection to several chips as a bus. The lines in that patent are apparently so wide that no separate pad is used, bonding of the arched wires being directly to each line. This invention employs a unique pattern to achieve compact interconnection, that pattern being not at all similar to that of the foregoing patent.
In accordance with this invention, wire bonding pads on the board or substrate are located having a long, bonding axis facing the chip. Generally the board pad is aimed more or less directly at the chip pad to be connected, the purpose being to optimize wirebond termination opportunities and to minimize possible shorts due to bonding-wire sag. The pads are spaced laterally along the length of the line of chips to be connected. Leads on the board parallel with the line of chips are connected to the top and bottom end of the bonding axis of each board pad, forming individual lines of a bus including the pad and the board leads to each end of the pad. Contiguous bus lines in a section including the board pads are directed toward the chip line either by including pads so directed or by having line sections parallel or spaced from the pads. A second section of the bus has similar pads or line parts from which the bus lines continue at a position reversing the displacement of the first section. Similar alternating sections occur along the bus.
Generally, available space along the line of chips is not a limiting factor and the pads can be laterally spaced or fanned out so that the board pads have little cumulative effect on the spacing of the bus perpendicular to the chips. The perpendicular width of the bus then can be as small as the sum of total line width, plus total line spacing, plus the effective length in the perpendicular direction of the one board pad having the longest effective perpendicular length. This reduces the board space used for a bus and minimizes the length of wires connecting chips to a bus.
The invention is described in detail below, with reference to drawing in which:
FIG. 1 is a view of the preferred and best implementation, having four memory chips on a circuit board;
FIG. 2 is an enlarged view of a middle one of those chips and the associated buses.
FIG. 3 is a side view of a section of FIG. 2 illustrative of the arching of the wries interconnecting the chips and the buses.
FIG. 4 is entirely illustrative of an alternative implementation of primary interest in describing the scope of this invention.
The drawings shows a preferred implementation with four chips 1a, 1b, 1c and 1d, each being a 64K bit semiconductor memory. The memories each may be a conventional random access memory (RAM) or a conventional read only memory (ROS) or some modification of such memories. Chips 1a-1d have a number of chip pads 3, some of which receive and transmit single bits as data and others of which receive single bits as address signals. These pads in this case being connected to common buses 5a and 5b. Other of chip pads 3 receive a chip select signal, as is conventioanl, which selects or activates one of the chips 1a, 1b, 1c and 1d, while the remaining three chips are not activated. In this preferred embodiment, the chip select lines are positioned within bus 5b thereby permitting their convenient location with respect to its associated chip pads 3.
More specifically, chips 1a-1d comprise RAM memories and each chip 1a-1d has a pad 3 which receives a read/write signal, as is conventional, to differentiate between a read operation, which extracts data from the RAM, and a write operation, which alters the contents stored. The read/write select pad 3 is connected to a line in one of the buses 5a and 5b.
In the implementation shown, each chip 1a-1d has eight data pads 3, thirteen address pads 3, one chip-select pad 3, and one read/write select pad 3. No effort is made in this description to describe comprehensively which of the pads 3 is connected for each of the foregoing operations, as this invention is not at all dependent upon the function of the signals on the chip pads 3 and as that may vary depending on the design of the chips 1a-1d. Additionally, each chip 1a-1d is designed to receive operating voltage on one pad 3V and to be connected to a ground reference voltage on another pad 3G. The pads 3G for ground and 3V for operating voltage are in the middle area of the line of pads 3 on the margin of each chip 1a-1d. The specific aspects of this embodiment permit the operating voltage and ground to be at the outer side of the buses 5a and 5b on the circuit board 6.
Chips 1a-1d are mounted on a circuit board 6 in a line with their opposite margins 7a and 7b parallel to that line. Margins 7a and 7b contain pads 3, typically about half on the one margin 7a and half on one margin 7b. The physical mounting of chips 1a-1d may be by electrically conductive adhesive or the like, as is conventional. Chips 1a-1d are positioned on an underlying conductive layer 8, which during operation is held at a predetermined substrate voltage, as is conventional. Generally parallel to the line of chips 1a-1d and printed on board 6 is bus 5a of conductors on the side near margin 7a and the bus 5b on the side near margins 7b, as is conventional.
FIG. 2 is a more magnified illustration of one of the chips, in this case chip 1c as connected to buses 5a and 5b. Buses 5a and 5b each comprise 13 lines, 9a through 9m for bus 5aand 11a-11m for bus 5b, the outer line 9m being the operating voltage line and the outer line 11m being the ground line, and therefore being large in area to provide shielding as is conventional. Line 12 within bus 5b is the chip select line for that chip and therefore does not extend further toward chip 1b. Bus 5b will not be further mentioned in detail since discussion of bus 5a is directly applicable to bus 5b for the purposes of this invention. The wide region 14 above bus 5a is also conductive and held at ground during operation to provide shielding.
Referring again to FIG. 1, buses 5a and 5b have wider portions 13 which serve as terminals or pads. The wide portions provide area necessary to permit an end of wires 15 to be bonded to pads 13. The other ends of wire 15 are bonded to a pads 3 on chips 1a-1d.
Board pads 13 have a long axis along which wires 15 are bonded. As wires 15 are not wide, pads 13 need not be wide in the direction transverse to bonding. Accordingly, the preferred pad 13 has a long, bonding axis pointing at a corresponding chip pad 3 and a narrower dimension transverse to the bonding axis. The narrow transverse dimension conserves space. Individual ones of wires 15 connect one pad 3 on one chip 1a-1d to one pad 13 of buses 5a or 5b which is pointed toward that pad 3. (Identical connections are made to the chip-select line, which, in fact, are located within bus 5b.) Wires 15 extend over intermediate circuit elements and are sufficiently rigid as to not sag onto the board, thereby making an undesired electrical contact. Thus, for example, as illustrated by the cross-sectional view of FIG. 3, the wire denoted 15f extends over lines 9a-9k, and terminates on the pad 13f of line 91.
After fabrication of all connections of wires 15 to chip pads 3 and substrate pads 13, that part of the assembly including wires 15, pads 3, pads 13 and chips 1a-1d is covered with a passivation agent. The efficiency of the completed assembly requires that a seal against moisture and ionic contaminants (typically chlorine and potassium) be provided at the outer surface of chips 1 and wires 15 as well as the interstitial zones. Typically a high purity, low terminal expansion epoxy material is applied as a liquid and hardened in place. Such conventional practice is effective only if a stress relief zone or open space is provided between chips 1a-1d to minimize the cumulative thermal strains created by the different thermal coefficients of expansion of the encapsulated components working against the encapsulation material.
Less common but still conventional is the application of a thin conformal coating as a passivation agent, which surrounds individual elements rather than encapsulating groups of them. Such fabrication, including the connection of arched wires 15 followed by passivation, may be conventional and forms no part of this invention.
In the more enlarged illustration of FIG. 2, pads 13 of bus 5a are denominated pads 13a through 13m to facilitate discussion. Similarly chip pads 3 of margin 7a are denominated pads 3a through 3f, 3V, and 3h through 3m, the pad 3V being given a designation relating to its function of receiving the operating voltage. Wires 15 are similarly denominated. Accordingly, pads 3a and 13a are connected by arched wire 15a. Pads 3b and 13b are connected by wire 15b, with the other connection following that patten, pad 3V being connected to pad 13g by wire 15g.
Preferably the long, bonding axis of each board pad 13a-13m is directed toward or aimed at the associated chip pad 3a-3f, 3V and 3h-3m, to which it is connected by the corresponding wire 15a-15m. this aiming provides the longest effective area for bonding of the end of the corresponding wire 15a-15m, and minimizes the potential of wire sag producing a short with adjacent bus lines or pads. Pads 13 are made significantly wider than wires 9, such width and aiming of the long axis being desirable in the conventional practice of chip wirebonding.
The outermost pad 13g is generally central to chip 1c and therefore its long axis is generally perpendicular to the line of chips 1a-1d (FIG. 1). Pad 13g therefore takes the maximum space across the width of bus 5a. The other pads, 13a-13f and 13h-13m are the same size as pad 13g but are not perpendicular to the line of chip 1a-1d and therefore require somewhat less space across the width of bus 5a.
Pads 13 are located close to chips 1a-1d to minimize the length of wires 15. in the preferred embodiment illustrated in FIG. 1 and 2, the space available for buses 5a 5b permits a wider separation between the individual line 9a-9m and 11a-11m than the minimum possible without interline short circuits and the like. The wider spacing is normally more reliable and less costly to fabricate, so the lines such as lines 9a-9m are more widely spaced in the region between chips 1a-1d. The region proximate or closest to the chips 1a-1d, that at which the pads 13a-13m of FIG. 2 are located, have lines 9a-9m as closely spaced as possible. This locates pads 13a-13m as close to chip 1c as possible. The wide spacing is achieved by having line 9a intersect pad 13m somewhat internal to its long axis and parallel to the line of chips 1a-1d. Line 9c intersects pad 131 at the outer end of its long axis and parallel to the line of chips 1a-1d. Lines 9e, 9g, 9i and 9h have progressively longer parts extending in the direction of the long axis of the one of pads 13k, 13j, 13i and 13h, respectively, to which each connects, followed by parts parallel to the line of chips 1a-1d. The section having pads 13a-13f has essentially the same configuration, with line 9b intersecting pad 13a somewhat internal of its long axis and line 91 having the longest part extending in the direction of the long axis of the pad 13 to which it connects.
Lines 9a through 9m, with the exception of line 9m, the outer line, are connected to opposite ends of the long axis of the corresopnding pads 13a-13f and 13h-13m to which they connect. The pads 13a-13f and 13h-13m are part of the electrical continuity of bus 5a. Line 9a, the line closest to chip 1c contacts pad 13m at the end of pad 13m farthest from chip 1c. Line 9a is connected to the opposite side of pad 13m and therefore has a length extending across the middle region of chip 1c which is displaced toward chip 1c an amount equal to the component of the length of pad 13m which is perpendicular to the line of chips 1a-1d. The next line, line 9b, finds no pad near pad 13m, but has a part 17b generally following pad 13m so as to be substantially spaced from the edge of pad 13m, thereby also displacing line 9b toward chip 1b. This pattern is repeated to pad 13h. Thus, line 9c connects to the end of pad 131 more distant from chip 1c and connects to the opposite end of pad 131 from which line 9c extends across the middle of chip 1c. Line 9b does not connect to a pad, but has a part 17d which generally folows pad 131 and is spaced from it. This relationship continues through pad 13g of line 9m with the exception that line 9m connects only to the outer side of pad 13g.
The group of pads 13m, 13l, 13k, 13j, 13i, and 13h along with parts 17b, 17d, 17f, 17h, 17j and 17l form a section in which lines 9a-9l are spaced and approximately in parallel and are one distance from the line of chips 1a-1d on one side of the pads 13h-13m and are displaced a different distance from the line of chips 1a-1d, on the other side of those pads. The amount of the displacement is that of the section containing pads 13m, 13l, 13k, 13j, 13i and 13h and parts 17b, 17d, 17f, 17h, 17i and 17l which has a direction toward the line of chips 1a-1d.
More specifically, in FIG. 2 those lines in bus 5a are closer to the chip 1c in the central part to the left of the pads 13h-13m. On the other side of chip 1c is a basically similar section having lines pads 13a-13f and parts 17a, 17c, 17e, 17g, 17i and 17k between and alternating with the pads 13a-13f. The middle expanse of lines 9a-9l contact the bottom of pads 13a-13f or parts 17a, 17c, 17e, 17g, 17i and 17k where there is no pad. This reverses the displacement of the adjoining section, resulting in lines 9a-9l being displaced outward perpendicular from the line of chips 1a-1d the same amount as the previous inward displacement of lines 9a-9l in the region central and proximate to chip 1c.
The lines 9a-9m and pads 13a-13m, may be as close together at every point as the minimum interline spacing allowed by the technology involved. They avoid contact by being displaced as groups. As the sections having displacement toward and away from the chips alternate (FIG. 1), the total minimum required area need be expanded ony by the length of the longest component of all the pads 13a-13m which is perpendicular to the line of chips 1a-1d. As discussed above, the embodiment shown permits extra spacing between the lines 9a-9m in the regions between chips 1a-1d. To utilize this as described, the sections having displacement generally contain both pads 13a-13m and parts of lines 9c-9m extending in the same direction as the long axis of the pads 13a-13m to which each line connects. Where use of space on board 6 is to be minimized, the parts of lines 9c-9m extending past the pads 13 and in the direction of the long axis of pads 13 would be eliminated. The interline spacing of line 9a-9m in the regions between chips 1a-1d would then be as close as that in the regions proximate to chips 1a-1d.
It will be noted that where a line, such as line 9a, is displaced in one direction, this need not influence other lines which are positioned away from the direction of displacement. It is for this reason that line 9m simply connects to the end of pad 13g farthest from chip 1c and has a single part extending across the line of chips 1a-1d spaced a fixed distance from the line of chips 1a-1d. The continuing outward position may be maintained as there is no line farther outward to be influenced.
This preferred arrangement of lines 9 containing parts 17 and pads 13 is provided for the purpose of minimizing the maximum length of wires 15, the longest being wire 15g. The length of wire 15g is a function of the number and center-to-center spacing of lines 9 in the area between pad 13g and chip 1c. Such spacing is dependent upon the width of the lines 9 and the spacing between lines 9, as well as the distance between the edge of bus 5a and the adjoining one of chips 1a-1d. As refinements permit reduced spacing of these elements, the distance between pad 13g and chip 1c will be reduced and as a result wire 15g will be made shorter. This is attractive, because shorting possibilities are reduced, as has been noted, and problems related to solid passivations can be minimized.
In the FIG. 4 arrangement, all of the pads 13a through 13m are contiguous and form a group of pads in a section which displaces the location of lines 9a-9l from the margin 7a of chip 1c. All of the displacement parts 17a-17l form a group opposite the group of pads 13a-13m. As shown, pads 13a through 13m occupy most of the space near chip 1c, but the lesser space for the section of parts 17a-17l having a return displacement normally would be availavle prior to the area needed for a displacement section of pads 13 related to the adjoining chip 1b.
It will be apparent that alternative configurations may be adopted without departing from the essential aspects of this invention. Accordingly, patent coverage should be as provided by law, with particular reference to the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3562592 *||24 Apr 1969||9 Feb 1971||Int Standard Electric Corp||Circuit assembly|
|US3716761 *||3 May 1972||13 Feb 1973||Microsystems Int Ltd||Universal interconnection structure for microelectronic devices|
|US4289384 *||30 Apr 1979||15 Sep 1981||Bell & Howell Company||Electrode structures and interconnecting system|
|US4513555 *||27 Dec 1982||30 Apr 1985||Lawrence Brothers, Inc.||Barn door framing system|
|GB847735A *||Title not available|
|JPS5796561A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4752862 *||20 Dec 1985||21 Jun 1988||Seiko Instruments & Electronics Ltd.||Electronic device|
|US4934045 *||30 Jan 1989||19 Jun 1990||Semiconductor Energy Laboratory Co., Ltd.||Method of producing electric circuit patterns|
|US4942400 *||9 Feb 1990||17 Jul 1990||General Electric Company||Analog to digital converter with multilayer printed circuit mounting|
|US5012213 *||19 Dec 1989||30 Apr 1991||Motorola, Inc.||Providing a PGA package with a low reflection line|
|US5025555 *||19 Mar 1990||25 Jun 1991||Semiconductor Energy Laboratory Co., Ltd.||Method of producing electric circuit patterns|
|US5072519 *||19 Mar 1990||17 Dec 1991||Semiconductor Energy Laboratory Co., Ltd.||Method of producing electric circuit patterns|
|US5095407 *||23 Aug 1989||10 Mar 1992||Hitachi, Ltd.||Double-sided memory board|
|US5208729 *||14 Feb 1992||4 May 1993||International Business Machines Corporation||Multi-chip module|
|US5266833 *||30 Mar 1992||30 Nov 1993||Capps David F||Integrated circuit bus structure|
|US5373114 *||3 May 1993||13 Dec 1994||Stanley Electric Co., Ltd.||Circuit substrate|
|US5534729 *||17 Feb 1995||9 Jul 1996||Texas Instruments Incorporated||Integrated circuit lead frame for coupling to non-neighboring bond pads|
|US6370766 *||28 Feb 1997||16 Apr 2002||Lucent Technologies Inc.||Manufacture of printed circuit cards|
|US6420658 *||30 Nov 1999||16 Jul 2002||Oki Electric Industry Co., Ltd.||Module circuit board for semiconductor device having barriers to isolate I/O terminals from solder|
|US6498306 *||20 Dec 2001||24 Dec 2002||Oki Electric Industry Co., Ltd.||Module circuit board for semiconductor device having barriers to isolate I/O terminals from solder|
|US6703567 *||29 May 2001||9 Mar 2004||Infineon Technologies Ag||Conductor track layer structure and prestage thereof|
|US6812555 *||10 Mar 2003||2 Nov 2004||Everstone Industry Corp.||Memory card substrate with alternating contacts|
|US6833509||7 Nov 2002||21 Dec 2004||Oki Electric Industry Co., Ltd.||Module circuit board for semiconductor device having barriers to isolate I/O terminals from solder|
|US7247800||11 Feb 2004||24 Jul 2007||Oki Electric Industry Co., Ltd.||Module circuit board for semiconductor device having barriers to isolate I/O terminals from solder|
|US20030102155 *||7 Nov 2002||5 Jun 2003||Norio Takahashi||Module circuit board for semiconductor device having barriers to isolate I/O terminals from solder|
|US20040178513 *||10 Mar 2003||16 Sep 2004||Everstone Industry Corp.||Memory card substrate with alternating contacts|
|US20050274541 *||11 Feb 2004||15 Dec 2005||Norio Takahashi||Module circuit board for semiconductor device having barriers to isolate I/O terminals from solder|
|U.S. Classification||361/775, 361/767, 174/261, 361/748, 361/774, 257/691|
|Cooperative Classification||H01L2924/3025, H01L24/85, H01L2924/00014, H01L2924/01013, H01L24/49, H01L2224/85, H01L2924/01019, H01L2924/01057, H01L2924/01033, H01L2224/48247, H01L2224/48227, H01L2924/14, H01L2224/49171, H01L2924/01082|
|European Classification||H01L24/85, H01L24/49|
|14 Jan 1985||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:EDWARDS, JOHN C.;REEL/FRAME:004415/0712
Effective date: 19850114
|17 Aug 1989||FPAY||Fee payment|
Year of fee payment: 4
|15 Jul 1993||FPAY||Fee payment|
Year of fee payment: 8
|2 Sep 1997||FPAY||Fee payment|
Year of fee payment: 12