|Publication number||US4333142 A|
|Application number||US 06/056,909|
|Publication date||1 Jun 1982|
|Filing date||12 Jul 1979|
|Priority date||22 Jul 1977|
|Publication number||056909, 06056909, US 4333142 A, US 4333142A, US-A-4333142, US4333142 A, US4333142A|
|Inventors||Gilman D. Chesley|
|Original Assignee||Chesley Gilman D|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Referenced by (62), Classifications (16)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a division, of application Ser. No. 818,235 filed July 22, 1977.
This invention pertains generally to computer and memory systems and more particularly to a self-configurable computer and memory system formed on a single wafer.
Computer systems are commonly created by interconnecting smaller modules such as CPU's, memory modules, and input/output controllers. These modules are often interconnected by a common bus which carries the full word data and memory address data in parallel.
In recent years, large scale integration (LSI) has been developed to the point where the modules can be integrated on a single chip, e.g., microprocessor CPU's. Thus, using LSI modules and a common bus for interconnection, a complete computer system can be constructed on a wafer. However, a potential problem exists because a bad LSI module can cause the entire wafer computer system to malfunction. Thus, redundant modules must be present on the wafer, and means for testing and avoiding bad modules must be provided.
Prior art techniques such as discretionary wiring, pad relocation, probe testing and computer mask generation might be used. However, these techniques have the disadvantage of high cost and inflexibility when other circuits fail in use.
The invention provides a self-configurable computer and memory system in which a plurality of CPU, ROM, and RAM modules are formed on a semiconductor wafer. A first one of the CPU's is used for testing the ROM's until a good ROM is found. The CPU's are then tested with a program from the good ROM until a good CPU is found, and then the RAM's are tested with the good CPU and ROM. Data indicating the condition of the RAM's is stored in a table formed in the CPU registers or in one of the RAM's or in another suitable store. Memory space is allocated on a page basis, with each memory chip constituting one page.
It is in general an object of the invention to provide a new and improved computer and memory system and method of configuring the same.
Another object of the invention is to provide a system and method of the above character in which the computer and memory system is self-configurable.
Additional objects and features of the invention will be apparent from the following description in which the preferred embodiments are set forth in detail in conjunction with the accompanying drawings.
FIG. 1 is a block diagram of one embodiment of a computer and memory system according to the invention.
FIG. 2 is a block diagram of one of the CPU modules of the computer and memory system of FIG. 1.
FIG. 3 is a block diagram of one of the ROM modules of the computer and memory system of FIG. 1.
FIG. 4 is a block diagram of one of the RAM modules of the computer and memory system of FIG. 1.
As illustrated in FIG. 1, the computer and memory system is constructed in integrated form on a semiconductor wafer 11. The system includes a plurality of CPU modules 12, ROM modules 13 and RAM modules 14. In the embodiment illustrated, four CPU modules and four ROM modules are provided, although a greater or lesser degree of redundancy can be provided if desired. In this embodiment, 252 RAM modules are provided. The CPU, ROM and RAM modules are all interconnected by a common bus 16 which is also accessible externally of the wafer.
Referring now to FIG. 2, each of the CPU modules is formed on a separate chip 21 and includes a central processing unit 22 which, in the preferred embodiment, comprises a standard 8-bit microprocessor with a standard instruction set. The CPU has I/O STROBE lines 23, a MEMORY STROBE output 24, and a WRITE output 26. Word address and input and output data pass to and from the CPU on common bus 16, and chip address signals are provided on CHIP ADDRESS lines 27. The CPU module also includes an address register 28 which can be used either for storing the address of the first good RAM module or for storing a table of the good RAM's.
Each CPU module also includes a START IN line 31 which is connected to the input of a delay circuit 32. The output of the delay circuit is connected to one input of an AND gate 33, and the output of this gate is connected to a START OUT line 34. As illustrated in FIG. 1, the START OUT line of each CPU module is connected to the START IN line of the next successive CPU module.
Within each of the CPU modules, START IN line 31 is also connected to the SET input of a flip flop 36 and to the CPU itself. The RESET input of flip flop 36 is connected to the output and gate 33, and the output of flip flop 36 is connected to the OUTPUT ENABLE input of the CPU. AND gate 33 receives a second input from a START INHIBIT flip flop 37, which received a SET input from the CPU only if the CPU tests satisfactorily.
In operation, flip flops 36, 37 are both in the cleared state initially, the START signal is applied simultaneously to delay circuit 32, to the SET input of flip flop 36, and to the CPU. With flip flop 36 in its SET condition, the output lines of the CPU are enabled. If the CPU tests satisfactorily, a SET signal is delivered to flip flop 37 upon completion of the testing. With flip flop 37 set, the START signal which emerges from delay circuit 32 cannot pass through AND gate 33, and flip flop 36 remains in its SET condition. If the CPU has not tested satisfactorily by the time the START signal emerges from the delay circuit, this signal passes through gate 33 to the next CPU module. The START signal on output line 34 resets flip flop 36, thereby disabling the output lines of that CPU.
As illustrated in FIG. 3, each of the ROM modules 13 is formed on a separate chip 41 and includes a read only memory 42 of conventional design. In the embodiment illustrated, the ROM is organized in 256 words of 8-bits each, and it utilizes common bus 16 for both word address and for data in and data out. Each ROM module has a unique prewired chip address 40 and an address comparator 43 which compares this address with the chip addresses generated by the CPU on lines 27. When the address from the CPU matches the prewired address of the chip, an ENABLE signal is applied to the ROM by the address comparator via line 44. Each ROM receives MEMORY STROBE signals on line 24.
Each ROM module contains an identical copy of a CPU and RAM test program as well as other desired service routines, with the addresses shifted to reflect the proper module addresses. In addition, the last word of each ROM module contains a check sum of all of the other words of the module so that a CPU can perform a simple test function, in this case summation, upon all words of the ROM to verify that the ROM is operating correctly. This check sum routine is permanently built into the logic of each CPU.
As illustrated in FIG. 4, RAM modules 14 are generally similar to ROM modules 13, except that they include a read/write memory. Each of the RAM modules is formed on a separate chip 51 and includes a standard random access memory 52 organized in 256 words of 8-bits each. Each RAM module has a unique prewired address 50 and an address comparator 53 which compares this address with the chip addresses from the CPU. The output of the comparator is connected to the ENABLE input of the RAM by a line 54. The WRITE signals from the CPU are applied to the RAM via line 26.
Operation and use of the computer and memory system, and therein the method of the invention are as follows. Whenever power is applied to the wafer, a START signal is applied to the first CPU. Upon receipt of the START signal, the CPU accesses the words of the first ROM then adds them together and compares the result with the final word containing the check sum. If this test fails, it is performed upon the next ROM in turn. When a good ROM is found, the CPU test routine contained within the ROM is executed by the CPU to determine if the CPU is good. If both the ROM and the CPU test satisfactorily, the START INHIBIT flip flop is turned on or set, thereby preventing the passage of the START signal to the next CPU. If the first CPU does not test satisfactorily or cannot find a good ROM, the START signal passes to the next CPU. The process continues until a good ROM and a good CPU are found. If neither can be found, the wafer is discarded.
Once a good ROM and a good CPU are found, the CPU uses a RAM test routine contained in the ROM to test each RAM module in sequence. The address of the first good RAM module is stored in register 28, and a table of the addresses of the good and bad RAM's is created in the first good RAM. Alternatively, the table of good and bad RAM address can be maintained in register 28.
The RAM's are utilized as a page allocated memory system in which data and program space is allocated on demand on a page basis, with each RAM module corresponding to one page. Space is de-allocated on the same basis when it is no longed needed. In this embodiment, a page contains 256 8-bit words. Bad RAM modules are simply treated as permanently allocated and unavailable as pages.
It is apparent from the foregoing that a new and improved computer system and method of configuring the same have been provided. While only the presently preferred embodiments have been described in detail, as will be apparent to those familiar with the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.
For example, as technology permits, larger word widths and different degrees of module redundancy may be used. Furthermore, other modules such as I/O controllers may be included on the wafer using the described test and configure technique. Also, the separate ROM modules may be eliminated by embedding them in the CPU's in the form of ROM's, PLA's, or wired-in test sequences. In this case, separate ROM testing could be eliminated. If the CPU and ROM are located off the wafer, there is no need for redundancy of these units.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3659088 *||6 Aug 1970||25 Apr 1972||Cogar Corp||Method for indicating memory chip failure modes|
|US3704363 *||9 Jun 1971||28 Nov 1972||Ibm||Statistical and environmental data logging system for data processing storage subsystem|
|US3758761 *||17 Aug 1971||11 Sep 1973||Texas Instruments Inc||Self-interconnecting/self-repairable electronic systems on a slice|
|US3838260 *||22 Jan 1973||24 Sep 1974||Xerox Corp||Microprogrammable control memory diagnostic system|
|US3913072 *||23 Jul 1973||14 Oct 1975||Catt Ivor||Digital integrated circuits|
|US3917933 *||17 Dec 1974||4 Nov 1975||Sperry Rand Corp||Error logging in LSI memory storage units using FIFO memory of LSI shift registers|
|US3999051 *||28 Mar 1975||21 Dec 1976||Sperry Rand Corporation||Error logging in semiconductor storage units|
|US4038648 *||3 Jun 1974||26 Jul 1977||Chesley Gilman D||Self-configurable circuit structure for achieving wafer scale integration|
|US4058851 *||18 Oct 1976||15 Nov 1977||Sperry Rand Corporation||Conditional bypass of error correction for dual memory access time selection|
|US4066880 *||30 Mar 1976||3 Jan 1978||Engineered Systems, Inc.||System for pretesting electronic memory locations and automatically identifying faulty memory sections|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4441075 *||2 Jul 1981||3 Apr 1984||International Business Machines Corporation||Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection|
|US4527115 *||22 Dec 1982||2 Jul 1985||Raytheon Company||Configurable logic gate array|
|US5243703 *||5 Mar 1992||7 Sep 1993||Rambus, Inc.||Apparatus for synchronously generating clock signals in a data processing system|
|US5276893 *||8 Feb 1989||4 Jan 1994||Yvon Savaria||Parallel microprocessor architecture|
|US5319755 *||30 Sep 1992||7 Jun 1994||Rambus, Inc.||Integrated circuit I/O using high performance bus interface|
|US5430676 *||25 Feb 1994||4 Jul 1995||Rambus, Inc.||Dynamic random access memory system|
|US5434817 *||3 Nov 1994||18 Jul 1995||Rambus, Incorporated||Dynamic random access memory system|
|US5473575 *||5 Mar 1992||5 Dec 1995||Rambus, Inc.||Integrated circuit I/O using a high performance bus interface|
|US5499385 *||5 Mar 1992||12 Mar 1996||Rambus, Inc.||Method for accessing and transmitting data to/from a memory in packets|
|US5511024 *||25 Feb 1994||23 Apr 1996||Rambus, Inc.||Dynamic random access memory system|
|US5513327 *||31 Mar 1994||30 Apr 1996||Rambus, Inc.||Integrated circuit I/O using a high performance bus interface|
|US5583987 *||21 Dec 1994||10 Dec 1996||Mitsubishi Denki Kabushiki Kaisha||Method and apparatus for initializing a multiprocessor system while resetting defective CPU's detected during operation thereof|
|US5587962 *||7 Jun 1995||24 Dec 1996||Texas Instruments Incorporated||Memory circuit accommodating both serial and random access including an alternate address buffer register|
|US5606717 *||5 Mar 1992||25 Feb 1997||Rambus, Inc.||Memory circuitry having bus interface for receiving information in packets and access time registers|
|US5636176 *||22 Dec 1994||3 Jun 1997||Texas Instruments Incorporated||Synchronous DRAM responsive to first and second clock signals|
|US5638334 *||24 May 1995||10 Jun 1997||Rambus Inc.||Integrated circuit I/O using a high performance bus interface|
|US5657481 *||15 Nov 1996||12 Aug 1997||Rambus, Inc.||Memory device with a phase locked loop circuitry|
|US5680358 *||7 Jun 1995||21 Oct 1997||Texas Instruments Incorporated||System transferring streams of data|
|US5680367 *||7 Jun 1995||21 Oct 1997||Texas Instruments Incorporated||Process for controlling writing data to a DRAM array|
|US5680368 *||7 Jun 1995||21 Oct 1997||Texas Instruments Incorporated||Dram system with control data|
|US5680369 *||7 Jun 1995||21 Oct 1997||Texas Instruments Incorporated||Synchronous dynamic random access memory device|
|US5680370 *||7 Jun 1995||21 Oct 1997||Texas Instruments Incorporated||Synchronous DRAM device having a control data buffer|
|US5684753 *||7 Jun 1995||4 Nov 1997||Texas Instruments Incorporated||Synchronous data transfer system|
|US5768205 *||7 Jun 1995||16 Jun 1998||Texas Instruments Incorporated||Process of transfering streams of data to and from a random access memory device|
|US5805518 *||7 Jun 1995||8 Sep 1998||Texas Instruments Incorporated||Memory circuit accommodating both serial and random access, having a synchronous DRAM device for writing and reading data|
|US5809263 *||9 Dec 1996||15 Sep 1998||Rambus Inc.||Integrated circuit I/O using a high performance bus interface|
|US5915105 *||26 Nov 1997||22 Jun 1999||Rambus Inc.||Integrated circuit I/O using a high performance bus interface|
|US5928343 *||16 Jun 1998||27 Jul 1999||Rambus Inc.||Memory module having memory devices containing internal device ID registers and method of initializing same|
|US5954804 *||10 Feb 1997||21 Sep 1999||Rambus Inc.||Synchronous memory device having an internal register|
|US5983320 *||13 Aug 1997||9 Nov 1999||Rambus, Inc.||Method and apparatus for externally configuring and modifying the transaction request response characteristics of a semiconductor device coupled to a bus|
|US5991841 *||24 Sep 1997||23 Nov 1999||Intel Corporation||Memory transactions on a low pin count bus|
|US6119189 *||24 Sep 1997||12 Sep 2000||Intel Corporation||Bus master transactions on a low pin count bus|
|US6131127 *||24 Sep 1997||10 Oct 2000||Intel Corporation||I/O transactions on a low pin count bus|
|US6157970 *||24 Sep 1997||5 Dec 2000||Intel Corporation||Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number|
|US6188635||7 Jun 1995||13 Feb 2001||Texas Instruments Incorporated||Process of synchronously writing data to a dynamic random access memory array|
|US6418078||21 Dec 2000||9 Jul 2002||Texas Instruments Incorporated||Synchronous DRAM device having a control data buffer|
|US6598171||28 Mar 1997||22 Jul 2003||Rambus Inc.||Integrated circuit I/O using a high performance bus interface|
|US6662291||5 Jul 2002||9 Dec 2003||Texas Instruments Incorporated||Synchronous DRAM System with control data|
|US6728828||23 May 2003||27 Apr 2004||Texas Instruments Incorporated||Synchronous data transfer system|
|US6728829||30 May 2003||27 Apr 2004||Texas Instruments Incorporated||Synchronous DRAM system with control data|
|US6732224||30 May 2003||4 May 2004||Texas Instrument Incorporated||System with control data buffer for transferring streams of data|
|US6732225||2 Jun 2003||4 May 2004||Texas Instruments Incorporated||Process for controlling reading data from a DRAM array|
|US6732226||2 Jun 2003||4 May 2004||Texas Instruments Incorporated||Memory device for transferring streams of data|
|US6735667||30 May 2003||11 May 2004||Texas Instruments Incorporated||Synchronous data system with control data buffer|
|US6735668||2 Jun 2003||11 May 2004||Texas Instruments Incorporated||Process of using a DRAM with address control data|
|US6738860||30 May 2003||18 May 2004||Texas Instruments Incorporated||Synchronous DRAM with control data buffer|
|US6748483||2 Jun 2003||8 Jun 2004||Texas Instruments Incorporated||Process of operating a DRAM system|
|US6895465||31 Mar 2004||17 May 2005||Texas Instruments Incorporated||SDRAM with command decoder, address registers, multiplexer, and sequencer|
|US6910096||2 Jun 2003||21 Jun 2005||Texas Instruments Incorporated||SDRAM with command decoder coupled to address registers|
|US6993692||30 Jun 2003||31 Jan 2006||International Business Machines Corporation||Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories|
|US7209997||20 Nov 2003||24 Apr 2007||Rambus Inc.||Controller device and method for operating same|
|US7424659 *||31 Oct 2003||9 Sep 2008||Sandisk Il Ltd.||System-in-package and method of testing thereof|
|US7730368||5 Apr 2006||1 Jun 2010||Sandisk Il Ltd.||Method, system and computer-readable code for testing of flash memory|
|US7743293 *||24 Jul 2008||22 Jun 2010||Sandisk Il Ltd.||System-in-package and method of testing thereof|
|US8069380||7 Apr 2010||29 Nov 2011||Sandisk Il Ltd.||Method, system and computer-readable code to test flash memory|
|US20040186950 *||31 Mar 2004||23 Sep 2004||Masashi Hashimoto||Synchronous DRAM system with control data|
|US20040268198 *||30 Jun 2003||30 Dec 2004||International Business Machines Corporation||Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories|
|US20050149780 *||31 Oct 2003||7 Jul 2005||M-Systems Flash Disk Pioneers, Ltd.||System-in-package and method of testing thereof|
|US20080313511 *||24 Jul 2008||18 Dec 2008||Sandisk Il Ltd.||System-in-package and method of testing thereof|
|US20100199135 *||5 Aug 2010||SANDISK IL LTD. (formerly M-SYSTEMS FLASH DISK PIONEERS LTD.)||Method, system and computer-readable code to test flash memory|
|WO1991016680A1 *||16 Apr 1991||31 Oct 1991||Rambus Inc||Integrated circuit i/o using a high preformance bus interface|
|WO2005043276A2 *||13 Oct 2004||12 May 2005||Meir Avraham||System-in-package and method of testing thereof|
|U.S. Classification||716/136, 711/E12.087|
|International Classification||G06F15/177, G06F12/06, G01R31/3185, G11C29/00|
|Cooperative Classification||G11C29/006, G01R31/318511, G06F12/0669, G01R31/318505, G06F15/177|
|European Classification||G06F15/177, G01R31/3185M, G11C29/00W, G01R31/3185M3, G06F12/06K4|