US4301451A - Erasure method for memory-type EL display devices - Google Patents

Erasure method for memory-type EL display devices Download PDF

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US4301451A
US4301451A US06/100,170 US10017079A US4301451A US 4301451 A US4301451 A US 4301451A US 10017079 A US10017079 A US 10017079A US 4301451 A US4301451 A US 4301451A
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sustaining
active layer
pulses
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pulse
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Gary S. Barta
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Tektronix Inc
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Tektronix Inc
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Priority to GB8034932A priority patent/GB2064861B/en
Priority to DE19803042691 priority patent/DE3042691A1/en
Priority to JP16651480A priority patent/JPS5691293A/en
Priority to FR8025957A priority patent/FR2471643A1/en
Priority to NL8006588A priority patent/NL8006588A/en
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00Electroluminescent light sources
    • H05B33/12Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H05B33/145Arrangements of the electroluminescent material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B44/00Circuit arrangements for operating electroluminescent light sources
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • the present invention relates generally to thin-film electroluminescent (EL) display devices of the type having an inherent "memory", or voltage vs. brightness hysteresis. More particularly, the invention relates to an improved method of erasing such devices.
  • EL electroluminescent
  • U.S. Pat. No. 4,149,108 to I. Chang discloses a multistable cathode-ray tube that uses an a.c. thin-film EL panel as the storage display target.
  • the electroluminescent target of the Chang CRT is addressed directly by the tube's electron beam.
  • U.S. application Ser. No. 922,950, filed July 10, 1978 in my name and assigned to the assignee of the present invention describes an EL storage CRT with a target comprising a double insulated ZnS:Mn thin-film panel having a layer of a UV-emitting phosphor on the input side. Rather than being exposed to direct bombardment by the electron beam the EL panel is addressed by ultraviolet light emitted from the intermediate phosphor layer.
  • the conventional method of erasing an a.c. thin-film EL display panel is to reduce the amplitude of the applied a.c. signal, which is normally maintained at an image-sustaining level Vs, to a value below the extinction voltage Ve of the device. At or below Ve, the a.c. field across the thin-film EL layer is insufficient to maintain luminescence and the entire panel becomes dark, (unwritten).
  • the erase cycle is completed by raising the applied signal potential to Vs, which returns the panel to an erased, ready-to-write condition.
  • the above-described procedure has a significant drawback--a faint, residual image of the previously displayed information often remains when the applied voltage is returned to Vs.
  • the residual image problem can be eliminated by adding a preliminary step to the erasing process: increasing the applied potential to a value Vw high enough to place the entire panel in a bright, fully-written condition. Then, when the a.c. voltage is dropped to Ve and returned to Vs, the panel will be fully erased and free of residual images.
  • the added step produces a momentary bright "flash" that is unpleasant and greatly increases visual fatigue. The effect is particularly objectionable with large size display panels, or displays used in low ambient light conditions.
  • a principal object of the present invention is to meet this need in a practical and satisfactory manner.
  • a more specific object of the invention is to provide a method for erasing memory-type EL panels that results in complete erasure of all previously-displayed information without increasing visual fatigue.
  • Another object of the invention is to provide an erasure method that is simpler and less costly to implement than prior art methods.
  • Still another object of the invention is to provide an improved method of total erasure that does not require any change in the amplitude of the a.c. voltage applied to the panel.
  • a further object of the invention is to provide an improved erasure method that is applicable in all memory-type thin-film EL panel applications.
  • total erasure of a memory-type ZnS:Mn thin-film EL panel is achieved by applying an erase pulse opposite in polarity to the last-preceding pulse or cycle of the sustaining bias signal, and of sufficient amplitude and duration to relax the internal field across the EL layer.
  • the sustaining bias is then reapplied to place the panel in an erased and ready-to-write condition.
  • the polarity of the first sustaining bias pulse or cycle following the erase pulse is unimportant and may be of the same or the opposite polarity.
  • the erase pulse may be of the same amplitude as the pulses of the sustaining bias signal.
  • FIG. 1 is a fragmentary, cross-sectional view of a memory-type electroluminscent display panel
  • FIG. 2 shows a plot of display brightness versus applied voltage for the FIG. 1 EL panel
  • FIG. 3 illustrates the waveform of voltage pulses applied to the FIG. 1 panel during a complete erase cycle
  • FIG. 4 depicts the internal electric field produced in the active layer of the EL panel by application of the FIG. 3 waveform.
  • FIG. 1 shows a thin-film electroluminescent display panel 10 of known construction.
  • Panel 10 includes a transparent first electrode 14 of indium oxide (In 2 O 3 ) or indium-tin oxide (InSnOx) deposited on a planar glass substrate 12.
  • Overlaying electrode 14 is a first insulating layer 16 of a high dielectric strength material such as yttrium oxide (Y 2 O 3 ), silicon nitride (Si 3 N 4 ) or aluminum oxide (Al 2 O 3 ).
  • An active thin-film layer 18 of maganese-activated zinc sulfide (ZnS:Mn) deposited on the first insulating layer is covered by a second insulating layer 20 of Y 2 O 3 or the like.
  • ZnS:Mn maganese-activated zinc sulfide
  • a second electrode 22 overlays insulating layer 20 and completes the basic structure.
  • the fabrication of such panels is conventional, having been described in the above-mentioned Yamauchi et al. paper and numerous subsequent publications, and forms no part of the present invention.
  • a typical thin-film EL panel of the double-insulated described type may be constituted as follows:
  • Such a device emits yellow light when activated, and exhibits a hysteretic luminance vs. voltage behavior that is illustrated (in somewhat idealized form) in FIG. 2.
  • a.c. voltage pulses as from a source 24
  • luminance increases very rapidly as trapped electrons are liberated from the active EL layer. Liberation of the trapped electrons is essentially complete at point "b" on the curve, and further voltage increases (to point "c" and beyond provide only small gains in display brightness.
  • luminance decreases at a slow, or relatively constant rate until a "downward" threshold value is reached at point “d", where trapping rapidly reduces the electrons available for excitation of the Mn atoms. Below point “d”, further small reductions in the applied voltage rapidly decrease the device's luminance, until at point “e” the panel is in a "dark” , or erased, state.
  • a train 30 of sustained, alternating polarity voltage pulses Ps (FIG. 3) of an amplitude Vs is applied to panel 10 by source 24.
  • the value of Vs which may be referred to as the bias voltage, is set in the vicinity of the previously-mentioned upward threshold value.
  • Ls relatively low level
  • areas of the EL layer that are subsequently switched "on" by a writing electron beam, ultraviolet light or a transient voltage pulse settle at a high luminance level, Lw, and are sustained there by the pulses Ps.
  • panel 10 is totally erased without leaving residual images by interrupting the train of sustaining pulses and applying an erase pulse opposite in polarity to the last-preceding pulse Ps.
  • the erase pulse amplitude and duration are selected to produce relaxation of the internal field across EL layer 18.
  • the train of sustaining pulses is reapplied to place the panel in a ready-to-write condition.
  • FIG. 3 A representative erase cycle for a memory-type thin-film EL display panel is shown in FIG. 3. It will be assumed that the panel initially is in a fully written condition, and thus is being sustained at luminance level Lw by the alternating polarity pulses Ps forming pulse train 30. Following a positive sustaining pulse 32, the train is interrupted by a negative erase pulse 34. The amplitude and the duration of the erase pulse are emperically selected to relax the internal field across the thin-film EL layer before the sustaining pulse train is reapplied. To simplify implementation of the method, the amplitude Vr of the erase pulse may be the same as that of the sustaining pulses, but should not exceed Vs. Upon the conclusion of pulse 34, a train of sustaining pulses Ps is reapplied to the display panel. The train may begin with a pulse of either polarity without affecting erasure of the panel.
  • FIG. 4 A plot of the internal electric field in the ZnS:Mn active layer during the FIG. 3 erase cycle is shown in FIG. 4.
  • each sustaining pulse Ps steps the layer's internal field by an amount Es, which adds to the polarization field Ep during the next pulse to enhance luminance.
  • erase pulse 34 steps the internal field by an amount Er. This increases the field, causing the EL layer to emit light and discharge. The higher the field, the greater the emission and the faster the discharge, which reduces the EL layer's internal field.
  • the erase pulse terminates and the next sustain pulse Ps is applied the total field is insufficient to sustain electroluminescence at the Lw level.
  • FIG. 4 plot suggests, as one would expect, that there is a minimum value for Vr, below which erasure does not occur. This value will vary, depending on the construction of the EL panel, and is best determined by trial and error.
  • erasure of an EL panel by the method of the invention is seen as a rapid, complete disappearance of written images without any annoying flash.
  • the described technique is applicable to any type of hysteretic thin-film EL device, including those incorporating a layer of ultraviolet-emitting phosphor overlying the second conductive layer for conversion of incident electrons to UV light.
  • Such a device, used as a CRT storage target, is described in my above-mentioned application, Ser. No. 922,950.
  • One feature of the invention applicable only to a UV-addressed hysteretic EL panel is that writing can take place during the erase pulse. Portions of the panel thus written will remain stored, while all previously written information will be erased.

Abstract

An improved method of completely erasing images stored by memory-type electroluminescent display panels. The method comprises interrupting the a.c. sustaining bias signal normally applied to the panel and impressing an erase pulse that is opposite in polarity to the last-preceding sustaining pulse or cycle. The amplitude and duration of the erase pulse are chosen to effect relaxation of the EL layer's internal field. The sustaining bias signal is then restored to place the panel in an erased, ready-to-write condition.

Description

BACKGROUND AND OBJECTS OF THE INVENTION
The present invention relates generally to thin-film electroluminescent (EL) display devices of the type having an inherent "memory", or voltage vs. brightness hysteresis. More particularly, the invention relates to an improved method of erasing such devices.
Reports of long service life and an inherent memory capability have focused increased attention on a.c.-driven ZnS:Mn thin film EL devices in recent years. The hysteretic behavior of the brightness vs. applied voltage relationship of such devices (which is responsible for the memory effect) was first described by Y. Yamauchi et al. in the 1974 International Electron Devices Meeting Digest, pp. 348-351. Since that time, memory-type ZnS:Mn thin film EL devices have been used in a variety of information display applications. For example, C. Suzuki et al. have published descriptions of X-Y matrix EL panels with inherent memory for displaying alphanumeric characters (1976 S.I.D. International Symposium Digest pp. 50, 51) and television pictures (Information Display, Spring, 1977, pp. 14-19). U.S. Pat. No. 4,149,108 to I. Chang discloses a multistable cathode-ray tube that uses an a.c. thin-film EL panel as the storage display target. The electroluminescent target of the Chang CRT is addressed directly by the tube's electron beam. U.S. application Ser. No. 922,950, filed July 10, 1978 in my name and assigned to the assignee of the present invention, describes an EL storage CRT with a target comprising a double insulated ZnS:Mn thin-film panel having a layer of a UV-emitting phosphor on the input side. Rather than being exposed to direct bombardment by the electron beam the EL panel is addressed by ultraviolet light emitted from the intermediate phosphor layer.
With all such devices there is a need to erase stored information. The conventional method of erasing an a.c. thin-film EL display panel is to reduce the amplitude of the applied a.c. signal, which is normally maintained at an image-sustaining level Vs, to a value below the extinction voltage Ve of the device. At or below Ve, the a.c. field across the thin-film EL layer is insufficient to maintain luminescence and the entire panel becomes dark, (unwritten). The erase cycle is completed by raising the applied signal potential to Vs, which returns the panel to an erased, ready-to-write condition.
Although it is easy enough to do, the above-described procedure has a significant drawback--a faint, residual image of the previously displayed information often remains when the applied voltage is returned to Vs. The residual image problem can be eliminated by adding a preliminary step to the erasing process: increasing the applied potential to a value Vw high enough to place the entire panel in a bright, fully-written condition. Then, when the a.c. voltage is dropped to Ve and returned to Vs, the panel will be fully erased and free of residual images. Unfortunately, however, the added step produces a momentary bright "flash" that is unpleasant and greatly increases visual fatigue. The effect is particularly objectionable with large size display panels, or displays used in low ambient light conditions.
Thus, there is a demonstrated need for an improved method of erasing memory-type electroluminescent display devices--one that is free from the drawbacks of the methods described above. A principal object of the present invention is to meet this need in a practical and satisfactory manner.
A more specific object of the invention is to provide a method for erasing memory-type EL panels that results in complete erasure of all previously-displayed information without increasing visual fatigue.
Another object of the invention is to provide an erasure method that is simpler and less costly to implement than prior art methods.
Still another object of the invention is to provide an improved method of total erasure that does not require any change in the amplitude of the a.c. voltage applied to the panel.
A further object of the invention is to provide an improved erasure method that is applicable in all memory-type thin-film EL panel applications.
SUMMARY OF THE INVENTION
According to a preferred embodiment of the present invention, which is described in greater detail below, total erasure of a memory-type ZnS:Mn thin-film EL panel is achieved by applying an erase pulse opposite in polarity to the last-preceding pulse or cycle of the sustaining bias signal, and of sufficient amplitude and duration to relax the internal field across the EL layer. The sustaining bias is then reapplied to place the panel in an erased and ready-to-write condition. The polarity of the first sustaining bias pulse or cycle following the erase pulse is unimportant and may be of the same or the opposite polarity. For the sake simplicity and convenience, the erase pulse may be of the same amplitude as the pulses of the sustaining bias signal.
Other features, advantages and objects of my invention will be apparent as the following detailed description is read in conjunction with the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a fragmentary, cross-sectional view of a memory-type electroluminscent display panel,
FIG. 2 shows a plot of display brightness versus applied voltage for the FIG. 1 EL panel;
FIG. 3 illustrates the waveform of voltage pulses applied to the FIG. 1 panel during a complete erase cycle; and
FIG. 4 depicts the internal electric field produced in the active layer of the EL panel by application of the FIG. 3 waveform.
DETAILED DESCRIPTION
Referring to the drawings, FIG. 1 shows a thin-film electroluminescent display panel 10 of known construction. Panel 10 includes a transparent first electrode 14 of indium oxide (In2 O3) or indium-tin oxide (InSnOx) deposited on a planar glass substrate 12. Overlaying electrode 14 is a first insulating layer 16 of a high dielectric strength material such as yttrium oxide (Y2 O3), silicon nitride (Si3 N4) or aluminum oxide (Al2 O3). An active thin-film layer 18 of maganese-activated zinc sulfide (ZnS:Mn) deposited on the first insulating layer is covered by a second insulating layer 20 of Y2 O3 or the like. A second electrode 22, suitably of aluminum, overlays insulating layer 20 and completes the basic structure. The fabrication of such panels is conventional, having been described in the above-mentioned Yamauchi et al. paper and numerous subsequent publications, and forms no part of the present invention. By way of example only, a typical thin-film EL panel of the double-insulated described type may be constituted as follows:
______________________________________                                    
Element         Materials  Thickness, A                                   
______________________________________                                    
1st. Electrode 14                                                         
                SnO.sub.2  300-500                                        
1st. Insul. Layer 16                                                      
                Y.sub.2 O.sub.3                                           
                           2000-3000                                      
Active Layer 18 Zns:Mn     3500-7000                                      
2nd Insul. Layer 20                                                       
                Y.sub.2 O.sub.3                                           
                           2000-3000                                      
2nd Electrode 22                                                          
                Al          400-1000                                      
______________________________________                                    
Such a device emits yellow light when activated, and exhibits a hysteretic luminance vs. voltage behavior that is illustrated (in somewhat idealized form) in FIG. 2. As the peak amplitude of applied a.c. voltage pulses (as from a source 24) is increased, there is a slow increase in emitted light until the voltage exceeds a certain threshold value, indicated at point "a" on the curve. Above this "upward" threshold value, luminance increases very rapidly as trapped electrons are liberated from the active EL layer. Liberation of the trapped electrons is essentially complete at point "b" on the curve, and further voltage increases (to point "c" and beyond provide only small gains in display brightness. Upon reducing the amplitude of the applied voltage pulses, luminance decreases at a slow, or relatively constant rate until a "downward" threshold value is reached at point "d", where trapping rapidly reduces the electrons available for excitation of the Mn atoms. Below point "d", further small reductions in the applied voltage rapidly decrease the device's luminance, until at point "e" the panel is in a "dark" , or erased, state.
For operation as a storage display device, a train 30 of sustained, alternating polarity voltage pulses Ps (FIG. 3) of an amplitude Vs is applied to panel 10 by source 24. The value of Vs, which may be referred to as the bias voltage, is set in the vicinity of the previously-mentioned upward threshold value. Before information is written on the panel, its luminance is sustained by the pulse train at a relatively low level, Ls, as shown in FIG. 2. Areas of the EL layer that are subsequently switched "on" by a writing electron beam, ultraviolet light or a transient voltage pulse settle at a high luminance level, Lw, and are sustained there by the pulses Ps.
According to the present invention, panel 10 is totally erased without leaving residual images by interrupting the train of sustaining pulses and applying an erase pulse opposite in polarity to the last-preceding pulse Ps. The erase pulse amplitude and duration are selected to produce relaxation of the internal field across EL layer 18. Following the erase pulses, the train of sustaining pulses is reapplied to place the panel in a ready-to-write condition.
A representative erase cycle for a memory-type thin-film EL display panel is shown in FIG. 3. It will be assumed that the panel initially is in a fully written condition, and thus is being sustained at luminance level Lw by the alternating polarity pulses Ps forming pulse train 30. Following a positive sustaining pulse 32, the train is interrupted by a negative erase pulse 34. The amplitude and the duration of the erase pulse are emperically selected to relax the internal field across the thin-film EL layer before the sustaining pulse train is reapplied. To simplify implementation of the method, the amplitude Vr of the erase pulse may be the same as that of the sustaining pulses, but should not exceed Vs. Upon the conclusion of pulse 34, a train of sustaining pulses Ps is reapplied to the display panel. The train may begin with a pulse of either polarity without affecting erasure of the panel.
A plot of the internal electric field in the ZnS:Mn active layer during the FIG. 3 erase cycle is shown in FIG. 4. As will be observed, each sustaining pulse Ps steps the layer's internal field by an amount Es, which adds to the polarization field Ep during the next pulse to enhance luminance. Since the thin-film panel is a capacitive device, erase pulse 34 steps the internal field by an amount Er. This increases the field, causing the EL layer to emit light and discharge. The higher the field, the greater the emission and the faster the discharge, which reduces the EL layer's internal field. When the erase pulse terminates and the next sustain pulse Ps is applied, the total field is insufficient to sustain electroluminescence at the Lw level. Thus, the active layers free electrons are trapped out and the panel returns to the lower luminance level Ls. The FIG. 4 plot suggests, as one would expect, that there is a minimum value for Vr, below which erasure does not occur. This value will vary, depending on the construction of the EL panel, and is best determined by trial and error.
Visually, erasure of an EL panel by the method of the invention is seen as a rapid, complete disappearance of written images without any annoying flash. The described technique is applicable to any type of hysteretic thin-film EL device, including those incorporating a layer of ultraviolet-emitting phosphor overlying the second conductive layer for conversion of incident electrons to UV light. Such a device, used as a CRT storage target, is described in my above-mentioned application, Ser. No. 922,950. One feature of the invention applicable only to a UV-addressed hysteretic EL panel is that writing can take place during the erase pulse. Portions of the panel thus written will remain stored, while all previously written information will be erased.

Claims (8)

I claim as my invention:
1. A method of operating an electroluminescent device exhibiting voltage/luminance hysteresis, said device comprising an active layer of electroluminescent material, first and second electrodes of conductive material, each electrode being disposed opposite a different face of the active layer, and first and second dielectric layers separating and insulating said electrodes from the active layer, said method comprising the steps of:
(a) applying a sustaining voltage signal to the active layer through said electrodes, said signal including alternating polarity pulses having an amplitude sufficient to bias the device into its region of voltage/luminance hysteresis,
(b) discontinuing application of the sustaining signal,
(c) applying an erase pulse that reduces the active layer's internal electric field to a level such that reapplication of the sustaining voltage signal will cause luminescent regions of the device to be extinguished, said pulse having (i) an amplitude not exceeding that of the sustaining signal, (ii) a duration greater than that of the individual pulses in said sustaining signal, and (iii) a polarity opposite that of the last preceding pulse of said signal, and
(d) reapplying the sustaining signal.
2. The method of claim 1, wherein said active layer consists essentially of manganese-activated zinc sulfide.
3. The method of claim 1, wherein said sustaining voltage signal is in the form of a train composed of spaced, alternating polarity pulses.
4. The method of claim 3, wherein said pulses have a substantially rectangular waveform.
5. The method of claim 1, wherein said erase pulse has an amplitude substantially equal to that of said sustaining voltage signal.
6. A method of erasing an electroluminescent display device of the type exhibiting voltage/luminance hysteresis, said device comprising an active layer of electroluminescent material, first and second electrodes of conductive material, each one disposed opposite a different face of the active layer, and first and second dielectric layers separating and insulating said electrodes from the active layer, said device including at least one region of luminescence sustained by the application of alternating polarity voltage pulses to the active layer through said electrodes, said method comprising the steps of:
(a) interrupting the application of said alternating polarity sustaining voltage pulses to said active layer,
(b) applying an erase pulse that is (i) opposite in polarity to the last preceding sustaining pulse, (ii) longer in duration than individual sustaining pulses, and (iii) equal or lower in amplitude than the sustaining pulses, the amplitude and duration of the erase pulse being selected to provide a reduction in the active layer's internal electric field sufficient to produce extinction of luminescence in said region upon reapplication of said sustaining voltage pulses, and
(c) reapplying said sustaining voltage pulses.
7. The method of claim 6, wherein said erase pulse has an amplitude substantially equal to that of said sustaining pulses.
8. The method of claim 6, wherein said sustaining voltage pulses have a substantially rectangular waveform.
US06/100,170 1979-12-04 1979-12-04 Erasure method for memory-type EL display devices Expired - Lifetime US4301451A (en)

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Application Number Priority Date Filing Date Title
US06/100,170 US4301451A (en) 1979-12-04 1979-12-04 Erasure method for memory-type EL display devices
CA000363286A CA1144289A (en) 1979-12-04 1980-10-27 Erasure method for memory-type el display devices
GB8034932A GB2064861B (en) 1979-12-04 1980-10-30 Erasure method for electroluminescent display devices
DE19803042691 DE3042691A1 (en) 1979-12-04 1980-11-12 METHOD FOR CLEARING STORAGE ELECTROLUMINESCENT DISPLAY DEVICES
JP16651480A JPS5691293A (en) 1979-12-04 1980-11-26 Erasing method in el display unit
FR8025957A FR2471643A1 (en) 1979-12-04 1980-12-02 ERASING METHOD FOR MEMORY LIGHT EMITTING DISPLAY DEVICE
NL8006588A NL8006588A (en) 1979-12-04 1980-12-03 METHOD FOR ERASING ELECTROLUMINESCENT MEMORY DISPLAY UNITS.

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Cited By (6)

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Publication number Priority date Publication date Assignee Title
US4479120A (en) * 1980-10-15 1984-10-23 Sharp Kabushiki Kaisha Method and apparatus for driving a thin-film EL panel
US4485379A (en) * 1981-02-17 1984-11-27 Sharp Kabushiki Kaisha Circuit and method for driving a thin-film EL panel
US5004956A (en) * 1988-08-23 1991-04-02 Westinghouse Electric Corp. Thin film electroluminescent edge emitter structure on a silcon substrate
US5043631A (en) * 1988-08-23 1991-08-27 Westinghouse Electric Corp. Thin film electroluminescent edge emitter structure on a silicon substrate
US5671059A (en) * 1995-09-21 1997-09-23 Hewlett-Packard Company Electroluminescent color device
US20090046043A1 (en) * 2004-10-28 2009-02-19 Masayuki Ono Display and display driving method

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
US6271812B1 (en) * 1997-09-25 2001-08-07 Denso Corporation Electroluminescent display device

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US3975661A (en) * 1973-06-19 1976-08-17 Sharp Kabushiki Kaisha Driving method for a thin-film electroluminescent element of a three-layer construction
US4206460A (en) * 1977-03-10 1980-06-03 Sharp Kabushiki Kaisha EL Display drive controlled by an electron beam

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3975661A (en) * 1973-06-19 1976-08-17 Sharp Kabushiki Kaisha Driving method for a thin-film electroluminescent element of a three-layer construction
US4206460A (en) * 1977-03-10 1980-06-03 Sharp Kabushiki Kaisha EL Display drive controlled by an electron beam

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4479120A (en) * 1980-10-15 1984-10-23 Sharp Kabushiki Kaisha Method and apparatus for driving a thin-film EL panel
US4485379A (en) * 1981-02-17 1984-11-27 Sharp Kabushiki Kaisha Circuit and method for driving a thin-film EL panel
US5004956A (en) * 1988-08-23 1991-04-02 Westinghouse Electric Corp. Thin film electroluminescent edge emitter structure on a silcon substrate
US5043631A (en) * 1988-08-23 1991-08-27 Westinghouse Electric Corp. Thin film electroluminescent edge emitter structure on a silicon substrate
US5671059A (en) * 1995-09-21 1997-09-23 Hewlett-Packard Company Electroluminescent color device
US20090046043A1 (en) * 2004-10-28 2009-02-19 Masayuki Ono Display and display driving method
US7973747B2 (en) * 2004-10-28 2011-07-05 Panasonic Corporation Display and display driving method

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FR2471643A1 (en) 1981-06-19
GB2064861A (en) 1981-06-17
NL8006588A (en) 1981-07-01
GB2064861B (en) 1984-01-04
JPS5691293A (en) 1981-07-24
DE3042691A1 (en) 1981-06-11

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