US3886580A - Tantalum-gallium arsenide schottky barrier semiconductor device - Google Patents

Tantalum-gallium arsenide schottky barrier semiconductor device Download PDF

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US3886580A
US3886580A US404303A US40430373A US3886580A US 3886580 A US3886580 A US 3886580A US 404303 A US404303 A US 404303A US 40430373 A US40430373 A US 40430373A US 3886580 A US3886580 A US 3886580A
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tantalum
barrier
electrode
gallium arsenide
schottky barrier
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Joseph A Calviello
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Cutler Hammer Inc
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Priority to IT7451226A priority patent/IT1013254B/en
Priority to BR4510/74A priority patent/BR7404510A/en
Priority to DE2436449A priority patent/DE2436449C3/en
Priority to GB4378474A priority patent/GB1446406A/en
Priority to JP49115732A priority patent/JPS5116288B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28581—Deposition of Schottky electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H01L29/475—Schottky barrier electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/056—Gallium arsenide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/139—Schottky barrier

Definitions

  • Tantalum acts as a diffusion shield, enabling 3,244,555 4/1966 Adam et al. [17/212 use of gold as a direct contact on the electrode. 3,615,929 10/1971 Portnoy et al.. [48/175 3,663,279 5/1972 Lepselter 117/212 1 Clam, 4 Draw! Flgures TANTALUM GOLD TANTALUM 0111015 8 8 QXIDE 3 N EPITAXIAL LAYER 7 N7 GALLlUM ARSENIDE OHMlC coNT'A'ci [III TANTALUM-GALLIUM ARSENIDE SCHOTTKY BARRIER SEMICONDUCTOR DEVICE BAC KGROU ND This invention relates to improvements in Schottky barrier semiconductor devices.
  • Such devices are generally well known, for example in the form of asymmetrically conductive diodes'comprising a body of appropriately doped semiconductor such as gallium arsenide with a region of its surface in intimate contact with an electrode of metal having a suitable work function, such as nickel, molybdenum, tungsten, palladium, or gold.
  • the electrode is usually in the form of a thin film, deposited on the semiconductor by conventional tech niques.
  • All of the metals used heretofore as Schottky electrodes exhibit one or more undesirable characteristics that require special countermeasures, which are usually expensive and not always fully satisfactory, in fabrication of the devices.
  • nickel films are brittle and vulnerable to mechanical stress; tungsten tends to form conductive whiskers that short-circuit the edge of the barrier; gold, an otherwise nearly ideal material, diffuses into the semiconductor and destroys its characteristics, particularly at higher temperatures within the desired operating range of the device.
  • gold is also a nearly ideal material for making contact between the Schottky electrode and the external circuit.
  • it diffuses readily through some metals such as palladium that would otherwise be suitable as electrodes.
  • the prior art solution to this problem has been to provide a diffusion shield between the Schottky electrode and the gold terminal, comprising a film of some metal that resists gold diffusion.
  • the metals suitable as diffusion shields have such temperature coefficients of expansion that they must be sandwiched between additional metal layers of intermediate temperature coefficient to prevent destruction of the electrode-contact structure due to normal temperature variations.
  • the two or more additional metal layers required in prior art practice contribute substantially to the cost and difficulty of fabricating such devices.
  • Passivation of the semiconductor device in prior art practice usually involves a sequence of steps such as deposition of one or more layers of insulating film and selective etching to define the desired patterns.
  • the periphery of the barrier formed by the metalsemiconductor junction is particularly vulnerable to ambient reagents such as oxygen, water and sodium ions, and requires special precautions, as described in U.S. Pat. No. 3,635,417, for example.
  • the principal object of this invention is to provide gallium arsenide Schottky barrier devices that exhibit highly stable nearly ideal electrical characteristics undegraded by high temperature operation, and that are adapted to simple and economical fabrication.
  • improvements in such devices and in the method of making them are achieved by direct deposition of a tantalum electrode on a gallium arsenide substrate, direct deposition of a gold contact on the tantalum electrode, then formation of native oxide film on the exposed areas of the electrode and substrate for passivation.
  • Tantalum is effective as a gold diffusion shield, requiring no intermediate shield layers, and has a temperature coefficient of expansion nearly equal to that of gallium arsenide, enabling operation of the device at elevated temperatures without mechanical or electrical degradation.
  • the native oxides are stable and impervious. Improved yield in manufacturing is attained because the barrier can be made immediately after cleaning the substrate, minimizing the possibility of contamination or oxidation of the cleaned surface, and the back contact 6 n be made subsequently. The barrier and electrouc structure will resist, without damage, the high temperature needed in forming the back contact.
  • FIG. 1 is a sectional view of a Schottky diode illustrating a presently preferred embodiment of the invention.
  • FIG. 2 is a graph of the voltage-current characteristic of the diode of FIG. 1.
  • FIG. 3 is another graph, in semi-log form, of the initial forward-conducting portion of said characteristic.
  • FIG. 4 is a graph showing the relationship between bias and a function of barrier capacitance of said diode.
  • the diode to be described is particularly useful as a varactor in low noise high frequency parametric amplitiers. Modifications thereof, involving no difference in the application of the present invention, may be designed for other uses, as frequency multipliers, limiters and impatt oscillators, for example.
  • the Schottky barrier l is the interface or junction between a tantalum electrode 2 and the upper surface of an N-type epitaxial layer 3 of gallium arsenide, supported on an N+ gallium arsenide substrate 4 which is provided with an ohmic contact 5 on its lower surface.
  • a gold contact 6 on the upper surface of the tantalum electrode 2 provides for easy connection of the device to external circuit means, as by thermal compressive bonding thereto of a gold ribbon, not shown.
  • the epitaxial layer 3 and the substrate immediately adjacent to it are shaped as a short mesa, whereby the plane of the barrier 1 is slightly higher than the general level of the surrounding upper surface of the N+ substrate 4.
  • the tantalum electrode 2 overhangs the top of the epitaxial region 3, extending outwardly beyond the periphery of the barrier l as shown.
  • the lower surface of the overhanging part of the tantalum electrode forms an angle of about 90 with the nearby side surface of the epitaxial material.
  • the epitaxial layer 3 is about 12 microns in diameter and 0.4 microns thick, with a donor concentration of about 8 l0' atoms per cm".
  • the donor may be sulphur or tellurium.
  • the substrate 4 is preferably about microns thick.
  • the tan- 3 talum electrode 2 is about 2000A thick.
  • the gold contact member 6 should be about I micron or more in thickness, for reliable bonding to an external conductor.
  • the voltage-current characteristic curve of FIG. 2 is a copy, approximately full scale, of an oscilloscope display of said characteristic. On this scale, the reverse leakage current is imperceptible, and the curve coin cides with the abscissa between zero and the avalanche breakdown at about 20 volts. The knee of the curve at that point is very abrupt, visually indistinguishable in the display from a right angle, indicating uniformity of the field throughout junction area and the absence of defects at the edge of the junction.
  • FIG. 3 shows, on a different scale, the characteristic represented by the curve of FIG. 2 between zero and about +0.6 volt.
  • the solid portion 31 of the curve of FIG. 3 was plotted point by point, using an electrometer device capable of measuring currents as low as l ampere with useful accuracy.
  • the ordinate, in amperes, is logarithmic, causing the exponential relationship between voltage and current in this region to appear as a straight line in the graph.
  • Downward extrapolation of the curve 31, indicated by the dash line 32 intercepts the ordinate at about liXlO ampere, implying that the reverse saturation current I is of that value.
  • the data illustrated by FIG. 3 enables calculation of the diode parameter n, which is about L06 in the case of the described device. This value indicates a Schottky barrier of good quality, by usual standards.
  • FIG. 4 shows l/C as a function of voltage for the device of FIG. I, where C is the barrier capacitance in picofarads.
  • C is the barrier capacitance in picofarads.
  • the straight-line appearance of the graph 41 in the reverse bias region indicates a normal varactor characteristic.
  • the extrapolation into the forward bias region represented by the dash line 43 intercepts the abscissa at 0.8 volt, implying that the built-in voltage or contact potential d), is of that value, which is close to that theoretically expected in this case.
  • Schottky diodes of the above described construction have been maintained at 250C in ambient for 120 hours without detectable change in the characteristics shown in FIGS. 2, 3 and 4.
  • Present evidence supports the belief that such diodes will withstand and can be operated at considerably higher temperatures, say about 300C.
  • the method of making devices like that of FIG. 1 includes the usual preliminary steps of lapping the starting wafer of gallium arsenide to provide the desired thicknesses of the N epitaxial layer and N+ substrate, then cleaning, rinsing and drying, using conventional reagents.
  • the wafer is placed in a vacuum system of the type used for deposition of metal films by evaporation, with a mask perforated to expose the areas where Schottky electrodes are to be formed, and suitable provisions for evaporating first tantalum, then gold.
  • the system is then evacuated to a pressure of about 10'' mm Hg, and an ion pump maintained in operation to minimize active residual gases in the chamber, thereby preventing oxidation of the tantalum and deposition of tantalum oxide instead of tantalum.
  • the tantalum is evaporated, interrupting the process if necessary to avoid overheating and to maintain the 6 system pressure below about 10' mm Hg, until a film of about 2000A thick has been deposited. Then a layer of gold about I micron thick is deposited. The gold tends to spread slightly beyond the edge of the tantalum during deposition, forming a thin halo surrounding each deposit.
  • the halos are removed by sputter etching, followed by acid etching, or other usual procedure.
  • the wafer carries an array of perhaps I000 or more gold-covered tantalum deposits, and is ready for further processing to eventually produce a batch of diodes.
  • the array could be produced by using known photomasking and etching techniques instead of the perforated mask.
  • the next step is the formation of an ohmic contact layer on the back side of the wafer, i.e. on the surface opposite the tantalum spots.
  • This may be accomplished by a conventional technique, such as evaporation and sinter alloying of silver, tin and palladium.
  • the usual prior practice has been to form the back contact before forming the Schottky electrodes, because the high temperature required for sintering, about 420C, would degrade or destroy a previously formed barrier.
  • the Schottky barrier of the electrode structure of the present invention is not damaged by such temperature, and so may be formed before the back contact.
  • the wafer is then etched in known manner to remove the exposed epitaxial layer and some of the N+ substrate, forming a shallow mesa like that shown in FIG. 1 under each tantalum deposit.
  • the etching may be effected by immersion of the wafer in a solution of 3 parts sulphuric acid, 1 part hydrogen peroxide and 1 part water with mild agitation for 2 minutes, followed by immersion in a solution of 8 parts sulphuric acid, 1 part hydrogen peroxide and 1 part water for one minute.
  • This degree of etching, or its equivalent results in a slight undercut of the gallium arsenide beiow the tantalum, exposing the lower surface of the electrode in an overhanging annular region around the barrier, as described above and shown in FIG. 1.
  • the wafer After rinsing and partial drying, the wafer is baked or cured in air or oxidant gas for 1.5 hour at 350C to complete the drying and initiate formation of the tantalum oxide passivation film 8 (FIG. 1) around the edge of the barrier.
  • Completion of this film, and of the native oxide film 7 on the exposed upper surface of the Nisubstrate, can be effected by immersion of the wafer in a 30 percent solution of hydrogen peroxide for a period of 60 to hours, preferably under strong illumination.
  • native oxide is used herein to denote the oxide that forms under the described conditions. The composition of said oxide is not known with certainty at present, but is believed to be gallium oxide in amorphous form.
  • the wafer After passivation, the wafer is baked at 225C in air for about 4 to 6 hours, then scribed or diced in usual manner to separate the individual diode chips like that of FIG. 1 for mounting in appropriate supporting and connection structures.
  • a Schottky barrier semiconductor device comprising a body of gallium arsenide, a metal electrode in contact with said body to form therewith a Schottky barrier, and a passivation film covering at least the parts of said body and said electrode in the region of the periphery of said barrier, characterized in that a. said electrode is of tantalum,
  • said passivation film that covers said body is native oxide of gallium arsenide
  • said passivation film that covers said electrode is dicular to the plane of said barrier
  • tantalum oxide m Contact sald nat've ox'de e. said tantalum electrode extends along said plane film in close proximity to the edge of said barrier, d. the surface region of gallium arsenide adjacent the periphery of said barrier is approximately perpen- 5 outwardly beyond said barrier periphery.

Abstract

A schottky barrier semiconductor device wherein the semiconductor is gallium arsenide and the metal electrode is tantalum, passivated by formation of native oxides after the metal-semiconductor junction is made. Tantalum acts as a diffusion shield, enabling use of gold as a direct contact on the electrode.

Description

0 United States Patent 1 1 1 3,886,580 Calviello May 27, 197 5 [54] TANTALUM-GALLIUM ARSENIDE 3,672,984 6/1972 Sato et al ll7/2l2 SCHOTTKY BARRIER SEMICONDUCTOR 3,70l,93l lU/l972 Rev tz et al........ DEVICE 3,7l7,563 2/1973 Revitz et al 1. 204/192 3,756,924 9/l973 Collins et al 204/15 [75] Inventor: .flqoieph A. CaIvIeIIo, Kmgs Park, OTHER PUBLICATIONS l N. Anantha et al., Planar Mesa Schottky Barrier Di [73] Ass1gnee: Cutler-Hammer, Inc., Milwaukee, ode." IBM J. Res Dew-310py NOV. :97 pp 442 445 S. Sze, Physics of Semiconductor Devices, Wi- [22] Filed: Oct. 9, 1973 ley-Interscience, 1969, pp. 364367.
[21] Appl' 404303 Primary Examiner-Michael J. Lynch Assistant Examiner-Joseph E. Clawson, Jr. [52] U.S. C]. 357/15; 357/52; 357/54; Attorney, Agent, or Firm-Henry Huff 357/56 [5|] Int. Cl Holl 3/20 57 ABSTRACT [58] Field of Search" 317/235 g f ggj A schottky barrier semiconductor device wherein the l semiconductor is gallium arsenide and the metal electrode is tantalum, passivated by formation of native [56] References cued oxides after the metal-semiconductor junction is UNITED STATES PATENTS made. Tantalum acts as a diffusion shield, enabling 3,244,555 4/1966 Adam et al. [17/212 use of gold as a direct contact on the electrode. 3,615,929 10/1971 Portnoy et al.. [48/175 3,663,279 5/1972 Lepselter 117/212 1 Clam, 4 Draw! Flgures TANTALUM GOLD TANTALUM 0111015 8 8 QXIDE 3 N EPITAXIAL LAYER 7 N7 GALLlUM ARSENIDE OHMlC coNT'A'ci [III TANTALUM-GALLIUM ARSENIDE SCHOTTKY BARRIER SEMICONDUCTOR DEVICE BAC KGROU ND This invention relates to improvements in Schottky barrier semiconductor devices. Such devices are generally well known, for example in the form of asymmetrically conductive diodes'comprising a body of appropriately doped semiconductor such as gallium arsenide with a region of its surface in intimate contact with an electrode of metal having a suitable work function, such as nickel, molybdenum, tungsten, palladium, or gold. The electrode is usually in the form of a thin film, deposited on the semiconductor by conventional tech niques.
All of the metals used heretofore as Schottky electrodes exhibit one or more undesirable characteristics that require special countermeasures, which are usually expensive and not always fully satisfactory, in fabrication of the devices. For example, nickel films are brittle and vulnerable to mechanical stress; tungsten tends to form conductive whiskers that short-circuit the edge of the barrier; gold, an otherwise nearly ideal material, diffuses into the semiconductor and destroys its characteristics, particularly at higher temperatures within the desired operating range of the device.
For several reasons, for example its good thermal and electrical conductivity, its adaptability to thermal compression bonding, and resistance to corrosion, gold is also a nearly ideal material for making contact between the Schottky electrode and the external circuit. However, it diffuses readily through some metals such as palladium that would otherwise be suitable as electrodes. The prior art solution to this problem has been to provide a diffusion shield between the Schottky electrode and the gold terminal, comprising a film of some metal that resists gold diffusion.
The metals suitable as diffusion shields have such temperature coefficients of expansion that they must be sandwiched between additional metal layers of intermediate temperature coefficient to prevent destruction of the electrode-contact structure due to normal temperature variations. The two or more additional metal layers required in prior art practice contribute substantially to the cost and difficulty of fabricating such devices.
Passivation of the semiconductor device in prior art practice usually involves a sequence of steps such as deposition of one or more layers of insulating film and selective etching to define the desired patterns. The periphery of the barrier formed by the metalsemiconductor junction is particularly vulnerable to ambient reagents such as oxygen, water and sodium ions, and requires special precautions, as described in U.S. Pat. No. 3,635,417, for example.
SUMMARY The principal object of this invention is to provide gallium arsenide Schottky barrier devices that exhibit highly stable nearly ideal electrical characteristics undegraded by high temperature operation, and that are adapted to simple and economical fabrication.
According to this invention, improvements in such devices and in the method of making them are achieved by direct deposition of a tantalum electrode on a gallium arsenide substrate, direct deposition of a gold contact on the tantalum electrode, then formation of native oxide film on the exposed areas of the electrode and substrate for passivation. Tantalum is effective as a gold diffusion shield, requiring no intermediate shield layers, and has a temperature coefficient of expansion nearly equal to that of gallium arsenide, enabling operation of the device at elevated temperatures without mechanical or electrical degradation. The native oxides are stable and impervious. Improved yield in manufacturing is attained because the barrier can be made immediately after cleaning the substrate, minimizing the possibility of contamination or oxidation of the cleaned surface, and the back contact 6 n be made subsequently. The barrier and electrouc structure will resist, without damage, the high temperature needed in forming the back contact.
DRAWING FIG. 1 is a sectional view of a Schottky diode illustrating a presently preferred embodiment of the invention.
FIG. 2 is a graph of the voltage-current characteristic of the diode of FIG. 1.
FIG. 3 is another graph, in semi-log form, of the initial forward-conducting portion of said characteristic.
FIG. 4 is a graph showing the relationship between bias and a function of barrier capacitance of said diode.
DESCRIPTION The diode to be described is particularly useful as a varactor in low noise high frequency parametric amplitiers. Modifications thereof, involving no difference in the application of the present invention, may be designed for other uses, as frequency multipliers, limiters and impatt oscillators, for example.
Referring to FIG. 1, the Schottky barrier l is the interface or junction between a tantalum electrode 2 and the upper surface of an N-type epitaxial layer 3 of gallium arsenide, supported on an N+ gallium arsenide substrate 4 which is provided with an ohmic contact 5 on its lower surface. A gold contact 6 on the upper surface of the tantalum electrode 2 provides for easy connection of the device to external circuit means, as by thermal compressive bonding thereto of a gold ribbon, not shown.
The epitaxial layer 3 and the substrate immediately adjacent to it are shaped as a short mesa, whereby the plane of the barrier 1 is slightly higher than the general level of the surrounding upper surface of the N+ substrate 4. The tantalum electrode 2 overhangs the top of the epitaxial region 3, extending outwardly beyond the periphery of the barrier l as shown. The lower surface of the overhanging part of the tantalum electrode forms an angle of about 90 with the nearby side surface of the epitaxial material.
The entire upper surface of the gallium oxide member, except for that portion in contact with the tantalum electrode, is covered with a film of native oxide, formed in place as will be described. The edge of the tantalum electrode, and that part of the lower surface of the overhanging area not covered with the oxide film 7, is covered with a film 8 of tantalum oxide, also formed in place.
In a typical varactor diode, the epitaxial layer 3 is about 12 microns in diameter and 0.4 microns thick, with a donor concentration of about 8 l0' atoms per cm". The donor may be sulphur or tellurium. The substrate 4 is preferably about microns thick. The tan- 3 talum electrode 2 is about 2000A thick. The gold contact member 6 should be about I micron or more in thickness, for reliable bonding to an external conductor.
The voltage-current characteristic curve of FIG. 2 is a copy, approximately full scale, of an oscilloscope display of said characteristic. On this scale, the reverse leakage current is imperceptible, and the curve coin cides with the abscissa between zero and the avalanche breakdown at about 20 volts. The knee of the curve at that point is very abrupt, visually indistinguishable in the display from a right angle, indicating uniformity of the field throughout junction area and the absence of defects at the edge of the junction.
FIG. 3 shows, on a different scale, the characteristic represented by the curve of FIG. 2 between zero and about +0.6 volt. The solid portion 31 of the curve of FIG. 3 was plotted point by point, using an electrometer device capable of measuring currents as low as l ampere with useful accuracy. The ordinate, in amperes, is logarithmic, causing the exponential relationship between voltage and current in this region to appear as a straight line in the graph. Downward extrapolation of the curve 31, indicated by the dash line 32, intercepts the ordinate at about liXlO ampere, implying that the reverse saturation current I is of that value. The data illustrated by FIG. 3 enables calculation of the diode parameter n, which is about L06 in the case of the described device. This value indicates a Schottky barrier of good quality, by usual standards.
FIG. 4 shows l/C as a function of voltage for the device of FIG. I, where C is the barrier capacitance in picofarads. The straight-line appearance of the graph 41 in the reverse bias region indicates a normal varactor characteristic. The extrapolation into the forward bias region represented by the dash line 43 intercepts the abscissa at 0.8 volt, implying that the built-in voltage or contact potential d), is of that value, which is close to that theoretically expected in this case.
Schottky diodes of the above described construction have been maintained at 250C in ambient for 120 hours without detectable change in the characteristics shown in FIGS. 2, 3 and 4. Present evidence supports the belief that such diodes will withstand and can be operated at considerably higher temperatures, say about 300C.
The method of making devices like that of FIG. 1 includes the usual preliminary steps of lapping the starting wafer of gallium arsenide to provide the desired thicknesses of the N epitaxial layer and N+ substrate, then cleaning, rinsing and drying, using conventional reagents.
Immediately after cleaning, the wafer is placed in a vacuum system of the type used for deposition of metal films by evaporation, with a mask perforated to expose the areas where Schottky electrodes are to be formed, and suitable provisions for evaporating first tantalum, then gold. The system is then evacuated to a pressure of about 10'' mm Hg, and an ion pump maintained in operation to minimize active residual gases in the chamber, thereby preventing oxidation of the tantalum and deposition of tantalum oxide instead of tantalum.
The tantalum is evaporated, interrupting the process if necessary to avoid overheating and to maintain the 6 system pressure below about 10' mm Hg, until a film of about 2000A thick has been deposited. Then a layer of gold about I micron thick is deposited. The gold tends to spread slightly beyond the edge of the tantalum during deposition, forming a thin halo surrounding each deposit. The halos are removed by sputter etching, followed by acid etching, or other usual procedure.
At this stage, the wafer carries an array of perhaps I000 or more gold-covered tantalum deposits, and is ready for further processing to eventually produce a batch of diodes. Although the above procedure is preferred at present, it will be understood that the array could be produced by using known photomasking and etching techniques instead of the perforated mask.
Preferably, the next step is the formation of an ohmic contact layer on the back side of the wafer, i.e. on the surface opposite the tantalum spots. This may be accomplished by a conventional technique, such as evaporation and sinter alloying of silver, tin and palladium. The usual prior practice has been to form the back contact before forming the Schottky electrodes, because the high temperature required for sintering, about 420C, would degrade or destroy a previously formed barrier. The Schottky barrier of the electrode structure of the present invention is not damaged by such temperature, and so may be formed before the back contact.
The wafer is then etched in known manner to remove the exposed epitaxial layer and some of the N+ substrate, forming a shallow mesa like that shown in FIG. 1 under each tantalum deposit. As a specific example, the etching may be effected by immersion of the wafer in a solution of 3 parts sulphuric acid, 1 part hydrogen peroxide and 1 part water with mild agitation for 2 minutes, followed by immersion in a solution of 8 parts sulphuric acid, 1 part hydrogen peroxide and 1 part water for one minute. This degree of etching, or its equivalent, results in a slight undercut of the gallium arsenide beiow the tantalum, exposing the lower surface of the electrode in an overhanging annular region around the barrier, as described above and shown in FIG. 1.
After rinsing and partial drying, the wafer is baked or cured in air or oxidant gas for 1.5 hour at 350C to complete the drying and initiate formation of the tantalum oxide passivation film 8 (FIG. 1) around the edge of the barrier. Completion of this film, and of the native oxide film 7 on the exposed upper surface of the Nisubstrate, can be effected by immersion of the wafer in a 30 percent solution of hydrogen peroxide for a period of 60 to hours, preferably under strong illumination. The term native oxide" is used herein to denote the oxide that forms under the described conditions. The composition of said oxide is not known with certainty at present, but is believed to be gallium oxide in amorphous form.
After passivation, the wafer is baked at 225C in air for about 4 to 6 hours, then scribed or diced in usual manner to separate the individual diode chips like that of FIG. 1 for mounting in appropriate supporting and connection structures.
I claim:
1. A Schottky barrier semiconductor device comprising a body of gallium arsenide, a metal electrode in contact with said body to form therewith a Schottky barrier, and a passivation film covering at least the parts of said body and said electrode in the region of the periphery of said barrier, characterized in that a. said electrode is of tantalum,
b. said passivation film that covers said body is native oxide of gallium arsenide,
6 c. said passivation film that covers said electrode is dicular to the plane of said barrier, and
tantalum oxide m Contact sald nat've ox'de e. said tantalum electrode extends along said plane film in close proximity to the edge of said barrier, d. the surface region of gallium arsenide adjacent the periphery of said barrier is approximately perpen- 5 outwardly beyond said barrier periphery.

Claims (1)

1. A SCHOTTKY BARRIER SEMICONDUCTOR DEVICE COMPRISING A BODY OF GALLIUM ARSENIDE, A METAL ELECTRODE IN CONTACT WITH SAID BODY TO FORM THEREWITH A SCHOTTKY BARRIER, AND A PASSIVATION FILM COVERING AT LEAST THE PARTS OF SAID BODY AND SAID ELECTRODE IN THE REGION OF THE PERIPHERY OF SAID BARRIER, CHARACTERIZED IN THAT A. SAID ELECTRODE IS OF TANTALUM, B. SAID PASSIVATION FILM THAT COVERS SAID BODY IS NATIVE OXIDE OF GALLIUM ARSENIDE, C. SAID PASSIVATION FILM THAT COVERS SAID ELECTRODE IS TANTALUM OXIDE IN CONTACT WITH SAID NATIVE OXIDE FILM IN CLOSE PROXIMITY TO THE EDGE OF SAID BARRIER, D. THE SURFACE REGION OF GALLIUM ARSENIDE ADJACENT THE PERIPHERY OF SAID BARRIER IS APPROXIMATELY PERPENDICULAR TO THE PLANE OF SAID BARRIER, AND E. SAID TANTALUM ELECTRODE EXTENDS ALONG SAID PLANE OUTWARDLY BEYOND SAID BARRIER PERIPHERY.
US404303A 1973-10-09 1973-10-09 Tantalum-gallium arsenide schottky barrier semiconductor device Expired - Lifetime US3886580A (en)

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US404303A US3886580A (en) 1973-10-09 1973-10-09 Tantalum-gallium arsenide schottky barrier semiconductor device
CA199,683A CA992221A (en) 1973-10-09 1974-05-13 Tantalum-gallium arsenide schottky barrier semiconductor device
FR7417434A FR2246980B1 (en) 1973-10-09 1974-05-20
IT7451226A IT1013254B (en) 1973-10-09 1974-05-27 IMPROVEMENT IN SEMI-CONDUCTIVE DEVICES WITH SCHOTTKY BARRIER LAYER
BR4510/74A BR7404510A (en) 1973-10-09 1974-05-31 IMPROVEMENT IN SCHOTTKY SEMICONDUCTOR OBSTRUCTOR DEVICE AND SCHOTTKY OBSTRUCTOR ELECTRODE STRUCTURE PROCESS
DE2436449A DE2436449C3 (en) 1973-10-09 1974-07-29 Schottky diode and process for its manufacture
GB4378474A GB1446406A (en) 1973-10-09 1974-10-09 Semiconductor devices
JP49115732A JPS5116288B2 (en) 1973-10-09 1974-10-09
US543633*A US3923975A (en) 1973-10-09 1975-01-23 Tantalum-gallium arsenide schottky barrier semiconductor device

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JPS51141584A (en) * 1975-06-02 1976-12-06 Toshiba Corp A semiconductor unit
US4028140A (en) * 1974-10-29 1977-06-07 U.S. Philips Corporation Semiconductor device manufacture
US4034394A (en) * 1975-04-16 1977-07-05 Tokyo Shibaura Electric Co., Ltd. Schottky semiconductor device
US4062103A (en) * 1974-09-14 1977-12-13 Tokyo Shibaura Electric Co., Ltd. Method for manufacturing a semiconductor device
US4075650A (en) * 1976-04-09 1978-02-21 Cutler-Hammer, Inc. Millimeter wave semiconductor device
US4179533A (en) * 1978-04-25 1979-12-18 The United States Of America As Represented By The Secretary Of The Navy Multi-refractory films for gallium arsenide devices
US4201604A (en) * 1975-08-13 1980-05-06 Raytheon Company Process for making a negative resistance diode utilizing spike doping
US4307132A (en) * 1977-12-27 1981-12-22 International Business Machines Corp. Method for fabricating a contact on a semiconductor substrate by depositing an aluminum oxide diffusion barrier layer
US4312113A (en) * 1978-10-23 1982-01-26 Eaton Corporation Method of making field-effect transistors with micron and submicron gate lengths
US4379005A (en) * 1979-10-26 1983-04-05 International Business Machines Corporation Semiconductor device fabrication
US4468682A (en) * 1981-11-12 1984-08-28 Gte Laboratories Incorporated Self-aligned high-frequency static induction transistor
US4474623A (en) * 1982-04-26 1984-10-02 Raytheon Company Method of passivating a semiconductor body
US4541000A (en) * 1980-02-13 1985-09-10 Telefunken Electronic Gmbh Varactor or mixer diode with surrounding substrate metal contact and top surface isolation
US4923827A (en) * 1988-05-16 1990-05-08 Eaton Corporation T-type undercut electrical contact process on a semiconductor substrate
US4935805A (en) * 1988-05-16 1990-06-19 Eaton Corporation T-type undercut electrical contact on a semiconductor substrate
US5622877A (en) * 1993-03-02 1997-04-22 Ramot University Authority For Applied Research & Industrial Development Ltd. Method for making high-voltage high-speed gallium arsenide power Schottky diode
WO1998056039A1 (en) * 1997-06-03 1998-12-10 University Of Utah Research Foundation Utilizing inherent rectifying characteristics of a substrate in semiconductor devices
US20050156188A1 (en) * 2004-01-19 2005-07-21 Ro Jae C. Nitride semiconductor light emitting device and method of manufacturing the same
US20130126894A1 (en) * 2007-01-19 2013-05-23 Cree, Inc. Low voltage diode with reduced parasitic resistance and method for fabricating

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DE3005301C2 (en) * 1980-02-13 1985-11-21 Telefunken electronic GmbH, 7100 Heilbronn Varactor or mixer diode
JPS6081859A (en) * 1983-10-11 1985-05-09 Matsushita Electric Ind Co Ltd Schottky barrier semiconductor device

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US3663279A (en) * 1969-11-19 1972-05-16 Bell Telephone Labor Inc Passivated semiconductor devices
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Cited By (22)

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Publication number Priority date Publication date Assignee Title
US4062103A (en) * 1974-09-14 1977-12-13 Tokyo Shibaura Electric Co., Ltd. Method for manufacturing a semiconductor device
US4028140A (en) * 1974-10-29 1977-06-07 U.S. Philips Corporation Semiconductor device manufacture
US4034394A (en) * 1975-04-16 1977-07-05 Tokyo Shibaura Electric Co., Ltd. Schottky semiconductor device
JPS51141584A (en) * 1975-06-02 1976-12-06 Toshiba Corp A semiconductor unit
JPS5744020B2 (en) * 1975-06-02 1982-09-18
US4201604A (en) * 1975-08-13 1980-05-06 Raytheon Company Process for making a negative resistance diode utilizing spike doping
US4075650A (en) * 1976-04-09 1978-02-21 Cutler-Hammer, Inc. Millimeter wave semiconductor device
US4307132A (en) * 1977-12-27 1981-12-22 International Business Machines Corp. Method for fabricating a contact on a semiconductor substrate by depositing an aluminum oxide diffusion barrier layer
US4179533A (en) * 1978-04-25 1979-12-18 The United States Of America As Represented By The Secretary Of The Navy Multi-refractory films for gallium arsenide devices
US4312113A (en) * 1978-10-23 1982-01-26 Eaton Corporation Method of making field-effect transistors with micron and submicron gate lengths
US4379005A (en) * 1979-10-26 1983-04-05 International Business Machines Corporation Semiconductor device fabrication
US4541000A (en) * 1980-02-13 1985-09-10 Telefunken Electronic Gmbh Varactor or mixer diode with surrounding substrate metal contact and top surface isolation
US4468682A (en) * 1981-11-12 1984-08-28 Gte Laboratories Incorporated Self-aligned high-frequency static induction transistor
US4474623A (en) * 1982-04-26 1984-10-02 Raytheon Company Method of passivating a semiconductor body
US4923827A (en) * 1988-05-16 1990-05-08 Eaton Corporation T-type undercut electrical contact process on a semiconductor substrate
US4935805A (en) * 1988-05-16 1990-06-19 Eaton Corporation T-type undercut electrical contact on a semiconductor substrate
US5622877A (en) * 1993-03-02 1997-04-22 Ramot University Authority For Applied Research & Industrial Development Ltd. Method for making high-voltage high-speed gallium arsenide power Schottky diode
WO1998056039A1 (en) * 1997-06-03 1998-12-10 University Of Utah Research Foundation Utilizing inherent rectifying characteristics of a substrate in semiconductor devices
US20050156188A1 (en) * 2004-01-19 2005-07-21 Ro Jae C. Nitride semiconductor light emitting device and method of manufacturing the same
US20060202217A1 (en) * 2004-01-19 2006-09-14 Ro Jae C Nitride semiconductor light emitting device and method of manufacturing the same
US20130126894A1 (en) * 2007-01-19 2013-05-23 Cree, Inc. Low voltage diode with reduced parasitic resistance and method for fabricating
US9041139B2 (en) * 2007-01-19 2015-05-26 Cree, Inc. Low voltage diode with reduced parasitic resistance and method for fabricating

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JPS5067560A (en) 1975-06-06
FR2246980A1 (en) 1975-05-02
DE2436449A1 (en) 1975-04-24
CA992221A (en) 1976-06-29
JPS5116288B2 (en) 1976-05-22
IT1013254B (en) 1977-03-30
BR7404510A (en) 1976-02-10
DE2436449B2 (en) 1977-04-21
DE2436449C3 (en) 1980-06-19
FR2246980B1 (en) 1978-01-13
GB1446406A (en) 1976-08-18

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