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Publication numberUS3821731 A
Publication typeGrant
Publication date28 Jun 1974
Filing date23 Jul 1973
Priority date7 Jun 1971
Publication numberUS 3821731 A, US 3821731A, US-A-3821731, US3821731 A, US3821731A
InventorsLevine M
Original AssigneeAnn Arbor Terminals Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Graphics display system and method
US 3821731 A
Abstract  available in
Images(2)
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Claims  available in
Description  (OCR text may contain errors)

United States Patent [191 Levine June 28, 1974 GRAPHICS DISPLAY SYSTEM AND METHOD Inventor: Michael Robert Levine, Ann Arbor,

Mich.

Assignee: Ann Arbor Terminals, lnc., Ann

Arbor, Mich.

Filed: July 23, 1973 Appl. No.: 381,577

Related US. Application Data Continuation of Ser. No. 150,288, June 7, abandoned.

US. Cl.... 340/324 AD, l78/DlG. 3, 340/1725 Int. Cl. G06f 3/14 Field of Search 340/324 A, 324 AD;

l78/DIG. 3, 6.8, 7.5 D

[5 6] References Cited UNITED STATES PATENTS 10/1963 Kronenberg et a1. 340/324 AD 9/1968 Lee 340/324 AD 10/1969 Manber 340/324 AD 6/1971 Kraatz .[340/324 AD 3,646,257 2/1972 Epstein et a1. l78/DlG. 3 3,668,687 6/1972 Hale 340/324 AD 3,713,135 1/1973 Lazecki 340/324 AD Primary ExaminerDavid L. Trafton Attorney, Agent, or FirmBarnes, Kisselle, Raisch & Choate [5 7] ABSTRACT ing, circuit means are provided to respond to the starting point identification to gate the beam on and to the horizontal line identification to maintain the beamgated on along a scan line until the end of the line. For vertical line drawing, the beam is gated on at the starting point and a recirculating shift register stores the starting point identification to gate the beam on at the corresponding positions in successive scan lines.

19 Claims, 5 Drawing Figures ,2 Y 52 raster vert sync.

oriz. stable sync. L MV 4 L 12 so mam memory 3; standard dotoddress television monitor 66 address or can 69 0 cntr 2 J6 inputl load j reg. control and bt- 19 T /l 49 MV computer Pland and recirculating shift register f and memory I i ,L l

1 GRAPHICS DISPLAY SYSTEM AND METHOD This is a continuation of application Ser. No. 150,288, filed June 7, 1971 now abandoned.

This invention relates to digital data processing systems and more particularly to a graphics display system utilizing a television raster scan wherein digital data is used to generate a graphics display including dots and horizontal and vertical lines.

Graphics display systems presently commercially available fall generally into three categories. The first type is a so-called limited graphics display wherein one point is displayed during each scan line in response to an instruction from memory. So long as the change in the function being displayed is small from scan line to scan line, the technique is effective because the eye will integrate the dots as a continuous line function. However, as the change in the function increases from scan line to scan line, the eye does not effectively integrate the function. This causes the function to lose continuity to the viewer and, in an extreme case of large differences, the display becomes meaningless. Hence although a limited graphics system can display a slowly varying function, it cannot effectively display rapidly varying functions. The second type, commonly known as a full graphics display, is implemented by providing one memory location for every possible dot position on the display. Lines are drawn by displaying each dot in response to a separate digital instruction. Hence a line consisting of three dots requires three separate instructions from memory. Although the full graphicssystem can effectively display rapidly varying functions, it requires a large memory that is too expensive for many applications. The third type which may be termed character graphics has a limited character set, typically 64 characters; and the display field is divided into contiguous character cells, as contrasted to the dot matrix of a full graphics system. A designated character may be displayed at a designated cell. A graphic display is gen erated by selecting appropriate characters for contiguous cells. However, resolution with a character graphics display can be no greater than the cell size, typically one percent of the full graphics resolution capability. Character graphics, like limited graphics, cannot effectively display a rapidly varying function.

An object of the present invention is to provide a graphics display system and method that overcome the aforementioned disadvantages of the aforementioned displays.

Further objects of the present invention are to provide a graphics display system and method that provide effective display of rapidly varying functions and that reduce the number of memory locations required, and hence are low in cost, by comparison to prior art capable of displaying rapidly varying functions.

Other objects, features and advantages of the present invention will become more apparent in connection with the following description, the appended claims and the accompanying drawings in which:

FIG. 1 is a block diagram illustrating a first embodiment of the graphics display system of the present invention;

FIG. 2 is a coding format of the digital code data for the embodiment of FIG. 1;

FIG. 3a is a simplified display illustrating the generation of horizontal andvertical lines by means of the circuit of FIG. l;

FIG. 3b is a table of coding for generating the display of FIG. 3a with the circuit of FIG. 1;

FIG. 4 is a block diagram illustrating a second embodiment of a display system of the present invention; and

FIG. 5 is a coding format for the system of FIG. 4.

Referring in greater detail to the drawings, digitally coded data from a computer 10 is loaded into a main memory 12 via an input register 14 under control of a load control circuit 18 which also controls an address counter 16. In response to a strobe command at line 19 from the computer 10, the data necessary to generate a complete display frame on a standard television monitor 20 is entered into memory 12. It will be understood that the particular manner in which data is loaded into memory 12 is not an essential feature of the present invention. Various different techniques can be used. For

purposes of illustration, memory 12 is a random access memory, for example, the memory known commercially as MOS RAM, that is loaded sequentially and then read sequentially under the control of the address counter 16 to generate a display on monitor 20.

By way of further illustration, one typical display contains, for example, 256 scan lines each of which has 512 dot positions at which a dot could be displayed. For reasons that will later be apparent, each byte or digital word from computer 10 has the format shown in FIG. 2 wherein nine of the bits 22 (FIG. 2) is a number specifying one of the 512 dot positions on a scan line. For reasons as will later be described in greater detail, the nine-bit dot position specified by the data in memory 12 identifies the number of dot positions to the next dot to be displayed. The remaining three bits are a line feed bit 24, a horizontal line drawing bit 26 and a vertical line drawing bit 28.

The nine bits 22 in each byte are transferred sequentially from memory 12 under the control of the address counter 16 to a countdown counter 30. For the above example, counter 30 has nine stages so that it can count up to 512. Simultaneously the line feed bit 24 is fed through a bistable multivibrator 32 to an AND gate 34. The horizontal line drawing bit 26 is steered into a pair of AND gates 36, 38 in a horizontal line generator 40 designated by broken lines; and the vertical line drawing bit 28 is steered to a pair of AND gates 42, 44 in a vertical line generator 46 designated by broken lines.

A raster scan timing cicuit 50 generates timing signals applied, respectively, via line 52 to counter 16, via line 54 to gate 34, and via line 56 to multivibrator 32. The timing signal applied to gate 34 via line 54 is a dot clock pulse train containing the desired number of pulses, 512 pulses for the above example, to determine the number of dot positions which can be illuminated along each horizontal scan line at monitor 20. Hence timing circuit 50 provides a burst of 512 pulses in synchronism'with the beam as it traces each horizontal scan line. The dot clock pulse train is applied to gate 34 only during the useful portion of a horizontal scan on the display; that is, the clock is not applied at gate 34 during horizontal and vertical retrace of the beam. The timing signal applied to counter 16 via line 52 is the vertical sync pulse which is also fed to a mixer 60 to synchronize the display frame at monitor 20 with the readout at memory 12. The timing signal for multivibrator 32 on line 56 is the horizontal sync pulse which is also applied to mixer 60 to synchronize. the scan lines 3 1 to memory readout. Multivibrator 32 is set by a binary ONE in the line feed bit 24 to disable gate 34.The next horizontal sync pulse at line 56 resets multivibrator 32, enabling gate 34 to pass the dot clock pulse train to counter 30.

The pulses passed to counter 30 by gate 34 count down the number stored in the counter 30 from memory 12. As the counter 30 passes through zero, an output pulse, commonly known as the underflow pulse, is generated by counter 30 and applied to line 31. The underflow pulse on line.31 is applied to the other inputs of all four AND gates 36, 38, 42, 44. The underflow pulse on line 31 is'also fed to an OR gate 64, an OR gate 65 inthe input of the address counter 16, and via an OR gate 67 and a delay 66 to the load input 69 of the counter 30. Gate 67 also receives a vertical sync pulse on line 52 to initially load counter 30 at the start of a display frame. The underflow pulse on line 31 passes directly through gate 64 and-an AND gate 71- to mixer 60 to intensify the beam at monitor 20. Gate-71 is controlled by a blanking signal from circuit 50 which disables gate 71 to prevent video signals from reaching mixer 60 during horizontal and vertical retrace periods and at the last dot position on each scan line, i.e., dot position 512 for the above example. The underflow pulse fed to counter 16 via the gate 65 increments the address counter 16 so that the next digital word is available for entry into counter 30. The underflow pulse applied to the load input 70 via' gate 67 and delay 66 causes the next word to be entered into counter 30. The. slight delay introduced at 66 assures that the new word is loaded in counter 30.

A ONE in the horizontal line drawing bit 26 (designating that a horizontal line is to be drawn) steersan underflow pulse through gate 36 to set a bistable multivibrator 68 to its set condition. In its set condition, multivibrator 68 provides a video signal -to mixer 60 via gates 64 and 71 to-intensify the beam at monitor 20 until multivibrator 68 is reset. A ZERO in bit 26 will steer an underflow pulse on line 31 through gate 38 to reset multivibrator 68 and terminate the horizontal line. A ONE in the vertical line drawing 28 (designating that a vertical line is to be drawn) will steer an underflow pulse through gate 42 causing the underflow pulse to be stored in a recirculating shift register memory 70. The recirculating memory 70 has a number of stages corresponding to the number of effective dot positions on the display, i.e., 512 dot positions for the above example. Thedotclock pulse train from timing circuit 50 is also applied to memory 70 via line 54 to shift the register 70, causing each stored pulse to circulate in synchronism with the beam at monitor 20. Since pulses are entered in memory 70 by the underflow pulse, the stored pulse will provide avideo pulse to mixer 60 via gates '64 and 71 at the same dot position during subsequent scan lines to cause a vertical line to be displayed. A ZERO in bit 28 will steer an underflow pulse on line 31 through gate 44 to clear memory 70 at that dot position and terminate the vertical line. Hence the composite video developed by mixer 60 contains horizontal and vertical sync pulses from the raster scan timing circuit 50 to synchronize the display frame with memory 12 together with digital video signals formed by the underflow pulse on line 31 and the'outputs from the horizontal line generator 40 and the vertical line generator 46. i

The construction and operation of the data display system described hereinabove in connection with FIG. 1 will be more clearly understood by reference to the exemplary display shown in FIG. 3a and the 'corresponding digital codes shown in the table of FIG. 312. To generate the display shown in FIG. 3a, the 15 words shown in the table are stored in memory 12 at sequential memory addresses 0-14 (Column 1 of the table). At the beginning of the frame designated by point 0 at the left hand of the first upper scan line (FIG. 3a), the data from memory. address 0 0 is loaded in counter 30. The corresponding line feed bit 24 is fed to multivibrator 32 and horizontal and vertical line drawing bits 26, 28 are fed to the horizontal and vertical line generators 40, 46. In response to the ONE'in the line feed bit 24, gate 34 is disabled to inhibit transfer of a dot clock pulse train to counter 30 until the occurrence of the horizontal sync pulse at the end of the first scan line. When the beam reaches the end of the first scan line, multivibrator 32 is reset to enable gate 34 and begin countdown at counter 30. For the example being described, because the dot address 128 was entered in counter 30, upon the occurrence of the 128th dot clock pulse," an underflow pulse is generated by counter 30 and transferred via gates '64 and 71 and mixer 60 to the monitor 20 to generate a dot at the first display point 1 designated in FIG. 3d. Simultaneously, the ONE in the horizontal line bit 26 steers the underflow pulse through gate 36 to set multivibrator 68 which in turn generates a digital signal to maintain the beam on at the monitor 20. At the same time, the ONE in the vertical line bit 28 steers the underflow pulse through gate 42 and enters it into memory 70 to start the vertical line from point 1. The underflow pulse also increments the address counter 16 and, after a short delay, loads the contents of memory address 1 into counter 30. It is noted that the digital code at memory address 1 contains the number 256 which represents the distance in dot positions to the next dot to be displayed at point 2 (FIG. 3a).

Since theline feed bit 24 is a ZERO; multivibrator 32 remains in its reset state so that the gate 34 remains enabled and the dot clock pulse train at line 54continues to be passed via gate 34 to counter 30 to count down the dot address 256. After 256 pulses are counted, a second underflow pulse is generated by counter 30 at the dot position 2 (FIG. 3a). The second underflow pulse is steered by the ZERO in the horizontal line bit 26 through gate 38 to reset multivibrator 68, thereby turning off the beam at the number 2" dot position. The second underflow pulse is also steered by the ONE in the vertical line bit 28 through gate 42 into memory 70 to start the vertical line from point 2. The second underflow pulse increments the address counter and loads the contents of memory address 2 into counter 30. Because the line feed bit 24 is a ONE, multivibrator 32 is set to inhibit transfer of the dot clock pulse train to the counter 30, and the beam remains off from the number 2 dot position to the end of the second scan line. At the end of the second scan line, the horizontal sync pulse resets multivibrator 32 to enable gate 34 to pass the dot clock pulse train to counter 30.

When the beam reaches the 128th dot position in the third scan line, a digital video signal is generated by memory 70 to display a dot in vertical'alignment with the dot position 1*. When the beam reaches the 384th dot position, a second video. signal is generated by memory 70 to display a dot in the third scan line in vertical alignment with dot position 2. When the beam reaches the 512th dot position, point 3 (FIG. 3a), counter 30 generates a third underflow pulse toincre: ment the address counter and load the contents of memory address 3 into counter 30. The underflow pulse is blanked at the AND gate 71. From the foregoing partial description, the manner in which the remainder of the display is generated will be apparent.

Several important features of the data format to generate both vertical and horizontal lines merit special attention. Memory 12 contains only a dot address corresponding to the number of dot positions to the next dot to be displayed within the scan line. The line feed bit 24 determines whether the dot is to be displayed at the dot address number in the line being scanned or in the next succeeding line. In response to a ZERO line feed bit 24, a dot will be displayed in the line being scanned; and in response to a ONE, the dot will be displayed in the next succeeding line. Where several scan lines are to be traversed without generating a display, except for the dots, if any, generated by memory 70, the successive dot addresses will be the number 512 coupled with a ONE in line feed bit 24. The horizontal line bit 26 determines whether a horizontal line. is to be started or stopped at the dot address specified. The vertical line bit 28 determines whether a vertical line is to be started or stopped.

One of the more significant features of the present invention is that the display is generated with only a small memory. For example, based on the display of FIG. 3a, only words (or 180 bits) of memory were required. An equivalent display generated by a prior art system of the full graphics type would have required 6,144 bits of memory because a bit must be stored for every possible dot position within the dot field. The drastic reduction in memory required is due to three factors. The digital code is a number specifying where the dot is to be positioned within possible dot positions in the dot matrix of the display. Hence memory 12 is only required to store the number of dots to be displaed rather than the total number of dot positions that are required with a full graphics system of the prior art. Thus a significant advantage is achieved in a display composed only of dots. However, still further reductions are achieved because horizontal and vertical lines can be drawn by storing only two words.

Referring to the alternative embodiment illustrated in FIG. 4, since many of the circuit components function in substantially the same manner as those previously described in connection with FIG. 1, similar components are designated by a prime numeral. Digital data is entered into a main memory 12' from a computer 10' via an input register 14 and a load control 18'. For a display of the type described in connection with FIG. 1, each digital word may again consist of nine dot address bits 90 (FIG. 5), a line feed bit 92, a horizontal line bit 94 and a vertical line bit 96. Although the overall format of the code in F IG. 5 corresponds to that described in connection with FIG. 2, the number designated by the nine bit dot address 90 is the absolute dot position in a scan-line as contrasted to the distance to the next dot to be displayed (dot address 22, FIG. 2). During a display, each word is read sequentially from memory 12 under the control of counter 16'. The horizontal and vertical line bits 94, 96 perform the same function described in connection with FIG. 1 to condition the AND gates 36, 38", 42', 44. The nine-bit dot address 90 is applied to one input of a comparator 100. In the embodiment of FIG. 4, the dot clock pulse train on line 54' is applied to a count-up counter 102 capa-' ble of counting up the total number of useable dot positions on each scan line. For the example described in connection with FIG. 1, counter 102 is a nine-stage counter to count up to 512 dot positions. Counter 102 also receives an input reset pulse from the vertical sync line 52 to initially synchronize the counter with the beginning of the display frame at monitor 20. During each scan line at monitor 20, counter l02'receives a burst of 512 dot clock pulses and repeats the count from zero to 511 during each scan line. The instantaneous count in counter 102 is applied to asecond input of comparator 100 for comparison against the dot position number from memory 12. Comparator 100 generates an output pulse at line 106 when the instantaneous count at count 102 is equal to the dot position number from memory 12'.

The output of comparator 100 is applied to an AND gate 108 which also receives a conditioning signal from the bistable multivibrator 32'. Multivibrator 32' (FIG. 4), as with multivibrator 32 (FIG. 1), is set by a line feed bit 92 and reset by a horizontal sync pulse on line 56'. In response to a ONE in the line feed bit 92, multi' vibrator 32 disables AND gate 108 to inhibit the transfer of pulses on line 106 to line 31. A horizontal sync pulse on line 56 resets multivibrator 32 enabling gate 108 to pass pulses on line 106 to line 31'. The pulse on line 31' (FIG. 4) corresponds identically in function to the underflow pulse on line 31 from counter 30 (FIG. 1). Hence'the output pulse online 31 is transferred through'gates 64, 71' to mixer 60to form the composite video applied to .monitor 20 Simultaneously, the pulse on line 31 enables those AND gates 36', 38', 42, 44 that were previously conditioned by the horizontal and vertical line bits 94, 96. The pulse on line 31' also increments the address counter 16.

The construction and operation of the data display system of- FIG. 4 will be more readily understood by reference to the description of FIG. 1 and to the manner in which the circuit of FIG. 4 generates the display of FIG. 3a. The data required by the circuit of FIG. 4 corresponds to the data in the table of FIG. 3b except that the dot address at memory address 1 is 384 rather than 256; the dot address at memory address 4 is 320; the dot address at memory address 10 is 320; and the dot address at memory address 13" is 384. During the first scan line, comparator 100 will generate an output at line 106 when the count in counter 102 equals the dot address number 128., The output pulse on line 106 is inhibited because the line feed bit 92 is a ONE. At the end of the first scan line, a horizontal sync pulse on line 56 resets multivibrator 32' to enable gate 108. On the second scan line, when counter 102 equals the number 128, an output pulse appears on line 106 and is passed via gate 108 to line 31 to cause a dot to be displayed on monitor 20 at point 1 (FIG. 3a). The pulse on line 31 is steered by the bit 94 through gate 36' to set multivibrator 68 and start a horizontal line. Bit 96 also steers the output pulse through gate 42' into memory to start a vertical line. The output pulse also causes the contents of memory address 1 to be applied to comparator 100. Because dot address (FIG. 5) is an absolute position along a scan line, the dot address at memory address l specifies the display point 2 (FIG. 3a) as dot position 384 rather than dot. position 256 (FIG. 3b) for the system of FIG. 1. Hence as the beam traverses the second scan line, a horizontal line is drawn between points f1 and 2 (F IG. Qa). When the beam reaches point the count in couniei T02 'rEacEeE tlie' number 384 and comparator 100 generates another pulse on line 106. This pulse is steered through gate 38 to reset multivibrator 68' and end the horizontal line. The pulse is also steered through gate 42' into memory 70' to start the second vertical line. The remainder of the display is'generated in a manner substantially the same as that described in connection with the display system of FIG. 1.

Although the main memories 12, 12 have been described as a random access memory with readout control by an address counter 16, other types of memory and readout controls could be used. For example, memories 12, 12', could be one or more MOS dynamic shift registers recirculating insynchronism with the display frame so that data is shifted out in the proper sequence. The horizontal line drawing video generated by circuits 40, 40' could be gated with various clocks from" timing circuits 50, 50' to display dotted and dashed lines. Additional bits can be added into memories 1 2, 12 to specify color or different colors for different dots or lines. To implement of color display, the color data must also be transferred to memories 70, 70 at the starting point of a vertical line-Although the code format has been described as adding additional bits to each word to control line feed and horizontal and vertical line drawing, these controls could be stored as separate words that are read sequentially to generate the display. For example, the dot address word required to display a dot at a given dot position could be preceded by a control word to start or end either a horizontal or a vertical line as required. The control word would condition the gates 36, 38, 42, 44 so that on the following dot address word the output pulse on line 31 would be steered in the desired manner in generators 40, '46. The present invention also contemplates generating a vertical line of given length by a digital word identifying the starting point and the number of dots in successive scan lines required for the given length. At the starting point, the length of the line is entered in recirculating memory (70, FIG. 1; 70', FIG. 4)

and the length is decremented once during each successive scan line.

I claim:

1. In a system for displaying graphics on a beam-type display device that exhibits a television raster scan line pattern wherein the beam traverses successive generally parallel scan lines with a plurality of predetermined positions along each scan line corresponding to a respective point from which a line may be drawn in a diis to be drawn from said first dot position, first circuit means responsive to said number code to generate a beamswitching control signal when scanning'reaches said first dot position in said one scan line and means including a recirculating memory responsive to said beam switching control signal and to said line drawing code for producing a plurality of beam switching sigpulse train.

8 nals during scan lines subsequent to said one scan line, said recirculating memory having at leasta number of stages corresponding to the number of useable dot positions in any given scan line and being recirculated in synchronism with said scanning raster.

2. The system set forth inclaim 1 further comprising a raster scan timing circuit providing a dot clock pulse train containing a number of pulses equal to said useable number of dot positions in each scan line and wherein said recirculting memory is a recirculating shift register that is shifted in response to said dot clock 3. The method of generating a graphics display on a beam-type display device that exhibits a television raster scan line pattern wherein the beam traverses successive generally parallel scan lines with a plurality of dot positions along each scan line corresponding to respective points at which the beam may be intensified to display a dot, said display device having a first predetermined maximum number of dot positions at which a dot can be displayed, the steps of providing a plurality of storage locations for digital data corresponding to a second predetermined maximum number of dot positions to be intensified in any given display, said second number of dot positions being substantially less than said first number of dot positions, storing in said storage locations a plurality of digital data words coded to identify selected positions at which dots are'to be displayed, successively reading each of said words from said storage location one by one in synchronism with raster scanning over a plurality of scan lines while intensifying said beam in response to each word when said beam reaches each predetermined dot position, said words being read successively one by one by reading another code each time said beam reaches that selected dot position identified by that code which was last read, and wherein said data words are coded to designate whether each dot is to be displayed at a dot position specified thereby during the scan line then being traversed by said beam or during the next succeeding scan line to be traversed by said beam, and further comprising the step of inhibiting beam intensification at a dot position in the scan line being traversed'in response to a word coded to designate that the dot be displayed at a dot position in the next scan line 4. The method of generating a graphics display on a beam-type display device that exhibits a television raster scan line pattern wherein the beam traverses successive generally parallel scan lines with a plurality of dot positions along each scan line corresponding to respective points at which the beam may be intensified to display a dot, said display device having a first predetermined maximum number of dot positions at which a dot can be displayed, the steps of providing a plurality of storage locations for digital data corresponding to a second predetermined maximum number of dot positions to be intensified in any given display, said second number of dot positions being substantially less than said first number of dot positions, storing in said storage locations a plurality of digital data words coded to identify selected positions at which dots are to be displayed, successively reading each of said words from said storage location one by one in synchronism with raster scanning over a plurality of scan lines while intensifying said beam in response to each word when said beam reaches each predetermined dot position, said words being read successively one by one by reading another code each time said beam reaches that selected dot position identified by that code which was last read, and wherein said method further comprises the steps of coding a first word to designate that a line is to be drawn from a starting point dot position designated by said first word, and then, in response to said line drawing code, intensifying said beam at a dot position adjacent said starting point dot position.

5. The method set forth in claim 4 wherein a horizontal line is to be drawn and said first word is coded to designate that a horizontal line is to be drawn, and wherein said line is drawn by intensifying said beam at said starting point dot position and then, in response to said line drawing code, maintaining said beam intensified as it is scanned across said adjacent dot position.

6. The method set forth in claim 5 wherein a second word is coded to designate an end point dot position of said horizontal line, and said second word is further coded to designate that drawing of said horizontal line is to be terminated at said end point dot position, and wherein said method further comprises turning off said beam at said end point dot position in response to said further code of said second word.

7. The method set forth in claim 4 wherein a vertical line is to be drawn and said first word is coded to designate that a vertical line is to be drawn, and wherein said beam is intensified at said adjacent dot position by storing said starting point dot position in a recirculating memory in response to said line drawing code and recalling said stored dot position at the corresponding dot position in the next successive scan line.

8. The method set forth in claim 7 wherein said recirculating memory is a recirculating shift register, said starting point dot position is stored by entering a pulse in said shift register, and said pulse is recirculated in said shift register in synchronism with beam scanning each time said beam completes one scan line.

9. A system for displaying graphics including line-like segments on a beam-type display device that exhibits a television raster scan line pattern wherein the beam traverses successive generally parallel scan lines in a first direction and a plurality of predetermined positions along each scan line correspond to points at which the beam may be intensified to display a dot, comprising data storage means providing a digitally coded data signal having first data components each of which designates respective dot positions along said scan lines, said data signal further having second data components associated with respective first data components and designating whether its associated dot position is contained in a line segment, first circuit means operable in synchronism with raster scanning on said display device and responsive to said first data components to generate first video components for intensifying said beam at said designated dot positions and second circuit means operable in synchronism with raster scanning on said display device and responsive to both said first and said second data components to generate second video components for intensifying said beam at other dot positions such that associated first and second data components cause said beam to be intensified at oneof said predetermined dot positions on a given line segment and at other dot positions on the same given line segment.

10. The system set forth in claim 9 wherein said first circuit means generates memory sequencing signals in synchronism with said first video components and wherein said system further comprises means responsive to said memory sequencing signals to sequentially transfer data from said storage means to said first circuit means.

11. The system set forth in claim 10 further comprising raster scan timing means for generating a dot clock pulse train with each of the pulses therein representing a respective dot position along a scan line and wherein said first circuit means includes counter means and is responsive to said dot clock pulse train and said first data components to generate said first video components when raster scanning reaches said dot positions designated by said first data components.

12. The system set forth in claim 11 wherein said counter means is responsive to said pulse train to provide an instantaneous count representingthe dot position of said beam during eachscan line and wherein said first circuit means further comprises comparison means operatively coupled to said storage means and to said counter means andresponsive to said instantaneous count and said first data components to provide said first video components when raster scanning reaches dot positions designated by said first data components. i

13. The system set forth in claim 11 wherein said timing means also generates horizontal sync pulses, said data signal further includes third data components associated with respective first data components designating whether the dot position of its associated first data component is to be displayed in said line being scanned or in a subsequent line, and wherein said first circuit means further comprises means responsive to said horizontal sync pulses and to said third data components to inhibit generation of said first video components when said third data components designate beam intensification on a subsequent scan line.

14. The system set forth in claim 9 wherein said data signal further comprises third data components each of which designates respective dot positions along said scan lines and fourth data components each of which is associated with a respective third data component and designates the dot position of its associated third data component as being the end of a line segment, said first circuit means is responsive to said third data components'to generate output signals when raster scanning reaches dot positions designated by said third data components and wherein said second circuit means comprises means including gate means responsive to said output signals and to said fourth data components to inhibit said beam at said display when said beam reaches dot positions designated by said third data components.

15. The system set forth in claim 9 wherein said second data components designate that said line segments extend in a direction along said scan lines, and wherein said second circuit means comprises means including gate means responsive to said first video component signals and said second data components to generate second video components for intensifying said beam at successive dot positions along said scan lines.

16. The system set forth in claim 9 wherein said second data components designate that said line segments are generally orthogonal to said scan lines, said second circuit means comprises gate means and recirculating shift register means operated in synchronism with said scanning raster, and wherein said gate means is respon- 1 1 sive to said first video components and second data components associated therewith to cause pulses to be entered into said register means when raster scanning reaches dot positions designated by said first data components, said recirculating shift register means being arranged to generate said second video components during succeeding scan lines at dot positions therealong contained in said orthogonal line segments.

17. The method of generating a graphics display on a beam-type display device that exhibits a television raster scan line pattern wherein the beam traverses successive generally parallel scan lines with a plurality of display positions along each scan line at which the beam may be intensified to change the display, said display device having a first predetermined maximum number of display positions, the steps of providing a plurality of storage locations for digital data corresponding to a second predetermined maximum number of display positions at which the intensity of the display may be changed, storing in said storage locations a plurality of digital data words coded to identify selected display positions at which the intensity of the display is to be changed, successively reading each of said words from said storage locations one by one in synchronism with raster scanning of a plurality of scan lines while changing the intensity of the display by reading another word in response to said beam reaching that selected display position identified by that word which was last read and also changing the intensity of said display in response to said beam reaching that selected display position identified by that word which was last read so that storage locations are required for data corresponding to display positions where beam intensity is to be changed rather than for data at each of said first predetermined maximum number of display positions.

18. A system for generating displays on a beam-type display device that exhibits a television raster scan line pattern wherein each scan line includes a plurality of predetermined positions at which the intensity of said beam may be selectively switched between first and second states of intensification comprising memory storage means for storing a plurality of codes that identify selected display positions in a plurality of scan lines, first means responsive to sequencing signals to read said codes from said memory means one at a time and provide a respective digital signal representing each of said codes, second means responsive to a clock pulse signal synchronized with scanning of said beam and to each of said digital signals as it is read from memory to generate a beam control signal each time said beam reaches that display position identified by the last code read from said storage means, third means responsive to each said control signal to generate a beam switching signal adapted to switch said beam from one intensification state to the other intensification state and fourth means responsive to each said control signal to generate a respective sequencing sig nal for said first means to thereby cause another code to be read from memory identifying another selected position at which said beam is to be switched,

19. The method of generating a graphics display on a beam-type display device that exhibits a television raster scan line pattern wherein a beam scans consecutive scan lines each of which includes a plurality of predetermined positions at which the intensity of said beam may be selectively switched between first and second states of intensification to create a display comprising the steps of storing a plurality of data codes in a main memory with each code identifying a respective selected display position at which said beam is' to be switched, said stored codes identifying consecutive positions at which said beam is to be switched in at least first and second consecutive scan lines, and wherein said method further comprises generating said display by sequentially reading said codes from said memory one at a time to consecutively identify said selected display positions as said beam scans said consecutive scan lines, said sequential code reading including the steps of reading a first data code from memory, identifying a first selected display position in said first line corresponding to said first data code, generating a first beam control signal in response to said beam reaching said first display position, generating a first beam switching signal in response to said first control signal to switch said beam at said display, reading a second data from said memory in response to said first control signal to identify a second selected display position in said second line, generating a second beam control signal in response to said beam reaching said second display position, generating a second beam switching signal in response to said second control signal to switch said beam at said display, and reading a third data code from said memory in response to said second control signal to identify a third selected display position at which said beam is to be switched and. wherein each time said beam reaches a selected display position identified by that code which was read last, a beam control signal is generated to cause another code to be read from said memory.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
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Classifications
U.S. Classification345/20
International ClassificationG09G1/16, G09G1/14
Cooperative ClassificationG09G1/143, G09G1/162
European ClassificationG09G1/16D, G09G1/14D