US3691370A

US3691370A - Logic track circuit

Info

Publication number: US3691370A
Application number: US141269A
Authority: US
Inventors: Ajoy Kumar Pal
Original assignee: Individual
Current assignee: Individual
Priority date: 1971-05-07
Filing date: 1971-05-07
Publication date: 1972-09-12
Anticipated expiration: 1989-09-12

Abstract

A binary logic circuit responsive to three binary logic input signals produced by respective railway signalling circuit means coupled to a section of track and located at a train highway crossing and track portion on either side thereof for activating a warning system or crossing gate when a train is approaching or traversing a crossing from either direction and thereafter deactivating the system in a fail safe manner. The logic circuit includes a plurality of interconnected AND, OR, AND NOT logic gates. Additionally, a pair of flip-flop circuits are also connected into the circuitry for providing a determination of whether the train is approaching or receding from the crossing. The logic combination of the input signals also checks the condition of the circuit itself and provides an output indicative thereof to the system whenever the circuit adopts an abnormal state of operation.

Description

United States Patent Pal [451 Sept. 12, 1972 [54] LOGIC TRACK CIRCUIT [72] Inventor: Ajoy Kumar Pal, 2035 Prentiss Drive, Apt. 210, Downers Grove, 111. 60515 [22] Filed: May 7,1971

21 Appl. No.: 141,269

[52] US. Cl ..246/125, 246/40 [51] Int. Cl. ..B61l 1/02 [58] Field of Search ..246/34 CT, 40, 125-l30, 246/249, 34 R [56] References Cited UNITED STATES PATENTS 3,333,096 7/ 1967 Ohman et a1. ..246/34 CT FOREIGN PATENTS OR APPLICATIONS 915,701 7/1954 Germany ..246/34 R Primary Examiner-Gerald M. Forlenza Assistant Examiner-George H. Libman Attrney-Emory L. Groff and Emory L. Groff, Jr.

[5 7] ABSTRACT A binary logic circuit responsive to three binary logic input signals produced by respective railway signalling circuit means coupled to a section of track and located at a train highway crossing and track portion on either side thereof for activating a warning system or crossing gate when a train is approaching or traversing a crossing from either direction and thereafter deactivating the system in a fail safe manner. The logic circuit includes aplurality of inter connected AND, OR, AND NOT logic gates. Additionally, a pair of flip-flop circuits are also connected into the circuitry for providing a determination of whether the train is approaching or receding from the crossing. The logic combination of the input signals also checks the condition of the circuit itself and provides an output indicative thereof to the system whenever the circuit adopts an abnormal state of operation.

14 Claims, 3 Drawing Figures f 14 s 1 l2 V.

3 L02 tug 22 Y I INPUT CROSSIG. OUTPUT CPL'G RELAY CPL'G AMA 29 H|Z 2o I 32 X \(IQ FILTER l Mb osc.

PATENTED SEP 12 I972- SHEET 2 [IF 2 Tll'l nnn |I||| IIIIH INVENTOR.

WILLARD L. GE/GER LOGIC TRACK CIRCUIT BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to highway crossing protection systems for railroads and more particularly to binary digital logic circuitry which will provide fail safe operation of warning signal apparatus or crossing gates.

2. Description of the Prior Art All the presently known overlay track circuits for highway crossing protection for railway apparatus use audio frequency transmitters and receivers in various configurations with either the transmitter at the end of the warning zone and the receiver at the crossing or with the receiver at the end of the warning zone and the transmitter at the crossing. The basic principle involved in all of these track circuits is the same, however, in that an audio frequency current is transmitted into the rails by the transmitter which is adapted to energize electromechanical track relays incorporated within the receivers. Whenever a locomotive or other rolling stock shunts the transmitted current, the relay or relays become deenergized. Other electromechanical relays known as stick relays are also incorporated within the receiver and are used to differentiate between trains approaching to or receding from the crossing. The combination of stick and track relays determine the conditions of track, whether occupied or not, and provide signals accordingly to a relay which controls the crossing gate. The major disadvantage in this technique lies in the use of approximately 8,000 to 10,000 feet of cable wire and cableing necessary either to energize the transmitter at the end of the warning zone or to bring the receiver signal to the Crossing from the end of the warning zone. The transmitter and receiver in their present configurations also present problems in maintenance when either malfunctions.

Moreover, electromechanical relays incorporated within the receiver need periodic maintenance in order to guarantee reliable operation. With the use of such relays, it is difficult to limit the effective length of this track circuit, inasmuch as the effective or electrical length as determined by the electrical track resistance referred to as the track ballast resistance will vary with a change in climatic condition. These relays are likely to operate improperly whenever the resistance of the track ballast changes unless special care has been paid to the amount of current flowing through the rails. In some cases, these electromechanical devices are replaced by highly sensitive transistorized devices or ferrite cores but there is no technique, known at present, which can place both the transmitter and receiver at the crossing without the use of cableing.

SUMMARY In view of the above, it is the object of this invention to provide an improved railway signalling system for warning a motorist at a railway crossing and/or indicating occupancy of a portion of track by a train. The subject invention briefly comprises, inter alia, a constant current audio frequency transmitter of AC signal coupled across the rails of a section of track intermediate the location of a pair of separated narrow band AC shunt circuits respectively coupled across the tracks. The transmitter is located, for example, at a highway crossing located midway between the shunts so that the track section is divided into a first and a second track portion on opposite sides of the crossing. A resonantly tuned transformer is coupled by means of its primary circuit across the track proximately to or at the location of the transmitter. The voltage across its secondary circuit is rectified and fed to a first threshold circuit which is adapted to provide a first binary logic signal output. A pair of current" transformers are coupled to the track on either side of the crossing adjacently thereto as opposed to near the location of the shunts. The respective secondary windings of the current transformers are coupled to rectifiers and respective threshold circuits which provide a second and third binary logic output signal therefrom. The constant current transmitter thus transmits current into three current paths which include the tuned transformer connected to the track at thecrossing as well as the current flowing in the two track portions containing the current transformers and the respective shunts. As a train approaches or recedes from the crossing the amount of current flowing in the first and second track portion as well as the tuned transformer will change as the wheels of the train short out more or less rail segments of the track portions. The three binary logic signals are utilized to provide an indication of the occupancy condition of the track between the two shunts. A binary logic circuit comprised of AND, OR, and NOT logic gates is coupled to the three threshold circuits. It is responsive to the three binary output signals therefrom and performs a predetermined logic function taking into account all possible conditions to operate circuit means indicative of either the approach of a train from either direction, the presence of the train at the crossing, the clearance of the track upon the passing of a train, as well as providing a self check of its own logic output.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an electrical block diagram illustrative of a first embodiment of the subject invention;

FIG. 2 is a diagram illustrative of waveforms of the outputs of the three transformers utilized by the subject invention; and

FIG. 3 is an electrical block diagram of a second embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings and more particularly to FIG. 1,

reference numerals

10 and 12 designate two rails of a railroad track across which are connected two series

resonant circuits

14 and 16. Each is comprised of an inductance and a capacitance and is commonly referred to in the art as AC shunts. The

shunts

14 and 16 are shown disposed on opposite sides of a highway crossing 18 shown located preferably midway therebetween. An AC source 20 comprising a constant current, audio frequency transmitter is coupled across the

rails

10 and 12 at the crossing 18 at the

connections

21 and 22. The

connections

21 and 22 are substantially opposite each other so that as a train rolls over the location of the connections, the source 20 will be shorted out by the wheels and axle of the train.

A first transformer 24 tuned by means of the capacitor 26 and the inductance of the primary winding 28 is also coupled across the

rails

10 and 12 at the crossing adjacent the

connections

21 and 22. The primary circuit of the transformer 24 is tuned to the frequency of the AC source 20 so as to allow only current transmitted to the

rails

10 and 12 at the crossing to pass through it. The secondary winding 30 of the transformer 24 is coupled to a full-wave bridge rectifier 32 which provides a DC output which is coupled to a first threshold circuit 34 which may be, for example, a Schmitt trigger circuit. The threshold circuit 34 is operatively biased by means not shown to provide an output whenever the primary winding 28 of the transformer 24 is energized by the AC source 20, but does not provide an output when the primary winding becomes deenergized whereupon the secondary current drops to zero. The threshold circuit 34 is said to change from a binary I state to a binary state.

A second and third transformer 38 and 36 are coupled by means of their respective

primary windings

40 and 42 to the rail on opposite sides of the crossing 18 in relatively close proximity thereto, as opposed to the position of the

shunts

14 and 16. The

primary windings

40 and 42 comprise parallel branches of, for example, a single turn of copper wire which will offer less resistance and inductive reactance to audio frequency current than the rail itself. Additionally the

primary windings

40 and 42 are respectively connected across the track joints 41 and 43. The joint may be of the insulated or regular type; however, if it is an insu lated type, there also includes means, not shown, which provides for electrical continuity for any other track currents. The transformers 36 and 38 are referred to as current transformers because the voltage appearing across the

secondary windings

44 and 46 is linearly proportional to the current flow in the

primary windings

40 and 42, respectively. The secondary winding 46 is coupled to a second full-wave bridge rectifier 48 by means of a series L-C filter 51. The filter 51 is tuned to the frequency of the constant current source 20 so that the bridge rectifier 48 only receives AC signals transmitted from the audio frequency source 20. The output of the bridge rectifier 48 is connected to a second threshold circuit 50. In a like manner the secondary winding 44 of the transformer 36 is connected to a third full-wave rectifier bridge 52 by means of a tuned series filter 54. Also the output of the bridge rectifier 52 is connected to a third threshold circuit 56. The

threshold circuits

50 and 56 are identical with respect to the threshold circuit 34. The

threshold circuits

50 and 56 moreover change from a binary 0 state to a binary I state whenever the currents through the respective primary circuits increase from a predetermined value indicative of a no train condition in the respective track portion on either side of the crossing 18 due to the passage of a train over the track between the shunts l4 and 16.

In the subject embodiment considered thus far, the AC source 20 transmits a substantially constant current, sinusoidal audio frequency signal into the rails at the

connections

21 and 22 and current flows through the

rails

10 and 12 in two track portion loops including the

shunts

14 and 16 respectively with the transformers 36 and 38 providing outputs across their respective

secondary windings

44 and 46 proportional to the magnitude of the loop currents. Additionally, a portion of the constant current output is divided into the primary winding 28 of the tuned transformer 24 located at the crossing. The movement of a train in either direction over the section of track intermediate the shunts l4 and 16 affects the voltage output of the transformers 36 and 38 due to the shorting effect of the train wheels as the train moves across the

rails

10 and 12. For example, as a train moves from left to right toward the crossing 18 shown in FIG. 1 the train, not shown, first passes the shunt 16 and in doing so reduces the track resistance in track portion-1 which will cause an increase in the respective loop current. Since a constant magnitude of current is coupled to the track, the current to the transformer 24 will be reduced in substantially like amount. The track portion '2, including the shunt portion 14 and transformer 36, however, is relatively unaffected. Thus in a no train condition, the current flowing through each of the three circuit branches is proportional to its own impedance; however, the train movement over the

rails

10 and 12 will affect the circuit impedance of the track portions on either side of the crossing. Since the

threshold circuits

34, 50 and 56 provide outputs of a binary nature, i.e., having two possible output states, the signals A, B and C generated by the

threshold circuits

50, 34 and 56 shown in FIG. 1, respectively comprise logic input signals, the combination of which are adapted to provide an indication of all possible conditions of the track section on either side of the crossing 18.

The following truth table I-A illustrates the track condition and required operating state of for example, a crossing gate located at a railroad crossing for trains moving from track portion-1 toward track portion-2.

gate open Considering now the case for trains moving from track portion-2 toward track portion-l reference is made to the truth table II-A shown below.

TRUTH TABLE II-A A B C condition of track & crossing gate state 0 1 0 No-traln-gate open 0 l 1 Train approaching-gate closed 0 0 0 Train on the crossing-gate closed I l 0 Train receding-gate open 0 0 1 Not Possible state I 1 1 Not Possible state I 0 0 Not Possible state 1 0 I Not Possible state 0 I 0 No-train-train clear of track portion-1.

Gate open.

In order to make the system fail safe, the NOT POSSIBLE states shown in the Truth Tables l-A and lI-A must be considered and the crossing gate must be activated whenever a NOT POSSIBLE situation develops within the circuitry for logically implementing the truth tables. This will be considered subsequently. It is also evident from the above that the combination of the signals A, B and C are the same when a train approaches the crossing 18 from track portion-1 as a train receding from the same crossing in the opposite direction. In order to differentiate such a situation, a direction sense can be obtained by the use of two additional signals x and y, such as shown by the partial Truth Tables I-B and II-B illustrated below.

TRUTH TABLE I-B A B C x y Condition of gate It is evident that the binary states of x and y for the two middle conditions of the truth tables merely reverse states. These signals can be generated whenever a change of state of the

threshold circuits

50 or 56 changes state due to the increased flow of current through the rails caused by a train approaching toward the crossing. Each will differentiate between trains receding from a crossing and trains approaching the crossing until the train has passed out of the track portions 1 and 2.

In view of the truth tables illustrated above, a signal having for example a binary 1 state which is indicative of a track condition necessitating the actuation of a warning device or closing at crossing gates must satisfy the following Boolean equation:

K-E-C A-R'C A-fi-C A-B-C +K-+K-B-0x A-BQ- y 1 l. Equation (1) can be simplified by rearranging terms to:

An embodiment of a logic circuit adapted to mechanize or implement equation (2) is additionally shown in FIG. 1 and constitutes a plurality of interconnected AND, OR, and NOT binary logic gates as well as a pair of bistable circuits commonly referred to as flip-flops. The two flip-flop circuits are utilized for deriving the Yand ysignals referred to above.

More particularly, the binary logic signal A from threshold circuit 50 is commonly fed to a first NOT circuit (logic inverter) 58 as well as to one input of a four input OR gate 60 and the AND

gates

62 and 64 which have two and three inputs respectively. The B binary logic signal is fed from threshold circuit 34 to the input of the NOT circuit 66 as well as to one input of the three input AND gate 68. The third binary logic signal C generated by the threshold circuit 56 is coupled to the input of the NOT circuit 70 as well as to one input of the four input OR circuit 72 and one input of the two input AND

gate

62 and 74.

The complementary binary logic signal A provided at the output of the NOT circuit 58 is coupled into one input of the three input AND

gates

68 and 76 as well as to one input of the OR circuit 72. The complementary signal 8 provided at the output of the NOT circuit 66 is coupled to one input of the

OR circuits

60 and 72 as well as to one input of the AND

gates

64, 74 and 76. Similarly, the complementary logic signal C generated by the NOT circuit 70 is commonly coupled to one input of the OR circuit 60 as well as one input of the AND

gates

68, 64, and 76. The outpu t of the AND circuit 68 comprises the logic signal A-B'C. This signal is commonly applied to the R(reset) inputs of the flip-

flops

78 and 80 through a differentiator and a diode D The outputs of the OR

gates

60 and 72 which comprises the logic signals A++C+ and A+ B+C+:v, respectively, are each fed to a separate input of the two input AND gates 82 which is followed by a NOT gate 84 coupled thereto. Additionally, the logic output signal-of the OR gate 60 is fed to the S(set) input of the flip-flop circuit through a differentiator 79 and a diode D while the output of the OR gate 72 is fed to the corresponding S input of the flip-flop circuit 78 through a differentiator 77 and a diode D The output of the AND

gates

76, 62, 74, and 64 are applied to separate inputs of a four input OR gate 86 whose output comprises the logic signal A-C+B-C A--C +A'E-C. The output of the NOT circuit 84 on the other hand comprises the logic signal (A+E+C+E) X+I+c+y With the outputs of the OR circuit 86 and the NOT circuit 84 applied to separate inputs of a two input OR gate 88, the output therefrom comprises a binary logic signal corresponding to the equation (2).

Normally when there is no train on the track portions 1 and 2 shown in FIG. 1, the

primary windings

40 and 42 of the current transformers 36 and 38, respectively, will be energized with a certain amount of the current injected to the

rails

10 and 12 at the

connections

21 and 22 located at the crossing 18. As noted earlier, the amount of current will depend on the impedance of the two track portions as well as the impedance of the tuned primary circuit of transformer 24 also coupled to the

rails

10 and 12 at the crossing 18. The current flowing through the respective

secondary windings

30, 44 and 46 will depend on the turns ratio of each of the transformers according to the relationship:

Current through secondary winding Current through primary winding Primary number of turns 7 igecondary number of turns The values of the impedancesoftlie track 655115 1" and 2 as well as the impedance of the tuned circuit are so selected in combination with the turns in the respective transformers so that the currents flowing through the inputs of the

threshold devices

50, 34, and 56 at no train condition will cause threshold circuit 50 to provide a binary 0 output, threshold circuit 34 to provide a binary l output, and threshold circuit 56 to provide a binary output. The combination of the binary logic outputs A, B, and C at this time can be expressed as (0, l, 0). This combination of binary signals applied to the inputs of the AND gate 68 will provide a binary l at the output thereof which is commonly fed to the differentiator 75. Whenever this output changes from a binary 1 to a binary 0 or from a binary "O" to a binary l there is an output across the differentiator 75. The signals at the R- terminal of the flipflops appear only at the output terminal A from binary 0 to binary l however. This resets the flip-flops causing a binary 0 to appear at the output terminal A thereof and comprises outputs Y and 3 from the

flipflops

78 and 80. Whenever the outputs of the OR

gates

60 or 72 change from a binary l to a binary O, the respective differentiator and diode combination will provide a signal to set the respective flip-flop, causing a binary l to appear at the A terminal of the respective flip-flop. This state will persist until the combination (A, B, C) turns back to (0, 1, 0) at which time both

flipflops

78 and 80 will be reset.

At the time when the signal (A, B, C) is a binary (0, l, 0) there will be a binary 1 provided at the output of the AND gate 82; however, a binary 0 will appear at the output of the NOT circuit 82. In a similar manner, a binary 0 will appear at the outputs of the AND

gates

76, 62, 74 and 64. A binary 0 output will likewise be presented at the output of the OR gate 86. Since both inputs to the OR gate 88 is a binary 0, its output will be a binary 0. For such a condition of the binary output of the OR gate 88, no actuating signal will be coupled to external apparatus such as a crossing relay, which will close a crossing gate or other signalling means.

When a train enters track portion-l from the left and passes the point 90 on rail 10 shown in FIG. 1 located near the narrow band shunt 16, a current. through the track portion'l will increase as shown by waveform 92 of FIG. 2 starting at the time t whereas the currents through the primary winding 28 of transformer 24 and track portion-2 as shown by

waveforms

94 and 96, respectively, of FIG. 2 will decrease. The increase of current through track portion-l after the time t will cause an increase of current through a secondary winding 46 of transformer 38 which will cause the threshold circuit 50 to switch states whereupon the logic signal A will change from a binary 0 to a binary I. However, there will be no change in states of

threshold circuits

34 and 56 and consequently the logic signals B and C will maintain its respective binary l and 0 state. The current through the secondary winding 46 will increase linearly until the train reaches point 98 on rail 10. As long as the train is between points 90 and 98, the combination of the signals A, B, C will be (1, l, 0). This will cause the output of the OR gate 72 to be in a binary 0 state. This change in the output of OR gate 72 will set the flip-flop 78 whereupon the it signal will switch from a binary 0 to a 1. This state of flipflop 78 will be maintained until the output of AND gate 68 changes from binary 0 to a binary 1." Whenever any input to AND gate 82 becomes a binary 0, the output thereof will be a binary 0, resulting in a binary 1 input being provided to the OR gate 88 from the NOT gate 84. There will also be no change in the outputs from AND

gates

76, 62, 74 and 64, however, the output of the OR gate 88 will be a binary l which is of proper polarity to actuate a crossing relay, etc.

When the train reaches point 98, the wheels of the train next will shunt the primary winding 42 and the current in the secondary winding 46 will immediately drop to zero as shown in FIG. 2 at the time t The current in the primary winding 28 will increase momentarily due to the constant current input to the rails until point 100 is reached at the time t as shown in FIG. 2 whereupon the wheels and axle combination of the leading truck of the train will shunt

connections

20 and 22 shown in FIG. 1. The current in the

secondary windings

30 and 44 will also drop to zero as shown by

waveforms

94 and 96 in FIG. 2. The time period between t, and t;, is of a negligible nature due to the relative proximity of points 98 and 100, as well as the speed of the train. As a result the momentary increase in the primary current in winding 28 of transformer 24 is of a transient nature, and will not affect the operation of the crossing relay or other signalling devices connected to the OR gate 88. These changes are not abrupt due to the presence of inductance in the circuit. At the time the binary state of the signals A, B and C will become (0, 0, O). This will cause a binary 1 to appear at the output of the AND gate 82 but a binary 0 at the output of the NOT gate 84; however, a binary l will appear at the output of AND gate 76 which will effeet a binary 1 output of the OR gate 88 to render the external apparatus coupled thereto in an operative state. The other AND

gates

62, 64 and 74 will have binary 0 outputs at this time.

When the last or rear wheels and axle of a train passes point 102 shown in FIG. 1 as the train passes from left to right and at a time t, as shown in FIG. 2, the three

transformers

24, 36 and 38 will again become energized from the constant current source 20. However, the current in the secondary winding 44 of transformer 36 will immediately jump to a high value as shown by waveform 96 of FIG. 2 but the

transformers

24 and 38 will be energized by current less than the value of the no train condition as shown by

waveforms

94 and 92, respectively. As a result, the combination of the logic signals A, B, and C will become (0, l, 1). Under this condition the output of OR gate 72 will become a binary l whereas the output of OR gate 60 remains a binary I because the signal I applied thereto has been triggered to a binary 1 state. This will bring a change in the binary output of AND gate 82 from a binary 0 state to a binary 1 Consequently, the output of NOT gate 84 will become a binary 0. This condition will be maintained until the train passes point 104 along rail 10 near the shunt l4 whereupon the current in the transformer 36 decreases to a no train value as shown at the time in FIG. 2. As a result thereof the state of signals A, B, and C will again be (0, 1, 0). This binary combination will provide a binary 1 output from the AND gate 68 which will reset the flip-

flops

72 and 78 to a binary 0 again bringing the circuit to a quiescent state. For trains moving from right to left between the

shunts

14 and 16, the opposite reasoning will prevail but the operation again is the same, except that the condition of the flip-flops 78 and will reverse as indicated in Truth Tables [-B and II- B.

Thus the combination of the

differentiators

75, 77 and 79 and the respective diodes D D and D causes each flip-

flop

78 and 80 to change state only when the output pulse at the logic OR

gates

60 or 72 changes from a binary l to a binary 0. The combination will enable pulses for yto be in a binary l state so long as a train is within the warning zone. Each flip-flop will return to its normal state (3: 0, y when the AND gate 68 turns back to a binary l from a binary 50.77

All of the logic circuitry including the threshold circuits shown in FIG. 1 are particularly adapted to be fabricated from semiconductor devices which may or may not be in integrated circuit form. However, the use of cableing of extensive length is eliminated because the transmitter and receiver means are located at or substantially near the crossing. Even though current through the narrow band shunts will change due to the variation of track resistance caused by the variation of climatic conditions, the current through the current transformers will remain substantially constant. As a result, the circuitry shown in FIG. 1 will be more reliable than other known track circuits which perform the same function.

A second embodiment of the subject invention is shown in FIG. 3 and is similar to the first embodiment shown in FIG. 1; however two additional transformers 106 and 108, referred to as summing transformers, are respectively coupled to the full-

wave bridge rectifiers

48 and 55 from the current transformers 36' and 38' The current transformers 36 and 38' are modifications of the current transformers shown in FIG. 1 in that the subject transformers now include the center tapped secondary windings 45 and 47, respectively. Secondary winding 45 includes two end terminals 110 and 112 and a center tap tenninal 114. Similarly secondary winding 47 includes

end terminals

116 and 118 and center tap terminal 120. r The secondary windings 45 and 47, moreover, are coupled together with such a polarity that the current from one current transformer will oppose the current from the other. More particularly, the end terminals 110 and 112 of winding 45 are directly connected to the center tap terminal 120 of winding 47 while the

end terminals

116 and 118 are directly connected to the center tap terminal 1 14 of winding 45. Additionally the primary winding 122 of the summing transformer 106 is coupled across the common connection between

terminals

118 and 114, and 120 and 112. The primary winding 124 of summing transformer 108, on the other hand, is coupled across the common connection between

terminals

112 and 120, and 114 and 116.

With such a connection and assuming a no train condition, irrespective of weather (dry or wet), the currents flowing through the track portions 1 and 2 are the same due to circuit symmetry and as a result the overall or resultant currents in each primary winding 122 and 124 is zero. During this time each of the

threshold circuits

50 and 56 will be in a binary 0" state. Whenever there is an unbalance of the currents flowing through the

primary windings

122 and 124, the respective secondary winding 126 and 128 will be energized accordingly. The

threshold circuits

50 and 56 are biased such that they will change to a binary 1 state for trains approaching from track portion 1 and from track portion 2 respectively.

With the configuration shown in FIG. 3 the logic expressed in equation (2) can also be simplified to:

This eliminates the AND

gates

64, 74, and 76 heretofore required and illustrated in FIG. 1.

Itshould also be pointed out with regard to FIG. 3 that in dry weather the ballast leakage resistances will be high whereas at wet weather the ballast leakage resistances will be low. The variation of ballast leakage resistances will cause a variation of current through the current transformers 36 and 38 even at no-train condition. Despite the above fact an equal amount of current will flow through the current transformers. This will cause an equal but opposite ampere-turn in each primary winding 122 and 124 of the summing transformers 106 and 108 resulting in zero outputs at the respective secondary windings 126 and 128. The output pulses from the

threshold circuits

50, 34, and 56 will be a logic (0, l, 0) irrespective of the condition of ballast. The crossing gate will therefore remain open even without any special attention to the amount of current flowing through the rails at varying ballast conditions.

The disconnection or breakage of connector or bonded wire will introduce a high resistance in the track circuit. This additional resistance will cause in the other track portion an increase flow of current which will energize the respective primary winding of the summation transformers 106 and 108. As a result either one of the

threshold devices

50 or 56 will change to a binary l state from a binary 0 state. The outputs of the

threshold circuits

50, 34 and 56 will be the same as though a train is approaching. This will result in the operation of the crossing relay. The crossing relay will remain in this condition until the broken connector or wire is replaced and the track circuit is brought to normal condition. When a train approaches the crossing point the current in the current transformer 36 or 38' nearer to the approaching train will gradually increase. The primary winding of the respective summation transformer 108 or 106 will be energized and the respective threshold device will change state bringing in the operation of the crossing relay.

Thus the input connections for the summation transformers are such that both these transformers will remain deenergized at no train condition as well as at varying ballast conditions because equal amount of current will flow through the two portions of rails. A slight unbalance of currents in the two current transformers will energize the respective summation transformer. The respective threshold device in turn will give an output resulting in the operation of the crossing relay.

Having disclosed what is at present considered to be the preferred embodiment of the subject invention, 1 claim as my invention:

1. A system for controlling railway signalling apparatus of the type described, comprising in combination:

a section of track including a pair of rails adapted to carry electrical current;

a first and a second alternating current shunt coupled across said rails respectively at opposite ends of said track section;

an alternating current source coupled across said rails at a location-intermediate said shunts;

a first transformer having a primary and a secondary circuit including circuit means for coupling the primary circuit thereof across said rails adjacent the location of coupling of said alternating current source;

a second and a third transformer each having a primary and a secondary circuit and including circuit means coupling the primary circuit in parallel circuit relationship respectively with a segment of a rail on opposite sides of the location of the coupling of said current source and said primary circuit of said first transformer, said current source feeding a predetermined magnitude of current in diverse directions through to said rails, said shunts and the primary circuits of said second and third transformer as well as the primary circuit of said first transformer whereupon the travel of a train over said track section alters the amount of current flowing in the respective primary circuits of said three transformers by the shunting action of the wheels thereof;

current rectifier means coupled to the secondary circuits of said first, second, third transformer for providing a DC output signal proportional to the current flow in the respective primary circuits;

first threshold circuit coupled to said rectifier means coupled to said secondary circuit of said first transformer means providing an output signal corresponding to a first of two possible binary logic states during a first track condition and a second binary logic state when the current in the respective primary decreases to predetermined value in response to a second track condition;

a second and third threshold circuit respectively coupled to the said rectifier means coupled to the secondary circuits of said second and third transformer, each of said threshold circuits providing an output signal corresponding to a mutually opposite or second binary logic state during said first track condition and a first binary state when the current in the respective secondary circuit exceeds a predetermined value in response to said second track condition; and

binary logic circuit means coupled to said first, second and third threshold circuits and being responsive to the binary logic states of the output signals thereof to energize apparatus for a predetermined binary logic combination of output signals from said threshold circuits.

2. The invention as defined by claim 1 wherein said alternating current source comprises a constant current, audio frequency transmitter.

3. The invention as defined by claim 2 wherein said first and second shunt circuits are resonant at the frequency of operation of said transmitter thereby providing a relatively low impedance to current flow between said rails at the location thereof, and additionally including circuit means coupled to the primary circuit of said first transformer for tuning s'aid primary circuit to said predetermined frequency of said transmitter means so as to be responsive only to a current of said predetermined frequency.

4. The invention as defined by claim 3 and additionally including circuit means coupled to the secondary circuits of said second and third transformer for providing a low circuit impedance for a secondary current flow of said predetermined frequency while providing a relatively high impedance for all other frequencies.

5. The invention as defined by claim 4 wherein said second and third transformers comprise current transformers wherein the current flowing in said secondary circuits is proportional to the current in said primary circuit and wherein said primary circuits respectively provide a relatively smaller impedance to current flow than said rail.

6. The invention as defined by claim 1 wherein said secondary circuit of said second and third transformer each includes a secondary winding having a first and a second secondary winding portion; and

additionally including a first and second summing transformer, each having a primary winding and a secondary winding; and

including circuit means coupling said first secondary winding portion of said second and third transformer in mutually opposite polarity relationship across said primary winding of said first summing transformer and said second secondary winding portion of said second and third transformer in mutually opposite polarity relationship across said primary winding of said second summing transformer; and

circuit means coupling said secondary winding of said first summing transformer to said rectifier means coupled to said second transformer and means coupling said secondary winding of said second summing transformer to said rectifier means coupled to said third transformer.

7. The invention as defined by claim 6 wherein said second and third transformers are comprised of current transformers wherein the current flowing in said respective secondary windings is proportional to the current in said primary circuit.

8. The invention as defined by claim 1 wherein said logic circuit means includes means for implementing the binary logic expression:

wherein A is the binary logic output signal from said second threshold circuit, B is the binary logic output signal from said first threshold circuit, C is the binary output logic signal from said third threshold circuit and wherein a? and Tare binary logic signals derived by said logic circuit to differentiate the direction of travel of a train over said track section, and including a first, second and a third logic inverter circuit coupled to said first, second and third threshold circuit for respectively providing an output signal comprising the logic signals A, E, and C.

9. The invention as defined by claim 8 and additionally including a first AND binary logic circuit 76 coupled to the output of said first, second and

third logic inverter

58, 66 and 70 for providing a logic output signal A-B'C;

a second AND binary logic circuit 62 coupled to said first threshold circuit 34 and said third threshold circuit 56 for providing a logic output signal A-C;

a third AND binary logic circuit 74 coupled to said third threshold circuit 56 and said second logic inverter circuit 66 for providing a logic output signal B'C;

a fourth AND binary logic circuit 64 coupled to said first threshold circuit 34 and said second and third

logic inverter circuits

66 and 70 for providing a logic output signal A-B-C;

a first OR binary logic circuit 86 coupled to the outputs of said first, second and third and fourth AND

circuits

76, 62, 74 and 64, a second OR circuit 88 having one input thereof coupled to the output of said first OR circuit 86;

a fifth AND binary logic circuit 68 having a plurality of inputs respectively coupled to said first logic inverter 58, said second threshold circuit 50 and said third logic inverter 70 for providing a logic output signal A-B-C;

a first and a second flip-

flop circuit

78 and 80 having one input terminal R coupled to the output of said fifth logic AND gate 68 and respectively providing output signals corresponding to a? and y,-

a third OR binary logic circuit 60 coupled to said first flip-flop 78 circuit, said first threshold circuit 34, said second logic inverter circuit 66 and said third logic inverter fiiguit 70 for providing a logic output signal A+B+C+x;

a fourth logic OR binary logic circuit 72 coupled to said second flip-flop circuit 80, said first logic inverter 58, said second logic inverter 66, said third threshold cirgiit 56 for providing a binary logic output signal A+B+C+ 1;

circuit means respectively coupling the outputs of said third and fourth OR

circuits

60 and 72 respectively to another input S of said second and first flip-

flop circuits

80 and 78;

a sixth AND binary logic circuit 82 having a first input coupled to the output of said third OR logic circuit 60 and a second input coupled to the output of said fourth OR logic circuit 72; and

a fourth logic inverter circuit 84 coupled to the output of said sixth AND circuit 82 and including circuit means coupling its output to another input of said second OR circuit 88.

10. The invention as defined by claim 8 and additionally including:

first differentiator means 75 and first diode means D coupled together between the output of said fifth AND gate 68 and said R input terminal of said first and second flip-

flop circuit

78 and 80;

second differentiator means 77 and second diode means D coupled together between the output of said fourth OR circuit 72 and said S input terminal of said first flip-flop circuit 78; and

third differentiator means 79 and third diode means D coupled together between the output of said third OR circuit 60 and said S input of said second flip-flop circuit 80.

11. The invention as defined by claim 6 wherein said binary logic circuit means includes means for implementing the binary logic expression:

(A+++x) (A++C+y) A-C+B 1 wherein A is the binary logic output signal from said second threshold circuit and A is the complement thereof, B is the binary logic output signal from said first threshold circuit and P; is the complement thereof,

C is the binary outpt 1t logic signal from said third threshold circuit and C is the complement thereof and 12. The invention as defined by claim 11 and wherein said logic circuit means is comprised of at least a first, second and a third

logic inverter circuit

58, 66 and coupled to said first, second and

third threshold circuit

34, 50, and 56 for respective lyprovidi ng output signals comprising the logic signals A, B, and C.

13. The invention as defined by claim 12 and additionally including:

a first AND binary logic circuit 62 coupled to said first threshold circuit 34 and said third threshold circuit 56 for providing a logic output signal A-C;

a second AND binary logic circuit 68 having a plurality of inputs respectively coupled to said first logic inverter 58, said second threshold circuit 50 and said third logi c in erter 70 for providing a logic output signal A'B-C;

a first and a second flip-

flop circuit

78 and 80 having one input terminal R coupled to the output of said second AND gate 68 and respectively providing output signals corresponding to Eand y;

a first OR binary logic circuit 60 coupled to said first flip-flop 78 circuit, said first threshold circuit 34, said second logic inverter circuit 66 and said third logic inverter circuit 70 for providing a logic output signal A++O+i;

a second OR binary logic circuit 72 coupled to said second flip-flop circuit 80, said first logic inverter 58, said second logic inverter 66, said third threshold circuit 56 for providing a binary logic output signal A+B+C+y;

circuit means respectively coupling the outputs of said first and second OR

circuits

60 and 72 respectively to another input S of said second and first flip-flop circuits 80 and 7 8;

a third AND binary logic circuit 82 having a first input coupled to the output of said third OR logic circuit 60 and a second input coupled to the output of said fourth OR logic circuit 72;

a fourth logic inverter circuit 84 coupled to the output of said third AND circuit 82; and

a third OR binary logic circuit 88 having a first input coupled to the output of said fourth logic inverter circuit 84, a second input coupled to the output of said first AND circuit 62 and a third input coupled to the output of said second logic inverter circuit 66, and an output coupled to external railway apparatus.

14. The invention as defined by claim 13 and additionally including:

first differentiator means 75 and first diode means D coupled together between the output of said second AND logic circuit 68 and said one input terminal R of said first and second flip-flop circuit 78 and second differentiator means 77 and second diode means D coupled together between the output of said second OR circuit 72 and another input S of said first flip-flop circuit 78; and

third differentiator means 79 and third diode means D coupled together between the output of said first OR circuit 60 and another input S of said second flip-flop circuit 80.

Q I Page .1 UNITED STATES PATENT OFFICE CERTIFICATE OF CQE CTION Patent No. 316914370 Dated September 12 1972 lnventofls) 'A-JOY KUMAR PAL 7 It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shownv below:

In the heading, the following should appear:

-Assignee: Bortec, Inc. Oak Brook, Illinois-m Disregard the drawings preceding the specification and claims as well as the view on the cover sheet. The specification and claims should be read in conjunction with the sheets of drawings following the claims, as shown on the attached sheets.

Signed and sealed this 31st day of December 1974.

(SEAL) Attest:

McCOY M. GIBSON JR. C. MARSHALL DANN Attesting Officer Commissioner of Patents USCOMM'DC 50376-P69 U.S. GOVERNMENT PRINTlNG OFFICE: I969 0-355-33 5 FORM PO-105O (10-69)

Claims

1. A system for controlling railway signalling apparatus of the type described, comprising in combination: a section of track including a pair of rails adapted to carry electrical current; a first and a second alternating current shunt coupled across said rails respectively at opposite ends of said track section; an alternating current source coupled across said rails at a location intermediate said shunts; a first transformer having a primary and a secondary circuit including circuit means for coupling the primary circuit thereof across said rails adjacent the location of coupling of said alternating current source; a second and a third transformer each having a primary and a secondary circuit and including circuit means coupling the primary circuit in parallel circuit relationship respectively with a segment of a rail on opposite sides of the location of the coupling of said current source and said primary circuit of said first transformer, said current source feeding a predetermined magnitude of current in diverse directions through to said rails, said shunts and the primary circuits of said second and third transformer as well as the primary circuit of said first transformer whereupon the travel of a train over said track section alters the amount of current flowing in the respective primary circuits of said three transformers by the shunting action of the wheels thereof; current rectifier means coupled to the secondary circuits of said first, second, third transformer for providing a DC output signal proportional to the current flow in the respective primary circuits; a first threshold circuit coupled to said rectifier means coupled to said secondary circuit of said first transformer means providing an output signal corresponding to a first of two possible binary logic states during a first track condition and a second binary logic state when the current in the respective primary decreases to predetermined value in response to a second track condition; a second and third threshold circuit respectively coupled to the said rectifier means coupled to the secondary circuits of said second and third transformer, each of said threshold circuits providing an output signal corresponding to a mutually opposite or second binary logic state during said first track condition and a first binary state when the current in the respective secondary circuit exceeds a predetermined value in response to said second track condition; and binary logic circuit means coupled to said first, second and third threshold circuits and being responsive to the binary logic states of the output signals thereof to energize apparatus for a predetermined binary logic combination of output signals from said threshold circuits.

3. The invention as defined by claim 2 wherein said first and second shunt circuits are resonant at the frequency of operation of said transmitter thereby providing a relatively low impedance to current flow between said rails at the location thereof, and additionally including circuit means coupled to the primary circuit of said first transformer for tuning said primary circuit to said predetermined frequency of said transmitter means so as to be responsive only to a current of said predetermined frequency.

6. The invention as defined by claim 1 wherein said secondary circuit of said second and third transformer each includes a secondary winding having a first and a second secondary winding portion; and additionally including a first and second summing transformer, each having a primary winding and a secondary winding; and including circuit means coupling said first secondary winding portion of said second and third transformer in mutually opposite polarity relationship across said primary winding of said first summing transformer and said second secondary winding portion of said second and third transformer in mutually opposite polarity relationship across said primary winding of said second summing transformer; and circuit means coupling said secondary winding of said first summing transformer to said rectifier means coupled to said second transformer and means coupling said secondary winding of said second summing transformer to said rectifier means coupled to said third transformer.

8. The invention as defined by claim 1 wherein said logic circuit means includes means for implementing the binary logic expression: A.C + B.C + A.B.C + A.B.C + (A+B+C+x).(A+B+C+y) 1 wherein A is the binary logic output signal from said second threshold circuit, B is the binary logic output signal from said first threshold circuit, C is the binary output logic signal from said third threshold circuit and wherein x and y are binary logic signals derived by said logic circuit to differentiate the direction of travel of a train over said track section, and including a first, second and a third logic inverter circuit coupled to said first, second and third threshold circuit for respectively providing an output signal comprising the logic signals A, B, and C.

9. The invention as defined by claim 8 and additionally including a first AND binary logic circuit 76 coupled to the output of said first, second and third logic inverter 58, 66 and 70 for providing a logic output signal A.B.C; a second AND binary logic circuit 62 coupled to said first threshold circuit 34 and said third threshold circuit 56 for providing a logic output signal A.C; a third AND binary logic circuit 74 coupled to said third threshold circuit 56 and said second logic inverter circuit 66 for providing a logic output signal B.C; a fourth AND binary logic circuit 64 coupled to said first threshold circuit 34 and said second and third logic inverter circuits 66 and 70 for providing a logic output signal A.B.C; a first OR binary logic circuit 86 coupled to the outputs of said first, second and third and fourth AND circuits 76, 62, 74 and 64, a second OR circuit 88 having one input thereof coupled to the output of said first OR circuit 86; a fifth AND binary logic circuit 68 having a plurality of inputs respectively coupled to said first logic inverter 58, said second threshold circuit 50 and said third logic inverter 70 for providing a logic output signal A.B.C; a first and a second flip-flop circuit 78 and 80 having one input terminal R coupled to the output of said fifth logic AND gate 68 and respectively providing output signals corresponding to x and y; a third OR binary logic circuit 60 coupled to said first flip-flop 78 circuit, said first threshold circuit 34, said second logic inverter circuit 66 and said third logic inverter circuit 70 for providing a logic output signal A+B+C+x; a fourth logic OR binary logic circuit 72 coupled to said second flip-flop circuit 80, said first logic inverter 58, said second logIc inverter 66, said third threshold circuit 56 for providing a binary logic output signal A+B+C+y; circuit means respectively coupling the outputs of said third and fourth OR circuits 60 and 72 respectively to another input S of said second and first flip-flop circuits 80 and 78; a sixth AND binary logic circuit 82 having a first input coupled to the output of said third OR logic circuit 60 and a second input coupled to the output of said fourth OR logic circuit 72; and a fourth logic inverter circuit 84 coupled to the output of said sixth AND circuit 82 and including circuit means coupling its output to another input of said second OR circuit 88.

10. The invention as defined by claim 8 and additionally including: first differentiator means 75 and first diode means D3 coupled together between the output of said fifth AND gate 68 and said R input terminal of said first and second flip-flop circuit 78 and 80; second differentiator means 77 and second diode means D1 coupled together between the output of said fourth OR circuit 72 and said S input terminal of said first flip-flop circuit 78; and third differentiator means 79 and third diode means D2 coupled together between the output of said third OR circuit 60 and said S input of said second flip-flop circuit 80.

11. The invention as defined by claim 6 wherein said binary logic circuit means includes means for implementing the binary logic expression: (A+B+C+x) . (A+B+C+y) + A.C+B 1 wherein A is the binary logic output signal from said second threshold circuit and A is the complement thereof, B is the binary logic output signal from said first threshold circuit and B is the complement thereof, C is the binary output logic signal from said third threshold circuit and C is the complement thereof and wherein x and y are binary logic signals derived by said logic circuit to determine the direction of travel of a train over said track section.

12. The invention as defined by claim 11 and wherein said logic circuit means is comprised of at least a first, second and a third logic inverter circuit 58, 66 and 70 coupled to said first, second and third threshold circuit 34, 50, and 56 for respectively providing output signals comprising the logic signals A, B, and C.

13. The invention as defined by claim 12 and additionally including: a first AND binary logic circuit 62 coupled to said first threshold circuit 34 and said third threshold circuit 56 for providing a logic output signal A.C; a second AND binary logic circuit 68 having a plurality of inputs respectively coupled to said first logic inverter 58, said second threshold circuit 50 and said third logic inverter 70 for providing a logic output signal A.B.C; a first and a second flip-flop circuit 78 and 80 having one input terminal R coupled to the output of said second AND gate 68 and respectively providing output signals corresponding to x and y; a first OR binary logic circuit 60 coupled to said first flip-flop 78 circuit, said first threshold circuit 34, said second logic inverter circuit 66 and said third logic inverter circuit 70 for providing a logic output signal A+B+C+x; a second OR binary logic circuit 72 coupled to said second flip-flop circuit 80, said first logic inverter 58, said second logic inverter 66, said third threshold circuit 56 for providing a binary logic output signal A+B+C+y; circuit means respectively coupling the outputs of said first and second OR circuits 60 and 72 respectively to another input S of said second and first flip-flop circuits 80 and 78; a third AND binary logic circuit 82 having a first input coupled to the output of said third OR logic circuit 60 and a second input coupled to the output of said fourth OR logic circuit 72; a fourth logic inverter circuit 84 coupled to the output of said third AND circuit 82; and a third OR binary logic circuit 88 having a first input coupled to the output of said fourth logic inverter circuit 84, a second input coupled to the output of said first AND circuit 62 and a third input coupled to the output of said second logic inverter circuit 66, and an output coupled to external railway apparatus.

14. The invention as defined by claim 13 and additionally including: first differentiator means 75 and first diode means D3 coupled together between the output of said second AND logic circuit 68 and said one input terminal R of said first and second flip-flop circuit 78 and 80; second differentiator means 77 and second diode means D1 coupled together between the output of said second OR circuit 72 and another input S of said first flip-flop circuit 78; and third differentiator means 79 and third diode means D2 coupled together between the output of said first OR circuit 60 and another input S of said second flip-flop circuit 80.