US3657805A - Method of housing semiconductors - Google Patents

Method of housing semiconductors Download PDF

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Publication number
US3657805A
US3657805A US67A US6770A US3657805A US 3657805 A US3657805 A US 3657805A US 67 A US67 A US 67A US 6770 A US6770 A US 6770A US 3657805 A US3657805 A US 3657805A
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Prior art keywords
collar
lid
slice
mounting
boat
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US67A
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Clair Allen Johnson
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to US00188445A priority patent/US3753054A/en
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Publication of US3657805A publication Critical patent/US3657805A/en
Priority to CA209,982A priority patent/CA984114A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01006—Carbon [C]
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    • H01L2924/01074—Tungsten [W]
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Definitions

  • ABSTRACT In a method of housing semiconductors, a sealing collar formed from a nickel-cobalt-iron alloy is mounted on a ceramic boat. An LSl slice is then mounted on the boat within the collar. Finally, a lid formed from the material of the collar is welded to the distal end of the collar. In a second embodiment of the method, the boat is formed from a ceramic ring, a nickel-cobalt-iron alloy plate and a molybdenum plate. In a third embodiment, an LSl slice and at least one conventional integrated circuit are mounted on the boat within the collar.
  • FIG. I4 CLAIR ALLEN JOHNSON ATTORNEY METHOD OF HOUSING SEMICONDUCTORS
  • integrated circuits have comprised discrete units. Typically, a plurality of identical integrated circuits are fabricated simultaneously in the form of a relatively large slice. During the latter stages of such an operation, the individual integrated circuits of the slice are separated from each other and are thereafter individually mounted in suitable housings.
  • LSI large scale integration
  • the various components of the slice are not separated from one another.
  • a housing for the entire LSI slice.
  • Such a housing must satisfy at least two requirements. First, it must form a hermetic seal around the slice. Second, it must permit access to the slice so that the system on the slice can be repaired, if necessary.
  • This invention relates to a method of housing semiconductors that meets both of these requirements.
  • a semiconductor device is mounted on a device receiving member within a sealing member and a lid is joined to the sealing member. If access to the device is required, the joint between the lid and the sealing member is removed.
  • FIG. 1 is an illustration of an initial step in the first embodiment of a method of housing semiconductors employing the invention
  • FIG. 2 is an illustration of a second embodiment of the method
  • FIG. 3 is a prespective view of a carrier assembly useful in the practice of the invention.
  • FIG. 4 is an enlarged prespective view similar to FIG. 3 in which certain parts have been broken away;
  • FIGS. 5, 6, and 7 are illustrations of intermediate steps in the first embodiment of the method
  • FIGS. 8, 9, 10, 11 and 12 are illustrations of modified versions of the step shown in FIG. 7;
  • FIG. 13 is an illustration of a third embodiment of the method.
  • FIG. 14 is the sectional view taken generally along the line 14-14 in FIG. 13.
  • an LSI slice receiving member includes a boat 12 formed from a high aluminum ceramic or a beryllia ceramic.
  • the boat 12 includes a central slice receiving cavity 14, an inner lip 16 that extends around the cavity 14 and an outer lip 18 that extends around the outer periphery of the boat.
  • a sealing rim 20 extends around the cavity 14 of the boat 12 between the inner lip 16 and the outer lip 18.
  • the boat 12 has outside dimensions of 214 X 2% X inch and is preferably formed from separate pieces that are fused into an unitary structure. Prior to the fusing operation, a plurality of electrically conductive connector strips 22 are formed on one of the pieces. In the finished boat 12, the strips 22 extend from the upper surface of the inner lip 16 under the rim 20 to the upper surface of the outer lip 18.
  • the LSI receiving member 10 further includes a sealing collar 24 that extends around the slice receiving cavity 14 of the boat 12.
  • the collar 24 is attached to the upper surface of the sealing rim 20 of the boat 12 by a malleable braze joint 26 and is preferably formed from a material having thermal expansion characteristics that match those of the material of the boat 12.
  • the collar 24 may be formed from an alloy containing 29 percent nickel, 17 percent cobalt and 54 percent iron. Such a material is sold under the trademark l(OVAR".
  • the collar 24 may be formed from a malleable material, such as copper, or the like.
  • the connector strips 22 are interconnected by a conductive strip that extends along the outer edge of the outer lip 18 of the boat 12.
  • a brazing material is simultaneously electro-plated to at least the outer portions of all of the strips 22 of the boat 12.
  • the connector strips 22 are electrically disconnected from one to another, preferably by forming a beveled surface 28 along the outer edge of the outer lip 18 of the boat 12 and thereby removing the conductive strip extending between the connector strips 22.
  • the lead frame 30 includes a plurality of individual leads or pins 32 that are electrically interconnected at their distal ends. Each lead 32 is connected to one of the connector strips 22 of the boat 12 by positioning the lead 32 in engagement with its respective strip 22 and thereafter melting the brazing material on the strip 22. When all of the pins 32 are attached to the strips 22, the electrical interconnections between the pins 32 are employed to simultaneously electroplate successive layers of nickel and gold over the exposed portions of all of the pins 32 and all of the strips 22.
  • the LSI slice receiving member 10 is mounted in a carrier assembly 34 at the conclusion of the electro-plating operation.
  • the carrier assembly 34 includes an upper member 36 and a lower member 38.
  • a plurality of teeth 40 extend downwardly from the upper member 36 and are positioned along inner and outer rows.
  • the lower member 38 is positioned between the rows of teeth 40 and is clamped to the upper member 36 by a plurality of socket head screws 42 each having an upwardly extending projection 44.
  • each pin or lead 32 of the member 10 is clamped between the upper and lower members 36 and 38 of the assembly 34 and is positioned between two pairs of the teeth 40 of the upper member 36.
  • LSI slice receiving member 10 After the LSI slice receiving member 10 is positioned in the carrier assembly 34, the interconnections between the distal ends of the leads 32 of the lead frames 30 are removed. It is best shown in FIG. 5, a LSI slice 46 is then positioned in the slice receiving cavity 14 of the boat 12 and is secured to the boat 12 by adhesive means 48 such as solder, epoxy, etc. Thereafter, the connector strips 22 of the LSI slice receiving member 10 are connected to terminals on the LSI slice 46 by individual gold wires 50. Preferably, the wires 50 are connected to the strips 22 and to the terminals of the slice 46 by one of the commonly employed chisel bonding or ball bonding techniques.
  • the LSI slice receiving member 10 is subjected to a vacuum test to determine whether any leaks exist either in the structure of the boat 12 or in the malleable braze joint 26. Also, as is best shown in FIG. 6, the LSI slice receiving member 10 is positioned in a test fixture 52, whereupon various electrical tests are performed on the slice 46.
  • the test fixture 52 includes a body 54 having a cavity 56 formed in it which receives the lower member 38 of the carrier assembly 34.
  • a plurality of conductive pins 58 are mounted in the body 54 for engagement with the leads 32.
  • the pins 58 are connected to the output of a computer controlled LSI slice testing apparatus (not shown) and serve to form electrical connections between the testing apparatus and the LS1 slice 46.
  • the test fixture further includes a heat sink (not shown) which engages the lower surface of the boat 12 of the LSI slice receiving member 10 and serves to remove heat from the slice 46.
  • the sealing step is illustrated in FIG. 7 and comprises positioning a sealing lid 60 over the slice receiving cavity 14 of the member 10 and thereafter forming a weld 62 between the outer edge of the lid 60 and the outer edge of the collar 24.
  • the lid 60 has outside dimensions that are substantially equal to the inside dimensions of the collar 24 and is preferably formed from the same material as the collar 24.
  • the weld 62 is preferably formed by employing a plasma arc welder to melt the outer edges of the collar 24 and the lid 60.
  • a welding rod may be employed to form the weld 62.
  • the weld 62 can also be formed by directing a welding current between a pair of rollers mounted in engagement with the collar 24 and the lid 60, respectively.
  • the weld 62 need not be a true weld and can be brazed joint, etc.
  • the slice receiving cavity can be filled with an inert gas before the lid 60 is attached to the collar 24.
  • the slice receiving member 10 can be filled with a pressurized gas such as helium. The latter procedure is helpful in testing the assembly for leaks.
  • FIGS. 8 through 12 Various modified versions of the sealing step shown in FIG. 7 are illustrated in FIGS. 8 through 12.
  • the version shown in FIG. 8 differs from the version shown in FIG. 7 in that a sealing collar 24a having an L-shaped cross section is employed.
  • the version shown in FIG. 9 differs from the version shown in FIG. 8 in that a band of brazing material 64 is positioned between a collar 24b and the lid 60.
  • a weld formed by surrounding the collar 24b with an induction heating coil and thereafter operating the coil to melt the band 64.
  • the versions of the sealing step shown in FIGS. 10, 11, 12 differ from the versions shown in FIGS. 7, 8, and 9 in that a flat lid 60a is employed.
  • the lid 60a is joined to an outwardly extending flange 66 formed on the distal end of a collar.
  • the lower portion of a collar 240 is shaped similarly to the lower portion of the collar 24a shown in FIG. 8
  • the version shown in FIG. 11 the lower portion of a collar 24d is shaped similarly to the lower portion of the collar 24 shown in FIG. 7.
  • the version shown in FIG. 12 differs from the version shown in FIG. 10 principally in that a ring of ceramic material 68 is positioned between a collar 24e and a lid 60a to provide additional strength.
  • the finished LSI assembly has the general appearance of the LSI slice receiving member 10 shown in FIG. 3.
  • the slice receiving cavity 14 of the member 10 is covered by a lid 60 and the interconnecting portions of the lead frames 30 are removed.
  • the finished LSI assembly is subjected to a variety of tests including mechanical and thermal shock tests, bake out and thermal cycling tests, centrifuge tests, etc. Finally, the LSI assembly is put into use. During the testing and the use of the LSI assembly, the carrier assembly remains attached to the leads extending from the boat. The carrier assembly protects the assembly and may be provided with identification means, if desired.
  • the slice receiving member forms a hermetically sealed housing around the LSI slice. Because the collar and the lid of the slice receiving member are formed from a material having a coefficient of thermal expansion matched to that of the slice receiving boat and because the collar and the boat are interconnected by a malleable joint, the housing withstands wide variations in temperature without developing leaks. If access to the slice is ever required, the housing can be opened by simply sanding away the weld between the collar and the lid.
  • FIG. 2 a second embodiment of the method of housing semiconductors employing the invention is shown.
  • the second embodiment is identical to the first embodiment except that the boat 12' of the second embodiment is comprised of three parts including a ring 70, a plate 72 and a plate 74.
  • the boat 12 is fabricated by brazing the ring 70, the plate 72 and the plate 74 to one another.
  • the ring 70 is formed from a ceramic material.
  • the plate 72 is formed from a material having thermal expansion characteristics similar to those of the ceramic material, for example, a nickel-cobaltiron alloy may be employed.
  • the plate 72 is formed from a material having thermal expansion characteristics that match those of the material of an LSI slice, for example, tungsten or molybdenum.
  • FIGS. 13 and 14 A third embodiment of the method of housing semiconductors is illustrated in FIGS. 13 and 14.
  • the third embodiment is virtually identical to the first embodiment in so far as the steps illustrated in FIGS. 1 and 3 through 12 are concerned.
  • One difference between the third embodiment and the first embodiment is that the rim 20", the collar 24" and the lid 60" of the third embodiment are square rather than round.
  • a very important difference between the third embodiment and the first embodiment is that a cavity 76 is formed in the boat 12" of the LSI slice receiving member 10'' between the slice receiving cavity 14" and the rim 20".
  • a conventional integrated circuit 78 is positioned in the cavity 76 and is connected to certain terminals on the LSI slice 46" and to certain of the connector strips 22" by a plurality of gold wires 80.
  • the integrated circuit 76 is employed in the third embodiment to perform a function that cannot be performed by the various components of the LSI slice 46". Therefore, the third embodiment of the method results in an LSI as sembly that is virtually identical to the assembly resulting from the use of the first embodiment in so far as outward appearance is concerned, but which has greater utility in that it can perform at least one additional function.
  • the lid is joined to the collar by a weld. This is advantageous because it permits the use of multiple passes to assure the formation of a seal, if necessary. Also, a weld is easily removed to permit access to the slice.
  • the weld is formed along a line positioned a considerable distance from the slice. In and of itself, this protects the slice form damage due to heat. Also, the location of the weld permits the positioning of heat sink members between the outer edge of the collar and the slice while the weld is being formed.
  • the carrier assembly protects and maintains the alignment of the leads of the assembly.
  • the carrier assembly also positions both the LS1 slice and the leads of the slice receiving member relative to test fixtures. By means of the projections of the socket head screws, the carrier assembly permits the stacking of LSI assemblies during shipping, storage, etc.
  • each carrier assembly can be suitably tagged, whereupon an automatic system can be employed to store and dispense LSI assemblies.
  • a method of housing semiconductors comprising: a. forming a semiconductor slice receiving member by attaching a first plate having a first coefficient of thermal expansion to a second plate having a second coefficient of thermal expansion and then mounting the second plate in the center of an annular body having a coefficient of thermal expansion similar to that of the second plate; attaching a collar to said receiving member; 0. positioning a semiconductor device, having substantially said first coefiicient of thermal expansion, and further having a front surface for electrical connections thereto, a back surface for mounting on said first plate with said back surface contiguous with said first plate; and d. thereafter attaching a lid to a portion of the collar remote from the slice receiving member for completely enclosing said semiconductor slice.
  • the positioning step comprises attaching said back surface to said first plate within the annular body, thereby rendering access to said front surface prior to said attaching of lid.
  • a method of housing semiconductors comprising: a. forming a semiconductor slice receiving member by l. attaching a first plate having a first coefficient of thermal expansion to a second plate having a second coefficient of thermal expansion; and
  • a method of housing semiconductors including the steps of:
  • the method of housing semiconductors according to claim 10 including the additional step mounting the boat in a carrier that engages and positions each of the leads.

Abstract

In a method of housing semiconductors, a sealing collar formed from a nickel-cobalt-iron alloy is mounted on a ceramic boat. An LSI slice is then mounted on the boat within the collar. Finally, a lid formed from the material of the collar is welded to the distal end of the collar. In a second embodiment of the method, the boat is formed from a ceramic ring, a nickel-cobalt-iron alloy plate and a molybdenum plate. In a third embodiment, an LSI slice and at least one conventional integrated circuit are mounted on the boat within the collar.

Description

United States Patent Johnson [451 Apr.25, 1972 [54] METHOD OF HOUSING SEMICONDUCTORS [72] Inventor: Clair Allen Johnson, Sherman, Tex.
[73] Assignee: Texas Instruments Incorporated, Dallas,
Tex.
[22] Filed: Jan. 2, 1970 [21] Appl.No.: 67
[52] U.S.Cl ..29/589, 317/234 G, 3l7/234H [51] Int. Cl. ..BOlj 17/00 [58] Field ofSearch ..29/576,577,'588,589;
[56] References Cited UNlTED STATES PATENTS 7/1965 Wegner et a1 ..29/589 X 1/1969 Dix et a1 ..29/588 X 3,502,786 3/l970 Stoll ..29/588 X Primary Examiner.l0hn F. Campbell Assistant ExaminerCarl E. Hall A!t0rney.lames 0. Dixon, Andrew M. Hassell, Harold Levine, Melvin Sharp, John E. Vandigriff, Henry T. Olsen and Michael A. Sileo, Jr.
[57] ABSTRACT In a method of housing semiconductors, a sealing collar formed from a nickel-cobalt-iron alloy is mounted on a ceramic boat. An LSl slice is then mounted on the boat within the collar. Finally, a lid formed from the material of the collar is welded to the distal end of the collar. In a second embodiment of the method, the boat is formed from a ceramic ring, a nickel-cobalt-iron alloy plate and a molybdenum plate. In a third embodiment, an LSl slice and at least one conventional integrated circuit are mounted on the boat within the collar.
12 Claims, 14 Drawing Figures FATE TEM E 25 I972 SHEET 2 OF 4 INVENTOR F I G. 4 CLAIR ALLEN JOHNSON ATTORNEY PI'JEHTEP- F 2 1972 3, 657, 805
SHEET 30F 4 36 22 M, f", Z
w MA FIG. IO
INVENTOR CLAIR ALLEN JOHNSON PATENTEDAPR 25 I972 8 657, 805
sum u BF 4 F I G. I3
44 (24" 34" 36 I] fljf 20" 1% 7 5 INVENTOR FIG. I4 CLAIR ALLEN JOHNSON ATTORNEY METHOD OF HOUSING SEMICONDUCTORS In the past, integrated circuits have comprised discrete units. Typically, a plurality of identical integrated circuits are fabricated simultaneously in the form of a relatively large slice. During the latter stages of such an operation, the individual integrated circuits of the slice are separated from each other and are thereafter individually mounted in suitable housings.
More recently, the concept of large scale integration (LSI) has been proposed. In accordance with the LSI concept, many of the various integrated circuits and other components comprising an electronic system are formed on a single slice. Preferably, extra or spare components are also provided so that in the event one of the components of the system is or becomes defective, a similar component can be substituted.
In the use of the LSI system, the various components of the slice are not separated from one another. Thus, it is necessary to provide a housing for the entire LSI slice. Such a housing must satisfy at least two requirements. First, it must form a hermetic seal around the slice. Second, it must permit access to the slice so that the system on the slice can be repaired, if necessary.
This invention relates to a method of housing semiconductors that meets both of these requirements. In accordance with the preferred embodiment of the invention, a semiconductor device is mounted on a device receiving member within a sealing member and a lid is joined to the sealing member. If access to the device is required, the joint between the lid and the sealing member is removed.
A more complete understanding of the invention may be had by referring to the following detailed description when taken in conjunction with the drawings, wherein:
FIG. 1 is an illustration of an initial step in the first embodiment of a method of housing semiconductors employing the invention;
FIG. 2 is an illustration of a second embodiment of the method;
FIG. 3 is a prespective view of a carrier assembly useful in the practice of the invention;
FIG. 4 is an enlarged prespective view similar to FIG. 3 in which certain parts have been broken away;
FIGS. 5, 6, and 7 are illustrations of intermediate steps in the first embodiment of the method;
FIGS. 8, 9, 10, 11 and 12 are illustrations of modified versions of the step shown in FIG. 7;
FIG. 13 is an illustration of a third embodiment of the method, and
FIG. 14 is the sectional view taken generally along the line 14-14 in FIG. 13.
Referring now to FIG. 1, an initial step in a first embodiment of a method of housing semiconductors employing the invention is shown. In accordance with the first embodiment, an LSI slice receiving member includes a boat 12 formed from a high aluminum ceramic or a beryllia ceramic. The boat 12 includes a central slice receiving cavity 14, an inner lip 16 that extends around the cavity 14 and an outer lip 18 that extends around the outer periphery of the boat. A sealing rim 20 extends around the cavity 14 of the boat 12 between the inner lip 16 and the outer lip 18.
The boat 12 has outside dimensions of 214 X 2% X inch and is preferably formed from separate pieces that are fused into an unitary structure. Prior to the fusing operation, a plurality of electrically conductive connector strips 22 are formed on one of the pieces. In the finished boat 12, the strips 22 extend from the upper surface of the inner lip 16 under the rim 20 to the upper surface of the outer lip 18.
The LSI receiving member 10 further includes a sealing collar 24 that extends around the slice receiving cavity 14 of the boat 12. The collar 24 is attached to the upper surface of the sealing rim 20 of the boat 12 by a malleable braze joint 26 and is preferably formed from a material having thermal expansion characteristics that match those of the material of the boat 12. For example, the collar 24 may be formed from an alloy containing 29 percent nickel, 17 percent cobalt and 54 percent iron. Such a material is sold under the trademark l(OVAR". Alternatively, the collar 24 may be formed from a malleable material, such as copper, or the like.
During the fabrication of the ceramic boat 12 of the LSI slice receiving member 10, the connector strips 22 are interconnected by a conductive strip that extends along the outer edge of the outer lip 18 of the boat 12. By means of such a strip, a brazing material is simultaneously electro-plated to at least the outer portions of all of the strips 22 of the boat 12. Thereafter, the connector strips 22 are electrically disconnected from one to another, preferably by forming a beveled surface 28 along the outer edge of the outer lip 18 of the boat 12 and thereby removing the conductive strip extending between the connector strips 22.
After the strips 22 have been electrically disconnected at least one lead frame 30 is attached to the LSI slice receiving member 10. The lead frame 30 includes a plurality of individual leads or pins 32 that are electrically interconnected at their distal ends. Each lead 32 is connected to one of the connector strips 22 of the boat 12 by positioning the lead 32 in engagement with its respective strip 22 and thereafter melting the brazing material on the strip 22. When all of the pins 32 are attached to the strips 22, the electrical interconnections between the pins 32 are employed to simultaneously electroplate successive layers of nickel and gold over the exposed portions of all of the pins 32 and all of the strips 22.
Referring now to FIG. 3, the LSI slice receiving member 10 is mounted in a carrier assembly 34 at the conclusion of the electro-plating operation. As is best shown in FIG. 4, the carrier assembly 34 includes an upper member 36 and a lower member 38. A plurality of teeth 40 extend downwardly from the upper member 36 and are positioned along inner and outer rows. The lower member 38 is positioned between the rows of teeth 40 and is clamped to the upper member 36 by a plurality of socket head screws 42 each having an upwardly extending projection 44. Thus, when the LS1 slice receiving member 10 is in the carrier assembly 34, each pin or lead 32 of the member 10 is clamped between the upper and lower members 36 and 38 of the assembly 34 and is positioned between two pairs of the teeth 40 of the upper member 36.
After the LSI slice receiving member 10 is positioned in the carrier assembly 34, the interconnections between the distal ends of the leads 32 of the lead frames 30 are removed. It is best shown in FIG. 5, a LSI slice 46 is then positioned in the slice receiving cavity 14 of the boat 12 and is secured to the boat 12 by adhesive means 48 such as solder, epoxy, etc. Thereafter, the connector strips 22 of the LSI slice receiving member 10 are connected to terminals on the LSI slice 46 by individual gold wires 50. Preferably, the wires 50 are connected to the strips 22 and to the terminals of the slice 46 by one of the commonly employed chisel bonding or ball bonding techniques.
When the connector strips 22 of the boat 12 have been connected to their respective terminals on the slice 46, various tests are performed. For example, the LSI slice receiving member 10 is subjected to a vacuum test to determine whether any leaks exist either in the structure of the boat 12 or in the malleable braze joint 26. Also, as is best shown in FIG. 6, the LSI slice receiving member 10 is positioned in a test fixture 52, whereupon various electrical tests are performed on the slice 46.
The test fixture 52 includes a body 54 having a cavity 56 formed in it which receives the lower member 38 of the carrier assembly 34. A plurality of conductive pins 58 are mounted in the body 54 for engagement with the leads 32. The pins 58 are connected to the output of a computer controlled LSI slice testing apparatus (not shown) and serve to form electrical connections between the testing apparatus and the LS1 slice 46. The test fixture further includes a heat sink (not shown) which engages the lower surface of the boat 12 of the LSI slice receiving member 10 and serves to remove heat from the slice 46.
At the conclusion of the various testing operations, the LSI slice receiving member is sealed. The sealing step is illustrated in FIG. 7 and comprises positioning a sealing lid 60 over the slice receiving cavity 14 of the member 10 and thereafter forming a weld 62 between the outer edge of the lid 60 and the outer edge of the collar 24. The lid 60 has outside dimensions that are substantially equal to the inside dimensions of the collar 24 and is preferably formed from the same material as the collar 24.
The weld 62 is preferably formed by employing a plasma arc welder to melt the outer edges of the collar 24 and the lid 60. Alternatively, a welding rod may be employed to form the weld 62. The weld 62 can also be formed by directing a welding current between a pair of rollers mounted in engagement with the collar 24 and the lid 60, respectively. Finally, the weld 62 need not be a true weld and can be brazed joint, etc.
During the sealing step, a dry atmosphere is maintained around the slice 46. Alternatively, the slice receiving cavity can be filled with an inert gas before the lid 60 is attached to the collar 24. Finally, the slice receiving member 10 can be filled with a pressurized gas such as helium. The latter procedure is helpful in testing the assembly for leaks.
Various modified versions of the sealing step shown in FIG. 7 are illustrated in FIGS. 8 through 12. The version shown in FIG. 8 differs from the version shown in FIG. 7 in that a sealing collar 24a having an L-shaped cross section is employed. The version shown in FIG. 9 differs from the version shown in FIG. 8 in that a band of brazing material 64 is positioned between a collar 24b and the lid 60. In the use of the version shown in FIG. 9, a weld formed by surrounding the collar 24b with an induction heating coil and thereafter operating the coil to melt the band 64.
The versions of the sealing step shown in FIGS. 10, 11, 12 differ from the versions shown in FIGS. 7, 8, and 9 in that a flat lid 60a is employed. In each case, the lid 60a is joined to an outwardly extending flange 66 formed on the distal end of a collar. In the version shown in FIG. 10, the lower portion of a collar 240 is shaped similarly to the lower portion of the collar 24a shown in FIG. 8, whereas the version shown in FIG. 11, the lower portion of a collar 24d is shaped similarly to the lower portion of the collar 24 shown in FIG. 7. The version shown in FIG. 12 differs from the version shown in FIG. 10 principally in that a ring of ceramic material 68 is positioned between a collar 24e and a lid 60a to provide additional strength.
At the conclusion of the sealing step, the method of housing semiconductors according to the present invention is complete. The finished LSI assembly has the general appearance of the LSI slice receiving member 10 shown in FIG. 3. Of course, the slice receiving cavity 14 of the member 10 is covered by a lid 60 and the interconnecting portions of the lead frames 30 are removed.
The finished LSI assembly is subjected to a variety of tests including mechanical and thermal shock tests, bake out and thermal cycling tests, centrifuge tests, etc. Finally, the LSI assembly is put into use. During the testing and the use of the LSI assembly, the carrier assembly remains attached to the leads extending from the boat. The carrier assembly protects the assembly and may be provided with identification means, if desired.
In the finished LSI assembly, the slice receiving member forms a hermetically sealed housing around the LSI slice. Because the collar and the lid of the slice receiving member are formed from a material having a coefficient of thermal expansion matched to that of the slice receiving boat and because the collar and the boat are interconnected by a malleable joint, the housing withstands wide variations in temperature without developing leaks. If access to the slice is ever required, the housing can be opened by simply sanding away the weld between the collar and the lid.
Referring now to FIG. 2, a second embodiment of the method of housing semiconductors employing the invention is shown. The second embodiment is identical to the first embodiment except that the boat 12' of the second embodiment is comprised of three parts including a ring 70, a plate 72 and a plate 74. Preferably, the boat 12 is fabricated by brazing the ring 70, the plate 72 and the plate 74 to one another.
In accordance with the second embodiment, the ring 70 is formed from a ceramic material. The plate 72 is formed from a material having thermal expansion characteristics similar to those of the ceramic material, for example, a nickel-cobaltiron alloy may be employed. On the other hand, the plate 72 is formed from a material having thermal expansion characteristics that match those of the material of an LSI slice, for example, tungsten or molybdenum.
When the boat 12 is so constructed, thermal stresses imposed between the LSI slice and the plate 74 during the operation of the slice are minimized. Likewise, thermal stresses are minimized between the plate 72 and the ring 70. Since the thermal expansion characteristics of the plate 74 and the plate 72 are not matched, stresses are imposed between the components. However, since neither the plate 72 nor the plate 74 is an active component, and since the plates 72 and 74 are brazed together, such stresses produce substantially no deleterious effects.
A third embodiment of the method of housing semiconductors is illustrated in FIGS. 13 and 14. The third embodiment is virtually identical to the first embodiment in so far as the steps illustrated in FIGS. 1 and 3 through 12 are concerned. One difference between the third embodiment and the first embodiment is that the rim 20", the collar 24" and the lid 60" of the third embodiment are square rather than round.
A very important difference between the third embodiment and the first embodiment is that a cavity 76 is formed in the boat 12" of the LSI slice receiving member 10'' between the slice receiving cavity 14" and the rim 20". A conventional integrated circuit 78 is positioned in the cavity 76 and is connected to certain terminals on the LSI slice 46" and to certain of the connector strips 22" by a plurality of gold wires 80. Typically, the integrated circuit 76 is employed in the third embodiment to perform a function that cannot be performed by the various components of the LSI slice 46". Therefore, the third embodiment of the method results in an LSI as sembly that is virtually identical to the assembly resulting from the use of the first embodiment in so far as outward appearance is concerned, but which has greater utility in that it can perform at least one additional function.
The use of the method of housing semiconductors that is shown in the drawings and described herein results in several advantages over other housing methods. For example, in the practice of the various versions of the sealing step shown in FIGS. 7 through 12, the lid is joined to the collar by a weld. This is advantageous because it permits the use of multiple passes to assure the formation of a seal, if necessary. Also, a weld is easily removed to permit access to the slice.
It should be noted that in each case, the weld is formed along a line positioned a considerable distance from the slice. In and of itself, this protects the slice form damage due to heat. Also, the location of the weld permits the positioning of heat sink members between the outer edge of the collar and the slice while the weld is being formed.
The mounting of the slice receiving member in the carrier assembly also results in several advantages. For example, the carrier assembly protects and maintains the alignment of the leads of the assembly. The carrier assembly also positions both the LS1 slice and the leads of the slice receiving member relative to test fixtures. By means of the projections of the socket head screws, the carrier assembly permits the stacking of LSI assemblies during shipping, storage, etc. Finally, each carrier assembly can be suitably tagged, whereupon an automatic system can be employed to store and dispense LSI assemblies.
Although various embodiments of the invention are illustrated in the drawings and described herein, it will be understood that the invention is not limited to the embodiments disclosed but is capable of rearrangement, modification and substitution of parts and elements without departing from the spirit of the invention.
What is claimed is: l. A method of housing semiconductors comprising: a. forming a semiconductor slice receiving member by attaching a first plate having a first coefficient of thermal expansion to a second plate having a second coefficient of thermal expansion and then mounting the second plate in the center of an annular body having a coefficient of thermal expansion similar to that of the second plate; attaching a collar to said receiving member; 0. positioning a semiconductor device, having substantially said first coefiicient of thermal expansion, and further having a front surface for electrical connections thereto, a back surface for mounting on said first plate with said back surface contiguous with said first plate; and d. thereafter attaching a lid to a portion of the collar remote from the slice receiving member for completely enclosing said semiconductor slice. 2. A method of housing semiconductors according to claim 1 wherein the positioning step comprises attaching said back surface to said first plate within the annular body, thereby rendering access to said front surface prior to said attaching of lid.
3. A method of housing semiconductors comprising: a. forming a semiconductor slice receiving member by l. attaching a first plate having a first coefficient of thermal expansion to a second plate having a second coefficient of thermal expansion; and
2. mounting the second plate in the center of an annular body having a coefficient of thermal expansion substantially similar to that of said second plate;
b. attaching a collar to said annular body of said slice receiving; member;
c. positioning a semiconductor slice having a coefficient of thermal expansion similar to that of said first plate on said slice receiving member and mounting said semiconductor slice within said collar on said first plate; and thereafter d. attaching a lid to a portion of said collar remote from said slice receiving member.
4. The method of housing semiconductors according to claim 1 wherein the collar extends away from the slice receiving member and is attached to the slice receiving member by a malleable braze joint.
5. The method of housing semiconductors according to claim 4 wherein the lid is formed from the same material as the collar and wherein the lid attaching step is carried out by welding the lid to the collar.
6. The method of housing semiconductors according to claim 5 wherein the lid attaching step is characterized by attaching an edge of the lid to an edge of the collar.
7. A method of housing semiconductors including the steps of:
a. providing a semiconductor slice receiving boat including a substrate having a cavity for receiving a semiconductor slice, a sealing rim extending around the cavity on said substrate, and a plurality of conductive strips between said substrate and said rim;
b. forming a sealing collar having the same periphery as that of the sealing rim and having a pair of end portions;
c. mounting the sealing collar on the receiving member with one end portion of the sealing collar in engagement with the sealing rim;
d. mounting a semiconductor slice in the slice receiving cavity of the boat;
e. providing a lid including an edge portion having the same periphery as the other end portion of the sealing collar, and
f. mounting the lid on the sealing collar with the edge portion of the lid in engagement with the other end portion of the collar.
8. The method of housing semiconductors according to claim 7 wherein the steps of forming a sealing collar and forming a lid are characterized by forming said collar and said lid from a material having a coefficient of thermal expansion similar to that of the material of the boat.
9. The method of housing semiconductors according to claim 7 wherein the step of mounting the lid is carried out by welding the edge portion of the lid to the other end portion of the collar.
10. The method of housing semiconductors according to claim 7 wherein the boat forming step includes the additional step of attaching a conductive lead to each of said conductive strips.
11. The method of housing semiconductors according to claim 10 including the additional step mounting the boat in a carrier that engages and positions each of the leads.
12. The method of mounting semiconductors according to claim 7 wherein the slice mounting step is further characterized by mounting at least one integrated circuit in the cavity between the LS1 slice and the collar.

Claims (12)

  1. 2. mounting the second plate in the center of an annular body having a coefficient of thermal expansion substantially similar to that of said second plate; b. attaching a collar to said annular body of said slice receiving; member; c. positioning a semiconductor Slice having a coefficient of thermal expansion similar to that of said first plate on said slice receiving member and mounting said semiconductor slice within said collar on said first plate; and thereafter d. attaching a lid to a portion of said collar remote from said slice receiving member.
  2. 2. A method of housing semiconductors according to claim 1 wherein the positioning step comprises attaching said back surface to said first plate within the annular body, thereby rendering access to said front surface prior to said attaching of lid.
  3. 3. A method of housing semiconductors comprising: a. forming a semiconductor slice receiving member by
  4. 4. The method of housing semiconductors according to claim 1 wherein the collar extends away from the slice receiving member and is attached to the slice receiving member by a malleable braze joint.
  5. 5. The method of housing semiconductors according to claim 4 wherein the lid is formed from the same material as the collar and wherein the lid attaching step is carried out by welding the lid to the collar.
  6. 6. The method of housing semiconductors according to claim 5 wherein the lid attaching step is characterized by attaching an edge of the lid to an edge of the collar.
  7. 7. A method of housing semiconductors including the steps of: a. providing a semiconductor slice receiving boat including a substrate having a cavity for receiving a semiconductor slice, a sealing rim extending around the cavity on said substrate, and a plurality of conductive strips between said substrate and said rim; b. forming a sealing collar having the same periphery as that of the sealing rim and having a pair of end portions; c. mounting the sealing collar on the receiving member with one end portion of the sealing collar in engagement with the sealing rim; d. mounting a semiconductor slice in the slice receiving cavity of the boat; e. providing a lid including an edge portion having the same periphery as the other end portion of the sealing collar, and f. mounting the lid on the sealing collar with the edge portion of the lid in engagement with the other end portion of the collar.
  8. 8. The method of housing semiconductors according to claim 7 wherein the steps of forming a sealing collar and forming a lid are characterized by forming said collar and said lid from a material having a coefficient of thermal expansion similar to that of the material of the boat.
  9. 9. The method of housing semiconductors according to claim 7 wherein the step of mounting the lid is carried out by welding the edge portion of the lid to the other end portion of the collar.
  10. 10. The method of housing semiconductors according to claim 7 wherein the boat forming step includes the additional step of attaching a conductive lead to each of said conductive strips.
  11. 11. The method of housing semiconductors according to claim 10 including the additional step mounting the boat in a carrier that engages and positions each of the leads.
  12. 12. The method of mounting semiconductors according to claim 7 wherein the slice mounting step is further characterized by mounting at least one integrated circuit in the cavity between the LSI slice and the collar.
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US00188445A US3753054A (en) 1970-01-02 1971-10-13 Hermetically sealed electronic package
CA209,982A CA984114A (en) 1970-01-02 1974-09-23 Synthetic plastics thermoforming machine

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US4914741A (en) * 1987-06-08 1990-04-03 Digital Equipment Corporation Tape automated bonding semiconductor package
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US3943557A (en) * 1974-02-19 1976-03-09 Plessey Incorporated Semiconductor package with integral hermeticity detector
US4920454A (en) * 1983-09-15 1990-04-24 Mosaic Systems, Inc. Wafer scale package system and header and method of manufacture thereof
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US4987475A (en) * 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
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US6888228B1 (en) 1998-04-02 2005-05-03 National Semiconductor Corporation Lead frame chip scale package
USRE39854E1 (en) 1998-04-02 2007-09-25 National Semiconductor Corporation Lead frame chip scale package
US20020048846A1 (en) * 1998-12-11 2002-04-25 Corisis David J. Die paddle clamping method for wire bond enhancement
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