US3596181A

US3596181A - Selective signalling system

Info

Publication number: US3596181A
Application number: US565624A
Authority: US
Inventors: Edward Camp Dowling; Earl Wilbert Eshenauer Jr; Robert Earl Jones; Michael Joseph Yaccino
Original assignee: AMP Inc
Current assignee: TE Connectivity Corp
Priority date: 1966-03-04
Filing date: 1966-07-15
Publication date: 1971-07-27
Anticipated expiration: 1988-07-27
Also published as: GB1119467A; DE1512840A1; ES337517A1; NL6702333A; SE347378B

Abstract

The disclosure relates to a central station having an encoder which is operable to selectively call any one of a plurality of individual remote stations by the transmission of a unique code which is comprised of a series of time intervals occupied by the presence or absence of a signal level. The encoder includes an input such as a keyboard to first develop the particular code to be transmitted in terms of a two-out-of-five bit position representation for each character of the transmitted message. The encoder also includes a register to temporarily store a combination of generated characters and then to automatically add tag and stop characters and translate the composite message into the previously mentioned signal mode for transmission. The encoder circuit transmits a given composite signal at an appropriate time relative to the availability of signalling channels. The code transmitted is of pulses or signals of long length relative to the typical pulse or signal length of noise. Each receiver station includes means for receiving the transmitted composite message, translating such into a code which may be serially decoded in a register decoder set up for serial comparison of each bit of such translated code. The decoder is operated to progressively and serially compare each bit of the translated code and advance a bit as long as each received code bit is correct with respect to the assigned station code. The decoder operates to destroy the advancing bit upon the receipt of an incorrect code bit. In the event of the proper code the decoder is made to produce an output in the form of some audible, visual indication or command function. The detector may include a number of parallel decoder paths for a receipt of a plurality of codes each representing a separate command function. The receivers for a given system may be made identical with variations in code assignment being provided by a novel code plug assembly.

Description

United States Patent Edward Camp bowling Harrisburg;

Earl Wilber Eshenauer, .lr., Steelton; Robert Earl Jones, Camp 11111; Michael .Iouph Yaocino, Mecltanicsburg, all 01, Pa.

[72] Inventors [21] Appl. No. 565,624

[22] Filed July 15, 1966 [4S] Patented July 27, 1971 [73] Assignee AMP Incorporated Harrisburg, Pa.

Continuation-impart of application Ser. No. 531,864, Mar. 4, 1966, now abandoned.

s41 SELECTIVE SIGNALLING SYSTEM 11 Claims, 31 Drawing Figs.

521 user 325/55,

178/l7C,340/168S s11 lnt.Cl noun/o0 50 FieldolSeareh ..32s/s5,s1;

340/l47,157,158,167,l68,174,168 SR, 334, 336, 337; 178/17, 17 A, 17.5

[56] References Cited UNITED STATES PATENTS 2,740,106 3/1956 Phelps 325/55 3,292,178 12/1966 Magnuski 325/55 3,335,406 8/1967 Clark 325/55 3,376,384 4/1968 Achramowicz. 178/175 3,396,239 8/1968 Yamauchi 178/175 3,056,116 9/1962 Crane 340/168C 3,175,191 3/1965 Cohn et a1. 325/55 3,384,873 5/1968 Sharma 325/55 Primary Examiner Robert L. Griffin Assistant Examiner-Albert .1. Mayer KEYBQARD aiii eaaieee Atromeys-Curtis, Morris and Safford, Marshall M.

l-lolcombe, William Hintze, William J. Keating, Frederick W. Raring, John R. Hopkins, Adrian J. La Rue and Jay L. Seitchik ABSTRACT: The disclosure relates to a central station having an encoder which is operable to selectively call any one of a plurality of individual remote stations by the transmission of a unique code which is comprised of a series of time intervals occupied by the presence or absence of a signal level. The encoder includes an input such as a keyboard to first develop the particular code to be transmitted in terms of a two-out-of-five bit position representation for each character of the transmitted message. The encoder also includes a register to temporarily store a combination of generated characters and then to automatically add tag and stop characters and translate the composite message into the previously mentioned signal mode for transmission. The encoder circuit transmits a given composite signal at an appropriate time relative to the availability of signalling channels. The code transmitted is of pulses or signals of long length relative to the typical pulse or signal length of noise. Each receiver station includes means for receiving the transmitted composite message, translating such into a code which may be serially decoded in a register decoder set up for serial comparison of each bit of such translated code. The decoder is operated to progressively and serially compare each bit of the translated code and advance a bit as long as each received code bit is correct with respect to the assigned station code. The decoder operates to destroy the advancing bit upon the receipt of an incorrect code bit. 1n the event of the proper code the decoder is made to produce an output in the form of some audible, visual indication or command function. The detector may include a number of parallel decoder paths for a receipt of a plurality of codes each representing a separate command function. The receivers for a given system may be made identical with variations in code assignment being provided by a novel code plug assembly.

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SHEET 5 UF 8 PULSE STRETCHER POWER SUPPLY REGULATED no 60m OUTPUT-1 wmume I6 an owl CORE OUTPUT ENCODER OUTPUT T0 TRANSLATOR based on radio, land line or optical transmission. Such uses inlo clude calling, paging, operating and checking equipment function.

With respect to radio communications, one of the most pressing problems facing the industry is that of availability of signalling frequencies. Even with careful supervision of those utilizing radio equipment and regulation of the equipment itself, the problem of bandwidth crowding and interference between signalling channels increases each year. This'means that a selective signalling system must be designed to operate in as narrow a bandwidth as possible, both with respect to its use in existing and standard frequency ranges and with respect to the few remaining unoccupied bandwidths. With respect to these applications the signalling mode employed in any selective signalling system must be such that it minimizes inter ference with other intelligence and the associated signal equipment must be such that the other communicated intelligence does not interfere with and falsely operate the signalling equipment. In applications over land lines the bandwidth problem is present to the same extent as with radio equipment and additionally there are problems relating to cross talk and amplifier distortion along the line. This means that selective signalling mode choices must be related to signal characteristics other than that of frequency, such as amplitude. The associated signalling equipment must also be chosen to optimize both signals-to-noise ratio and on-off ratio. In optical systems the equivalent of the foregoing problems are all present.

in all of these cases the choice of waveform should be such as to permit transmission and reception with minimum signal degradation and distortion and the equipment used must provide good discrimination between the received waveform and local noise or RFI.

An additional problem present with the imposition of a separate selective signalling system upon existing equipments is one of compatibility and power requirement. A large number of two-way radio communication .systems exist employed by taxicabs, police, fire and gas companies. Still other systems exist for use by military and civilian aircraft and for marine use. The typical automobile voltage available today is 12 volts DC and most existing mobile equipments operate from this supply. The typical supply aboard ships is some other voltage and usually some other frequency. For portable battery-operated equipment the supply may be at another voltage level. A selective signalling system for general use should be compatible with all of these systems in terms of required power supply or at least in terms of a relatively simple interface between such supplies ane. such existing equipment.

As still another consideration with respect to signalling the code utilized should be one which permits an easy implementation of checking procedures. Yet another consideration is one of adaptability for international use.

As will be appreciated, the foregoing sets forth a wide variety of applications wherein a selective signalling system might be expected to work with different types of communication transmitters and receivers. Some of these may be of considerable complexity and sophistication and some must of necessity be simple and inexpensive.

Accordingly, it is an object of the invention to provide a selective signalling system which utilizes a signalling code structure and signal waveform which reduces the required bandwidth occupied by the system signals. It is a further object to provide a selective signalling system which in its implementation is fully compatible, with both complex and simple radio equipment and with land line and optical transmission and reception equipment. It is a further object to provide a selective signalling system which can be used with a large number of transmitters or receivers of substantially identical construction, but with features enabling each transmitter or receiver to be easily preset to operate with a unique calling signal. In conjunction with this last mentioned object, the system of the invention also contemplates equipment operable with a code structure which can be readily expanded in terms of number of transmitter or receiver units. The code structure of the invention is such as to be acceptable with respect to any language or machine.

It is a final object of the invention to provide a selective signalling system including an encoder and one or more decoders of a construction which is reliable and of long life.

The foregoing objectives are attained through the present invention by the provision of a central station having an encoder which is operable to selectively call any one of a plurality of individual remote stations by the transmission of a unique code which is comprised of a series of time intervals occupied by the presence or absence of a signal level. This code is similar to the well-known mark-space coding technique employed in telegraphy. The encoder includes an input means such as a keyboard to first develop the particular code to be transmitted in terms of a two-out-of-five bit position representation for each character of the transmitted message. The env coder also includes a register to temporarily store a combination of generated characters and then to automatically add tag and stop characters and translate the composite message into the previously mentioned signal mode for transmission. The encoder circuit is made to transmit a given composite signal at an appropriate time relative to the availability of signalling channels. The code transmitted is in accordance with the invention made to be of pulses or signals of long length relative to the typical pulse or signal length of noise.

Each receiver station includes means for receiving the transmitted composite message, translating such into a code which may be serially decoded in a register decoder set up for serial comparison of each bit of such translated code. In accordance with the invention the decoder of use is operated to progressively and serially compare each bit of the translated code and advance a bit as long as each received code bit is correct with respect to the assigned station code. The decoder operates to destroy the advancing hit upon the receipt of an incorrect code bit. In the event of the proper code the decoder is made to produce an output in the form of some audible, visual indication or command function. Tln accordance with the invention, in one embodiment the detector may include a number of parallel decoder paths for a receipt of a plurality of codes each representing a separate command function. The invention receivers for a given system may be made identical with variations in code assignment being provided by a novel code plug assembly.

In the drawings:

FIG. 1 is a schematic diagram of the system of the lIlVIIllOIl in adaptations to various transmission media and in adaptations to various component arrangements;

FIGS. 2A-2C are schematic representations of general encoder embodiments;

FIGS. 3A-3C are schematic representations of general receiver embodiments;

FIG. 4A-4I is a time sequence plot showing the preferred signal waveform used by the invention;

FIGS. 5A and 5B are detailed schematics of a specific embodiment of the system encoder;

FIGS. 6 and 7 are schematics showing a preferred decoder wiring arrangement;

FIG. 8 is a partial representation of a magnetic core decoder preferred for use with the invention;

FIG. 9 is a time sequence plot of the set-clear states employed in the decoder circuit of FIGS. 6 and 8 to decode a FIG 13 is a detailed embodiment of a preferred decoder circuit; and

FIGS. l4A-E are representative of waveforms to aid in explaining the invention.

GENERAL DESCRIPTION Relative to the description to follow, the invention system is of the outboard type which embraces a single encoder and transmitter forming a command station and numerous receivers and decoders forming receiver stations. Outboard systems are typically used for paging. Also contemplated, but not here illustrated, are inboard systems wherein there are a large number of encoders and transmitters which each may generate and send a message identifying the transmitter location and indicating the presence of a condition, all received by a single master receiver. An example of an inboard system is that employed for city, tire and police call boxes.

Turning now to FIG. 1, there is shown an outboard selective signalling system including a variety of transmitter and receiver equipments general to the type of application contemplated for the present invention. There is included a master encoder capable of generating station calling or equipment function codes which are then transmitted by various means such as a radio transmitter, an optical transmitter or a land line transmitter. The master encoder may be operated by manual insertion of information in digital, decimal or binary form through dial or pushbutton devices or may be machinefed from tape, punch cards or other storage media. The encoded intelligence is then preferably translated into a type of on-ofi waveform, to be described hereinafter in detail, which is then transmitted directly or, in many instances, superimposed upon a suitable carrier compatible with the type of transmission contemplated. For example, with respect to the radio transmitter, the on-off waveform is superimposed upon a carrier in a selected AM or FM frequency band assigned to the particular type of communication. This may be done directly or by converting the on-ofi" waveform from a DC level or nonlevel into a single frequency tone or absence of tone or into two tones, one for on and one for off conditions. In the case of optical transmission this waveform is employed to modulate a transducer capable of biasing an optical source such as a laser, or like device, into on-off conditions to provide pulse modulation for that type of transmission. With respect to land line transmission, the calling code may, in certain instances, be sent directly as an on-off voltage level or, as is more frequently the case, sent as a distinct tone or tones in some frequency bandwidth so limited as not to interfere with voice communication. In closed circuit applications, such as in factories or as links between pumping stations on gas or oil lines, the calling signal may be superimposed upon existing communication lines or upon power lines by well-known techniques.

As will be developed more fully hereinafter, the code structure and associated equipment employed by the invention lends itself to use with a relatively large number of called stations or control functions. In FIG. 1, relative to radio transmission, a pair of receivers represent a large number of possible receiver stations. Each receiver will where necessary include equipment to demodulate the transmitted signal and/or detect the tone or tones used to represent the encoded on-off waveform. With each receiver station there is provided a decoder which has an output to some station call device such as an audible or visual indicator. Upon transmission of each calling signal each receiver associated with the system is actuated to attempt to respond. Only the receiver decoder set up for the particular code called does, however, respond to produce an output and an indication that the station is being called. All other stations in accordance with the invention do not respond.

The transmission of an optical calling signal is in a similar fashion received by a receiver and its decoder is operated to initiate a station call device. In the case of the optical receiver (and applicable to all of the various modes of transmission of FIG. 1) there is shown a pair of decoders, which decode the calling signal in parallel. One decoder has its output connected to initiate some control function. A representative application calling for this arrangement is one where the upper decoder operates from one calling code to signal the associated station that is being called for a normal or working purpose and the lower decoder is set up to receive a special code to initiate some alarm device to indicate the occurrence of an emergency, such as anticipated equipment failure or a change of mode of transmission.

The receivers associated with the land line transmission mode are shown to be connected in parallel to represent a .variety of decoder arrangements for station calls, control functions and verification of received call. The lower receiver is set up to supply parallel decoders, one of which has its output connected to a station encoder and transmitter to verify the successful detection of the calling code by transmitting a unique code back to a receiver and decoder at the master station.

In conjunction with the invention system, a particular type of code structure and signal waveform is employed. A detailed explanation of its advantage to both encoding and decoding equipment as well as to transmission equipment will be made apparent in the detailed description to follow. Briefly, the

' code structure contemplates a translation from decimal members into a binary representation in the encoder, a translation into an on-off waveform between the encoder and the transmitter and a given receiver and a translation from the on-off waveform into a different binary code for detection at the receiver decoder. Where necessary the on-off waveform is translated from a DC level into a tone or tones before being supplied to tansmitting equipment and such tone or tones are translated back into the on-off waveform before being supplied to the detector part of a receiver. The various code forms employed are made to be optimum for the type of equipment used in each phase of system operation. In the description to follow the terms set" and clear" represent the binary symbols employed in encoding. These terms are used relative to conditions caused in a series of bistable devices in an encoder register which, in the disclosed detailed embodiment, is a specially wired magnetic core shift register. When a device is set is will produce an output pulse and when it is clear it will produce substantially no output pulse.

The terms level (L) and not level (II) hereinafter used relate to the presence or absence of the code voltage level, or on and off." The L and L terms are also used relative to the decoder operation where L and E pulses are generated from the received waveform. These pulses are employed to serially drive a decoder register which, in the described detailed embodiment, is a magnetic core shift register wired to perform the decode function.

Referring now to FIG. 2A, a command station 10 is shown in a general schematic diagram to include components to produce and transmit a calling code in the L, I waveform previously mentioned. An input device such as keyboard 12 is provided to enable the selection of calling code through pushbuttons representative of numbers I through 9 and 0. The output from 12 is connected to a driver 14, which is made to be responsive to each pushbutton to inject into an associated register 16, a set-clear pattern in a standard twmout-of-five code representative of the particular decimal output from 12. This is shown in the following schedule with set (S) and clear (C) assigned to five adjacent stages or time related bit positions.

SCHEDULE Digit Bit Position l C C C S S 2 C C S C S 3 C C S S C 4 C S C C S 5 C S C S C 6 C S S C C 7 S C C C S 8 S C C S C 9 S C S C C O S S C C C In accordance with the invention, register 16 is comprised of a series of bistable stages adapted to serially store a calling message comprised of a number of characters each made up of two set conditions and three clear conditions in five adjacent stages. FIG. 2 shows 16 to have 26 stages to accommodate a message comprised of four decimal numbers, a start and a stop character, with four extra stages. Typical messages are shown in FIG. 4 in terms of set and clear states in the register stages.

After each number is input from 12 to 16 the driver 14 is caused to operate to shift the 5-bit character from the first five stages to the second five stages. For the message length shown (four numbers), after input of the fourth number the stages 5-26 of register 16 will be filled by reason of tag start and stop characters caused to be injected before and after the first and last bits of the message number in a manner to be detailed hereinafter.

There is provided a driver 18 which is made responsive to a nonbusy condition of transmitter 20 to cause 14 to drive 16 to output the stored message by driving the stages with an oddeven alternating drive. This produces a serial output of set and clear conditions of the stages. A translating device shown schematically as a relay 22 is provided to translate the output from 16 into the on-off waveform previously mentioned.

The relay 22 includes two coils W1 and W2 which are connected to be alternately operated through a latching contact set cl by input pulses from 16. The coils are chosen such that a pulse through one of the coils will energize such coil to eventually drive the contact set cl to open the circuit to such coil and close the circuit for the other coil. There is also provided a latching contact set (2 which is driven by both coils W1 and W2 between a ground contact associated with a L output and a contact from battery Bl associated with an L output.

As mentioned, a set condition will produce a pulse output from 12 and a clear condition will produce substantially no output pulse. With this in mind the message 5371 stored in 16 and comprised of set and clear conditions, as indicated in the top line of FIG. 4, will result in an output from 22 to 20 like that shown in the third line of FIG. 4. The second line of FIG. 4 is a time scale made up of 22 millisecond increments. With the contact set cl positioned as shown, the first output from 16 (the tag set condition producing an L pulse) operates to drive cl to close the path to coil W1 and will operate to close 02 to battery B1. This produces an L input to 20. The next bit is the first bit of the first character 5 and is a clear condition. This produces no output from 16 and does not operate relay 22. The next bit is a set condition and thus produces a pulse to coil W1 to drive contact cl to W2 and c2 to the ground side of the contact set. The output to 20 will then be L. The next bit output is a clear condition which does not operate 22. The fourth bit of the character 5 is again a set condition. Coil W2 is operated to return cl to call W1 and c2 to battery to produce an L output to 20. Following FIG. 4 it will be apparent that th e set-clear pattern stored in 16 will be translated into an L, L waveform wherein each set condition causes a transition from the previous voltage condition to the alternative condition, L or L.

In accordance with one aspect of the invention, the clock rate or rate of drive pulses supplied to the register 16 is made to be such that the set-clear pattern is output relatively slowly. This produces a waveform comprised of L and I: conditions which are relatively long in duration. For example, relative to the messages of FIG. 4, the clock rate is adjusted so that each bit from 16 is output every 22 milliseconds. This means that both L andT. conditions will persist at least 22 milliseconds. Each character of a message, being comprised of 5-bit positions, will be 1 milliseconds in length and a four character message with l-bit for each tag and stop character will be 462 milliseconds in length (the stop character not being part Q message length). The relatively long duration of the L and L conditions is utilized to reduce interference from RFI and various electrical noise. This is because the typical noise pattern in either radio or land line transmission is comprised of bursts of short duration. Accordingly, the rate of message transmission is made to be as slow as is practical, considering the number of messages per unit of time which must be handled by the system. If the rate is as above outlined a system can handle one call or message per half second or calls per minute. Normally. it is preferred to provide a guard band between calls of a length of time a little greater than the time length of a character of the message. If this is done the previously outlined message length will still permit a calling rate greater than one call per second. This rate is quite sufficient for a 10,000 subscriber system. It is, of course, contemplated that for larger systems the message rate may have to be increased, but even with a substantial increase the pulse rate will be far slower than that of the prior art practice.

As a further aspect, it will be apparent that the message above-described is numerically complex in the sense that it includes some 22-bit positions for a single call. This complexity further serves to reduce the likelihood that any combination of spurious pulses will reproduce a given code to cause a station decoder to respond. The code waveform, being of a single tone of L and Econditions, so compensates for the number and length of the code that overall the code of the invention is still more easily handled than with prior art systems.

The resulting waveform is used to modulate transmitter 20 to effect a transmission of the calling message.

FIG. 2B shows a version of the circuit wherein the outp ut of the last stage of 16 is fed to a standard flip-flop 19 which in one state drives a tone generator 21 to produce a frequency f, during L conditions and in the other state merely keys the transmitter 20 to transmit no tone during I: conditions. Each time a set state is output from 16 the flip-flop reverses its output. FIG. 2C shows another embodiment wherein the flip-flop 19 drives a tone generator 21 for L conditions and a tone generator 23 for L conditions. The two frequencies f and f then represent on and off conditions supplied to 20. As can be appreciated the use of but two tones still represents a considerable saving in required bandwidth. This latter approach is particularly desirable when the transmission mode is single sideband.

FIG. 3A is of a representative receiver station. There is included a receiver 24 to receive and demodulate the message waveform to produce an output in the same form as provided from 22 to 20 by the circuit of FIG. 2. The output from 24 is fed to 26, schematically shown as a relay, which is connected to a battery B2 to drive a sequence detector 32 with L and L pulses developed in

pulse generators

28 and 30. The fourth and fifth lines of FIG. 4 show the on condition of the L and L lines from 26 to 28 and 30. The detector includes a serial decoder set up to recognize the transmitted message and produce an output to some indicator device.

The circuit of FIG. 3A is operated by the waveform of the message 5371 of FIG. 4, as follows.

In accordance with the invention the contact set c3 is nor; mally clgsed to ground such that 28 is energized to provide a train of L pulses continuously to 32. As will be made apparent, until the first L pulse in input to 32, the decoder does not respond. When the message input begins the first condition is made to be the tag or L-bit. This actuates 26 through coil W3 to close 03 to the L path and energize generator 30 to produce a train of L pulses to 32. The next bit in accordance with the waveform for 5371 in FIG. 4 is still L and generator 30 is left on long enough to produce tw q pulses to 32.'There is then a transition in the waveform to L to cause the coil W3 to close c3 to the L path and energize 28 for a period long enough to produce two L pulses input to 32. Next, there is a transition to L for four time periods. Relay 26 is then operated to energize 30 to provide four L pulses to 32.

FIG. 3B shows a circuit operable with the encoder circuit of FIG. 2B. The received signal is supplied to a filter 25 sensitive to f which in turn drives the coil W3 to cause the operation of

generatog

28 and 30 dependent upon the presence or absence of L and L conditions or f,. FIG. 3C shows the receiver circuit for operation with the encoder circuit of FIG. 2C. Two

filters

25 and 27 separately detect f and f, to directly drive the

generators

28 and 30 to produce L and L inputs to the sequence detector 32.

As can be discerned from FIG. 4, the input of the waveform results in the generation of L andT: pulses on separate paths driving 32. If these pulses are assigned S and C representations a comparison with the code set into 16 will show that the initial code differs from the final code, which is decoded to provide a detect output. Also for comparison, a second message 5373 is shown in FIG. 4. This message differs only in the last character. As will be apparent, the number of bits of the generated message is even, the number of bit positions is even and the start and stop conditions are identical. This permits parity checking procedures to be easily implemented.

From FIG. 4 it will be observed that the number of bit positions transmitted is one greater than the number of bit positions decoded. This is inherent in the use of a stop bit which is always the same condition as the start bit, if the number of bits and bit positions is even.

This operates to the advantage of automatically restoring the receiver station to the L condition, which is necessary for system operation as thus described.

In regard to the system as described, various available components may be employed. The register of the encoder may be a shift register having a suitable number of stages each comprised of a bistable device such as a relay, tube, transistor or magnetic core. The encoder driver may be any suitable pulse developing device set up to advance intelligence stored in the register and to, on command, clear the register after a given message has been transmitted. Input from the keyboard may be implemented by the driver in serial or parallel fashion. The decoder may be any suitable device set up to operate serially from the type of pulses produced from the translator 26.

Certain of the control logic required for the foregoing general embodiment has for simplicity been left to be manually implemented. In the description to follow an alternative and more specific embodiment of the system of the invention will be detailed, which incorporates an automatic logic control to carry out the various component operations automatically from keyboard input to detect at a receiver station.

In the detailed embodiment to follow the bistable devices employed in the encoder register and in the receiver decoder are multiaperture cores, one core per stage. The general drive scheme employed is that known as MAD-R, described as to a shift register circuit in U.S. Pat. No. 3,125,747. The encoding technique of injecting set-clear patterns to be described is generally taught in U.S. Application Ser. No. 363,165 filed Apr. 28, 1964, now U.S. Pat. No. 3,484,755 in the name of]. P. Sweeney. The decoding technique is generally taught in U.S. application Ser. No. 444,714 filed Apr. 1, 1965, now U.S. Pat. No. 3,444,532 in the name of Joseph P. Sweeney. Preferred core drivers are generally taught in U.S. Pat. No. 3,221,176. A specific driver circuit for both the encoding circuit and the decoding circuit is taught in U.S. Application Ser. No. 378,652 filed June 29, 1964, now U.S. Pat. No. 3,284,644 in the name ofDormer et al.

DETAILED ENCODER DESCRIPTION Referring now to FIGS. A and 53, an alternative and specific encoder circuit 50 is shown, which is capable of auto matically generating the calling message heretofore described as an input to the system transmitter. The circuit is supplied by a power supply 52, which may be a standard unit capable of developing regulated DC outputs from a line supply. In the embodiment shown the line supply is 110", 60 cycles AC and the outputs of 52 are separate DC levels of about and 40 volts.

These outputs are connected to the various component circuits of the system, including a code input unit 54 which is operable to selectively inject an encoded message into a register 56. The unit 54 includes 10 switches Kl-K9, and KO operable normally as by a keyboard or by any suitable transducer to close selected paths to the register 56. Included in 54 is a lamp LAl in circuit through a current adjusting resistor R1 to ground and energized by a transistor Q1 (in FIG. 5B) supplied by the 40 supply and 52 through control components to be described hereafter. The base of Q] is connected to be dropped close to ground condition after the first character of a message is injected into the register to thus cut off lamp LAl. This indicates to the operator of 54 that a message is in process. The lamp LAl is held off by the off condition of Q1 until the complete message has been encoded and transmitted and the circuit 50 is ready for the next full message to be sent. This is accomplished by causing the SCR next to O1 to fire after the input of the first message character and latch on until the message is transmitted.

Referring back to 54, each of the switches Kl-K9 and KO includes two contacts such as KlA and K113, as shown relative to Kl. The switches of 54 are made such that the upper contacts close before the lower contacts. Switches of this type are well known. This switch construction permits the circuit path associated with the upper contact to be closed and stopped from bouncing before closure of the path associated with the lower contact.

When the upper contact KlA is closed a circuit path is provided leading from the contact to 56 and to windings having set inputs to a selected two of the first five stages of the register. For reasons to be made apparent, the register 56 includes 26 stages. In the register 56 the first ten windings are each associated with one of the numbers 1-9 and 0, and each winding links two of the first five stages in patterns like that given in the schedule previously set forth in the specification. The numbers above the windings in FIG. 5A represent the number of the stages linked by such winding. In the example previously given for the message 5371 in FIG. 4, the first switch operated links the second and fourth stages to set such, the first, third and fifth stages remaining clear.

In accordance with a preferred embodiment of the system of the invention, each stage is a multiaperture core (like that to be described in the detail given as to the preferred decoder embodiment to follow). The register 56 then includes 26 cores. The cores are connected by coupling loops to provide serial transfer. The first l0 windings shown in FIG. 5A are comprised of set turns N, linking two of the five cores so as to set such cores when the circuit is energized. Additionally, the cores are all linked by advance and prime drive windings for a standard MAD-R, odd-even advance circuit like that detailed in U.S. Pat. No. 3,125,747, previously mentioned.

From each of the set windings of 56 the circuit path is commoned to a lead connected to the anode of an SCR Q2 in FIG. 5A) which is initially in an off state. The cathode of QL. is connected to ground, as shown, and the gate of O2 is connected through a resistor R2 and a capacitor C1 back to 54 to the output side of the lower contact of each switch, such as KIB of K1. Since 02 is initially off, closure of KIA does not energize the circuit path just described.

The contact KlB has its input side connected in common with the input side of KIA to the collector of an NPN transistor Q3 having its emitter connected to ground as shown. Transistor O3 is also initially off. A capacitor C2 is provided with a charge of nearly 40" from a connection to the 40" lead from 52 through charge limiting resistor R3. When KllB is closed the lead from C2 (through the path associated with KlB to charge Cl and R2 to the gate of Q2) goes suddenly from ground to 40". The transient developed thereby couples through Cl and flows through R2 to gate Q2 on and cause conduction draining C2. The resulting discharge causes current flow through the path including contacts KIA, the selected set windings of 56, the common lead of the windings to the anode of O2 to ground. Since the contacts KIA are at this time already closed, no bounce or transient will be developed due to switch closure, which could adversely affect the setting of the stage selected.

When C2 has substantially discharged, Q2 will cut off due to a lack of holding current and will remain off due to the back bias developed by the collapse of the field in inductor L1. The capacitor C2 will recharge through charging resistor R3 from the 40 supply lead to 52. The resistor R4 is chosen to keep this supply from holding Q2 on after C2 has discharged and to limit the current flow through Q2 during discharge. The inductor L1 and resistor R5 serve to form the pulse produced when C2 discharges. Resistor R6 references C1 to ground and resistor R7 is a gate ground reference for 02.

All during the operation just described Q3 remains off due to a bias supplied to its base through a resistor R8 from control and timing portions of the circuit. lf Q3 is caused to fire it will keep C2 discharged by drawing off the charging current from R3 to ground. If C2 cannot charge, then Q2 cannot be gated on and the circuit is effectively disabled from setting the register. This control will be explained later in detail wherein as one disabling operation Q3 is fired after the input of the fourth character of a message (assuming message composition of four members).

As part of the operation just described there is provided a path from the gate circuit of Q2 through a current limiting resistor R9 and an isolating diode D1 to the START terminal of a flipflop 58. The flip-flop 58 may be considered as any standard unit adapted to be triggered to provide one of two outputs of 10" supplied from 52. One output is associated with an on condition which initiates a standard multivibrator 60 to supply alternating pulses on the two output leads shown. The other output of 58 serves to turn 60 off and thereby stop the supply of pulses output therefrom. The output of 60 is connected to a driver 62 capable of supplying properly timed advance and prime pulses to the register 56 to advance or shift the message therein. Assuming the register 56 to be comprised of multiaperture cores coupled in accordance with the MAD-R technique, the driver 62 is preferably that of the above-mentioned Dormer application.

When Q2 fires a pulse is produced which starts 58, 60 and 62 to advance the first character set into 56 out of the first five stages or cores along the register to make room for the second character of the message to be stored. therein.

Advance of the characters set into 56 is controlled as follows. At the end of each transmission, by means to be described, the sixth stage is set (the remaining stages or cores being cleared out to provide the tag bit heretofore mentioned). This tag bit always precedes a message and leads the first character along the register as 62 operates to advance. The eleventh stage of the register is made to include a dynamic output winding (numbered 11 in 56) leading to the gate of an SCR, Q4 (FIG. 5B). When the tag bit is input to stage ll the output winding will produce a pulse to the gate of Q4 causing it to fire and latch on supplied by current through limiting resistor R10 from other control circuitry, in turn supplied by the 40" lead of 52. When Q4 fires it cuts ofi' Q1 as previously mentioned and provides a pulse from its cathode through an isolating diode D2 and capacitor C3 to a lead going to the STOP terminal of 58. Resistor R11 couples DC components of this pulse to ground. The pulse produced when Q4 goes on thus cuts off 58, 60 and 62 to stop the advance of the message. This leaves the tag bit in stage 1 l and the stored S-bits (two set and three clear conditions) in the stages numbered 6-10. This also leaves the first five stages clear for the input of the next or second character of the message.

Assuming now that the switch for the second character 3 is closed, the circuit will operate as just described to set the

stages

3 and 4, leaving the

stages

1, 2 and 5 clear. See FIG. 4. Flip-flop 58 will again be energized by O2 to advance the stored message. The tag bit will move from stage 1 l to stage 16. Another dynamic output winding on stage 16 leads to the gate of SCR O5 to cause it to fire and hold on in the manner described relative to 04. This produces a pulse to the STOP lead of 58.

The next or third character 7 set into 56 causes an advance until the tag bit reaches stage 21 to provide an output to gate Q6 on which, as described, serves to again stop 58 and further advance. The last or fourth character is then input into the first five stages and then the message is advanced until the tag bit enters stage 26 to fire Q7 and again stop transfer. At this time the tag bit is in stage 26 and the four characters of the message are in stages 625.

When Q7 is gated on a lead from its cathode circuit carries the ensuing voltage transient through coupling capacitor C4 to gate of an SCR Q8. This gates Q8 on to draw current through an auxiliary set winding (S5 in 56) linking stage 5 to set such stage and provide a stop bit to complete the message stored in 56. The cathode of O8 is tied to ground and its anode is connected through the winding S5 to draw current through an isolating diode D3 linking resistor R12 to the 40" supply lead.

The operation of the circuit to fire Q7 also serves to initiate message output. When Q7 fires, the line leading from its cathode to resistor R13 (in FIG. 5A) is placed at a voltage level to charge the capacitor C6. The charging time for C6 is made relatively short so that after a fraction of a second the charge of C6 will fire unijunction transistor Q9. This delay is used to permit answering of multiple master encoders (by having different charging times in different encoders) and to assure correct operation of the circuit to prevent output if the line is busy. Conduction of Q9 will produce a pulse through isolating diode D4 to the START terminal of 58 causing 58, 60 and 62 to advance the message stored in 56 out of the register. The output winding labeled OUT is connected to input the message serially to a pulse stretcher 64.

The unit 64 may be considered as standard, having the required function of translating the dynamic output from the stages (which if cores, would be a few microseconds in length) into pulses of lengths suitable for the type of waveform heretofore described.

During this time a capacitor C7 is also being charged through a path including isolating diode D5 and charging resistor R14 connected by a lead to the cathode of Q7. The charging rate of C7 is relatively long (about 1 second) to permit the operation of 64 and the translator to accommodate the complete message which is then transmitted. When C7 is sufficiently charged it operates to fire a unijunction transistor Q10 drawing current from limiting resistor R16 and the 10 supply from 52.

The output of Q10 is connected to the gate of an SCR Q11, which is caused to fire and pull the base of the Darlington transistors Q12 and 013 to ground and effect cutoff. The transistor Q12 and Q13 are supplied by the 40' lead from 52 to provide the holding current to the SCRs Q4-Q'7. When Q12 and Q13 cutoff, Q4-Q7 also cut off and Q1 goes back on to cut on lamp LA1 and indicate that the circuit is ready for the next message.

When Q11 is cut on its anode circuit is pulled to ground to in turn supply a pulse on the lead connected to 64 at the end of the message. This reestablishes the initial circuit condition and prevents an erroneous output to the translators. When Q11 comes on, C5 discharges through D3 and the winding designated S6 which operates to clear all of the stages except 6, which is set with the tag bit for the next message to be encoded. The inductor L2 serves to shape this pulse. Q11 remains on until C5 is discharged and then cuts off due to a lack of holding current. When Q11 goes off, Q12 and Q13 come on to reestablish the anode supply to Q4-Q7 which are then off, but prepared for the next message.

Going back to the operation of Q7, when it is gated on by the input of the fourth character, the lead from its cathode extends over to the base of Q3 through R8. When Q6 goes on this operates to disable Q3 and the associated circuit to prevent its operation to set the register with message characters.

If the transmitter is busy at the time a message is initiated by operation of 54, the circuit including Q2 will also be disabled. This is accomplished by a connection from the transmitter to the lead labeled Line to the left of FIG. A under 54. This lead is coupled through a diode D6 to the base of an NPN transistor Q15 and through the emitter of 015 to the voltage divider comprised of resistors R18 and R19 to the base of NPN transistor Q16, both of which are normally off. The supply is connected to the emitter of Q17, which has its collector tied to ground through R22. The collector of 015 is also tied to the 10" supply lead from 52, which is extended through a limiting resistor R20 to the collector ofQl6.

The base ofQ17 is coupled through a speedup capacitor C9 and a resistor R2] to the collector of Q16, which is connected through an isolating diode D7 to the emitter ofQ9. The collector ofQl7 is connected to a lead going to the diode D8 to provide a back bias. The emitter of Q16 is suitably connected through the diode D9 to ground.

A diode D10 is connected in circuit with its anode to the anode of D8 and its cathode to the anode of D7 through R13.

With this circuit, if the line lead is busy it will experience positive and negative levels of voltage as the waveform rises and falls. The positive levels will gate Q15, Q16 and Q17 on to draw current from the 10 supply. This will drop the voltage of the line leading to D7 down to a low value. This forward biases D7 to cause C6 to dump its charge so that it cannot fire Q9. When Q is off (no line signal) D7 is back biased to permit C6 to charge as previously described. When the line lead is busy the positive excursions of the waveform voltage cause Q17 to fire. This back biases D8, which permits D10 to be back biased by input of the fourth character of the message when Q7 tires to establish a voltage level connected to the cathode of D10. This causes the common point connected to the anodes of D8 and D10 to experience a rise in voltage which couples through C12 to the cathode of Q14, permitting C7 to charge through Q14 to ground. The diodes D8 and D10 thus serve to disable encoding if the line is busy or if the fourth character has been set into the register.

In the foregoing manner the invention system is carried out to automatically encode a message in the form shown in FIG. 4.

DETAILED DECODER DESCRIPTION FIGS. 6 and 7 show two magnetic core arrays set up to decode the messages 5371 and 5373 shown in FIG. 4 to provide a detect output. Each array is wired to respond to the L and I; pulses heretofore discussed and each array could therefore be associated with a different receiver station or with different functions at the same receiver station. The leads shown represent drive windings connected in the manner shown in FIG. 8 to drive in a selected pattern of 21 multiaperture cores 0, and l,-20, arranged in the sequence of the bit positions of the transmitted message. Each core may be a single multiaperture magnetic core, or integrated in some composite core structure representing all of the cores. In either case there is for each core a geometry defining major and minor apertures and associated major and minor flux paths. The cores in FIG. 8 are shown as 70 to include a major aperture 72 and a minor aperture 74. In this particular embodiment the aperture 74 is a transmitting aperture. A number of coupling loops such as 76 link the cores in serial fashion to provide a serial transfer f magnetic remanence from core to core responsive to L and L drive pulses selectively applied through L and -L drive windings. These come from the pair of generators shown in FIG. 2. There is an additional drive winding, not shown, which links all of the minor apertures of the cores in a sense to switch or prime flux in a counterclockwise sense relative to the minor apertures in the manner described in U.S. Pat. No. 3,125,747 mentioned above.

The leads from L and L are connected through turns denominated N,, N, and N, which link major or minor apertures of the cores in a selected pattern. As will be apparent, the N, and N, windings link the cores through the major aperture and the turns N, link the cores through the minor transmitter apertures. The turns N, link only the 0;,core and are in a sense to drive such core to the set or 8 condition heretofore discussed in terms of intelligence content. The set condition may be taken as that condition of magnetic remanence wherein all of the remanent flux is in a counterclockwise direction. The N, turns link the cores in a clearing sense and either drive or leave the cores so linked in the clear or'C condition previously discussed. The clear condition has all of the remanent flux oriented in a clockwise direction. The N, turns link the core minor apertures in a sense so as to switch flux in a clockwise sense about the minor aperture 74. Additionally included with respect to the circuits of FIGS. 6, 7 and 8, but not shown, is a winding linking all of the cores O and l,20 with N turns so as to clear out the entire chain of cores.

Linking the last core 20, is a coupling loop denominated output which goes to the indicator or function device heretofore mentioned.

As mentioned, prior to the receipt of any message, all of the cores 0, and l,-20, are placed in the C condition effected by the application of a clearing pulse at some period of time after the end of the last message. This is shown relative to the time and sequence of the messages in FIG. 4 on the line labeled clear. Prior to the receipt of a message the L generator 28 produces pulses through the 1 line. This effects no transfer function, since all of the windings associated therewith are N, or N, turns and all of the cores are then in the clear condition. As the first bit of each message comes in the L line is energized with an L pulse. This operates on the N, turns linking 0, to drive the core to the set condition. The first pulse operates on the remaining cores again through only N turns and N, turns, and since the remainder of the cores are already in the cleared condition no system function results. The N, turns linking core 0, are made sufficient relative to the N, turns linking the same core to provide an MMF overriding the MMF due to N, so that the core 01,. is completely set. Reference may be made to FIG. 9 to show the initial states of the cores and then the states of the cores following the receipt of each of the L and L pulse associated with the first message. As can be seen, following the receipt of the L and L pulse associated with the first message. As can be seen, following the receipt of the tag level pulse the core 0, is set and the remaining'cores are cleared. The next pulse in accordance with the first message is again an L pulse applied to the L line shown in the drive circuit. This will again set core 0, The application of the L pulse will operate differently on core 1, with respect to the N, turns at this time, due to the priming operation which will have switched the set flux about aperture 74 so that the MMF applied via the N turns will cause a transfer of flux via coupling loop 76 to the core numbered 1, to set such core, thus transferring the set condition t o core number 1,. This is shown in FIG. 9. The next pulse is L and as is indicated from the FIG. 9, it results in a transfer of a set condition stored in core I, to the core number 2,. This is again due to the N, turns linking core 1,, which, because of the priming function w l contain flux in a proper sense to be switched by such turns to transfer the set condition to core number 2,. The next pulse is again a L pulse and it will effect a transfer of the set condition state stored in core number 2,. to core number 3,. It should be noted that certain of the cores preceding the core number 3, will be set or partially cleared out by the pulses on N,, N, and N The important thing, however, is the advance of the set condition along the cores. If the next pulse is a proper pulse in accordance with the code, which would be an L pulse, the set condition will be transferred to core number 4,. If the remaining pulses are proper in accordance with the assigned code the set condition will be continuously advanced to core number 20, and an output will be provided on the output loop connected thereto to provide an indication or control function heretofore described.

Relative to the foregoing description of a successful advance, it will be observed that the logic utilized with the detector circuits of FIGS. 6, 7 and 8 are one of selectively omitting the N -turns from successive cores in accordance with the particular code assigned. For example, the first pulse in accordance with the code shown in FIG. 4 after the tag pulse is an L pulse. It will be observed that the N, turns associated with the L leads are omitted from core number 1,. In a similar manner the third and fourth pulses in accordance with the code are both T. pulses and the N, turns associated with the L lead are omitted from the cores numbered 2, and 3,. The L and L pulses are, however, applied to each core 0, and I, through 20,. via the N turns which link all cores and are in series with the L andI: leads. A successful transfer is then dependent upon whether or not there is an MMF developed in the receiver core, which will swamp out or block the successful transfer initiated by the N turns on the preceding core. To explain this more completely, assume that the first pulse of the message (after the tag pulse) is incorrect, which would mean that it would be a L pulse rather than an L pulse, as shown in FIG. 4. The L pulse would tend to drive core 0, through the N, turns to transfer its set state to core number 1,. The L pulse would, however, drive core number 1, through the N, turns in a clearing sense to block the receipt of the set state and thus prevent a successful propogation. If all the remaining code bits were correct the last core would still be in the clear condition at the end of the message and no output would occur. In the same manner an incorrect bit anywhere in the message would cause a failure of transfer and preclude any output.

The second message of FIG. 4, 5373, necessitates a change in the wiring pattern of the decoder. This is shown for comparison in FIG. 7 by the change in the N, windings of the last five cores. In this regard and as a significant aspect of the invention, circuit changes to facilitate receipt of different codes are accomplished by the structure shown in FIGS. 10, 11 and 12. The unit 80 represents a receiver station set up to receive the code 5371. This assignment is accomplished by code plugs 82 which each are inserted into the face of 80 to engage pin members 84 shown in FIG. 11, which are connected to core windings in the decoder. Each pairof pins is made to connect the ends of a selected core clearing winding N,. This is shown in FIG. 8 by the points P as to

cores

1, and 2,. The windings installed on the cores are fixed and the windings to the pins are fixed. Each of the character positions include an array of pins connected to provide clearing inputs to the numbered cores 1,.,,, The N, input to core and the N, turns are hard wired into the register.

Each plug 82 includes a body 82a formed of plastic material having the related number printed on the face, as indicated in FIG. 10. Attached to the body is a plate 82b, as shown in FIG. 11, carrying a number of receptacles 82c aligned to mate with the pins 84. The pins are connected by conductive paths 82d (printed circuit, solder or wires) in patterns to define the interconnections necessary to define the choice of cores for the character. As previously mentioned, code assignment is achieved by not driving a given core with N turns. Thus, in FIG. 8, the

cores

1,, 4,, 5, are not driven by N, from L and the

cores

2,, 3, are not driven by N, from L. In FIG. 8 the paths 82d form the connections in the L lead a to b, b to c, (shorting out the N, winding from L on core 1,) c to d, e tofand so on along the array ofcores.

As the L lead the paths 82d connect 3 to h, h to i, itoj,j to k and so on down the core array.

In this manner a given decoder design can be constructed for all codes, the particular code assignment being made by selection of a numbered plug. The decoder for 80, set up for 5371, would then detect 1735 if the plugs were reversed from that shown. As can be discerned, considerable economies are derived by making all decoders identical, except for the relatively inexpensive code plugs.

Referring now to FIG. 13, there is shown in detail a circuit 100 for the decoder of the system of the invention. The circuit is supplied by a 12 DC supply regulated to about volts by a standard C regulator 102, which is also used to supply the receiver of the system. The output of 102 is then connected in a DC to DC converter 104, which converts the 10 volts to about 40 volts used to power the magnetic driver 106 of the circuit. The driver 106 is preferably of the type disclosed in the Dormer application previously mentioned. The driver 106 is connected to supply properly timed and shaped advance and prime pulses to the magnetic cores and windings schematically represented in unit 108. The winding scheme is shown in detail in the above-mentioned Sweeney et al. application. Also connected to the magnetic unit is a reset circuit including a normally closed switch 108 supplied by +10 and in series with an indicator lamp LA2 adapted to be driven by an SCR Q20, which is normally off. The lamp LAZ serves the function mentioned relative to FIG. 3 of indicating the successful detection of a received code. As also mentioned previously, this may serve to indicate that the station is being called or paged, or it may constitute a control function. The SCR Q20 has its gate connected to the output of the magnetic decoder unit (the last core) and is triggered on by such output to hold on, supplied from the 10" supply from 104. When Q20 is fired the resulting voltage developed across R60 is caused to gate a further SCR Q30 on to draw holding current from 104 through the coil of a loudspeaker LS. This output from 104 is preferably made oscillatory, about 1.2 k.c.p.s, to provide an audible tone from LS to supplement the visual indication of LA2.

The three leads from 106 are advance and prime drive leads connected to the various turns linking the cores of 108.

In accordance with the operation of the decoder heretofore described, L and L pulses are generated in a pattern to cause the successful advance of a set condition from the core through the remaining cores l,20,. The L andL pulses are developed by selectively gating one of the SCRs Q21 and Q22 on to close a path to ground from the magnetic driver 106. As explained in the Dormer application, the pulse for the advance, or L and L, circuits, including turns N and N, is derived by discharging a capacitor such as C15 through a pulse shaping network including L3. The capacitor recharges through the priming circuit, turns N priming the cores for the next advance L or L pulse.

There is an additional clearing path shown connected to an SCR Q23 and to the 40 volt supply through a charging network. This network includes a coupling diode D15 and resistor R30, a charging resistor R31, capacitor Cl6and a pulse shaping indicator L4. Capacitor C16 is charged from the supply and discharged when Q23 is fired by a control pulse generated elsewhere in the circuit. When Q23 fires the associated N, turns clear out all the cores of the decoder. This occurs between messages as shown in FIG. 4 on the line labeled clear.

Referring now to the data input side of circuit 100, the waveform of FIG. 4 comprising the transmitted message is input through a lead including a decoupling circuit comprised of a capacitor C17, a capacitor C18 and an inductor L5. This circuit effectively grounds high frequency components which may be passed on from the receiver. The resulting input is then essentially the waveform transmitted in terms of ti e presence or absence of a voltage level. In practice the waveform generated as an input to the transmitter will appear as in FIG. 4 or in part in FIG. MA.

This waveform may experience some degradation due to transmitter range or doppler effect, if the medium of transmission is radio. This is shown by the waveform 14B. Alternatively, the time period wherein there isno level may experience some transient like that shown in FIG. 14D. This phenomena occurs as ringing in land line transmission. The circuit is adapted to prevent a failure of response due to the type of degradation evidenced by FIG. 14b and to prevent a wrong call response due to the spurious pulse shown in FIG. MD.

This is accomplished by a number of circuit features which will now be made apparent. The filtered input from the data line is fed to the base of a transistor Q23 which serves an an emitter follower. The collector of Q23 is supplied from the 10" supply of 102 and its emitter is connected through a voltage divider comprised of R32 and R33 to the base of a transistor Q24. The resistors R32 and R33 are rated to hold Q24 off in the presence of low voltages developed by Q23, as for example, voltages below a 2 volt level. A resistor R34 is connected from the base of Q23 to ground to bias the base against temperature efiects.

The transistor Q24, along with a transistor Q25, serves as a Schmidt trigger to restore the square wave shape of the input waveform from that shown in FIG. 14A. The collectors of Q25 and Q24 are supplied in parallel from the supply, as shown, through limiting resistances R35 and R36 and variable resistances R37 and R38. The emitters of 025 and 024 are tied together to capacitor C19 and diode D16, which are in parallel to ground. This latter connection serves to set the triggering bias level necessary to fire Q24 and Q25. A capacitor C20 is connected between the base of Q25 and the collector of Q24 to speed up the switching action of the trigger resistor R39 maintains a DC level to 025 from the supply.

A capacitor C21 is coupled to the collector circuit of Q24 through a resistor R40 and through a diode D17 and resistor R41 in parallel with R40. The capacitor C21 is also coupled to the emitter of a unijunction transistor Q26 having one electrode connected through a limiting resistor R42 to the 10" supply and its other electrode connected through a signal developing resistor R43 back to the other side of C21 and to ground. Additional unijunction transistors Q27 and Q28 are in parallel with 026 with respect to the supply and to ground. The transistor Q27 has its emitter connected through a variable resistor R50 back to the resistor R37 in the collector circuit of Q24. The other transistor Q28 has a similar connection to the collector of Q25. The emitter of Q27 is also connected to a capacitor C22 and the emitter of Q28 is similarly connected to a capacitor C23. 4

The other electrodes of O26, Q27 and Q28 are each respectively connected to its gates of O21, Q22, and Q23 through a resistor such as R49 shown relative to Q26.

As previously mentioned relative to FIG. 3, when no message is being transmitted the decoder is continuously supplied with L pulses. This is achieved as follows. Capacitor C22 draws a charging current through R45, R50 and R35 from the 10" supply to raise the voltage to the emitter of Q27 until it goes on to discharge C22. This discharge presents a gating pulse to the gate of Q22 causing it to fire discharging C through the L lead. As soon as C22 is drained Q27 goes off. Q22 will go off when C15 is drained to permit C15 to recharge. This operation repeats to produce a train of L pulses to the decoder as long as the L condition exists and there is no input level to the circuit. The charging period of C22 is made to be about 22 milliseconds. During this time Q23 and Q24 are held off by the base path to ground. When 024 is off the 10 supply (through the path R35, R37 and R40) serves to charge C21, which is made to have a relatively long charging time (about 130 milliseconds). As C21 approaches its charged condition it biases the emitter of 026 to cause it to go on temporarily providing a gate pulse to fire Q23 and develop a clear pulse through the decoder. Capacitor C21 will again charge and the foregoing will repeat as long as the 1: condition remains. The clear pulse function has been previously mentioned.

During the L input condition Q25 is on supplied from the 10 supply as shown. There is a lead from the positive side of R36 to the emitter circuit of 028 which leads to C23. This places a reduced charging voltage on C23 which is adjusted by R38 to cause it to charge to about half its full level. The capacitor C22 is similarly supplied via a lead to the positive side of R35. During the L condition Q24 is off and R50 is adjusted to provide the charging period heretofore mentioned.

When L comes on the half charge on C23 will cause Q28 to come on in less time than if C23 were drained. This period is made to be about 11 milliseconds. When the L condition is present C22 is brought to half charge by the connection through R50 to R35, 024 being then on and R37 being adjusted to provide the proper charging voltage.

In summary, the capacitors C22 and C23 each first charge to cause Q27 and 028 to come on about I 1 milliseconds after the Schmidt trigger switches and thereafter required full time to charge. This causes the SCR's Q21 and Q22 to produce & and L pulses spaced 11 milliseconds after the L and L waveform conditions occur and thereafter to produce pulses spaced 22 milliseconds apart.

When the waveform representing the message is input to the first portion is always L. This cuts on Q23, which cuts on Q24 and cuts off Q25. When Q24 comes on the current charging C21 is drawn off to disable Q26 and Q23 and prevent the clearing operation. When Q24 comes on C23 charges and gates 028 to fire 021. As mentioned, Q24 in conducting prevents C22 from charging sufficiently to cause Q27 to come on, thus disabling the L side from firing as long as the L side is on. When the voltage level of the waveform goes off, back to L, Q23 goes off, Q24 goes off and Q25 comes on to reestablish the circuit. The waveform of FIG. 4 will, in the manner outlined, drive circuit 100 to produce an output from 108. The last bit of all messages is made to return the decoder to L, which assures preparation for the next message.

Referring back to FIGS. 14A-E the delay of 11 or so milliseconds due to the operation of C22 and C23 also operate to reduce spurious inputs. FIG. 148 shows a badly distorted L pulse. FIG. 14C shows the operation of C23 in charging to cut on Q28 responsive to the operation of 024 and Q25. As shown by the line above 0", C24 is partially charged. As soon as the input level exceeds the threshold of Q23 it cuts 024 on and 025 off and C23 charges to the threshold of Q28. 1f the spurious pulse of FIG. 14D occurs 023 will come on to cause Q24 to come on and Q25 to go off, but C23 will follow such and as soon as the transient drops to cut Q24 off the charge on C23 will drop to the half charge level.

Having now disclosed general and specific embodiments of our selective signalling system to enable its practice, the following claims are included to define what is asserted as the invention.

We claim:

1. A circuit for generating a message code comprised of a series of set and clear states made up of a series of distinct subseries of set and clear states comprising a register including a series of bistable stages capable of storing set and clear states, said stages being connected for serial transfer, first input means to inject a subseries in said register, translating means responsive to the output of said drive means operable to on and off conditions with said on condition effecting a repeated drive to said stages to transfer the states stored therein, first control means responsive to each operation of said first input means to actuate said drive means to the on condition and second control means to actuate said drive means to the off condition, second input means connected to a first subseries of stages in the first portion of said register, third input means connected to a stage adjacent to the first portion of said register, the said third input means operating to inject a tag bit in said register prior to the input of a message code, first output means connected to the first stage of each successive subsc 'ies of stages after the second and energized by the input of a set state, said first output means being connected to operate said second control means whereby following each input of a subseries the said register is caused to be driven to advance the subseries until said tag bit energizes the nest output means whereupon transfer is halted until the next input.

2. The encoder of claim 1 including means to input into said register a tag character leading the first message character and a stop character following the last character defining the calling code.

3. The encoder of claim 1 wherein said input means is operable to input an even number of set states for each character.

4. The encoder of claim 3 wherein the said input means is operable to set an even number of set states for each character and the means to input the tag and stop characters is connected to set stages defining such characters in an identical sense.

5. A decoder for use with a selective signalling system including a voltage source adapted to be connected to drive first and second pulse generators in response to an on-off voltage waveform representing a calling code, a plurality of bistable stages connected in series to be driven by said generators with each stage being capable of being driven to a set or clear condition, the said stages being connected to said generators in a pattern to provide a serial comparison of pulses produced by said generators to effect an advance of a set condition along said stages for one pattern and block the advance of a set condition for all other patterns whereby to provide a detect output signal for a proper calling code and no output signal for improper codes, means for clearing out said stages prior to the receipt of a message and means for setting the first stage at the receipt of a calling code, means responsive to said waveform to connect said source to drive one generator each time the voltage waveform goes on and to drive the other generator each time the voltage waveform goes off whereby to energize one or the other of said generators to provide pulse inputs to said stages in a given pattern, wherein there is included means responsive to the absence of a voltage level input to said decoder to drive the generator associated with the absence of a voltage level continuously between calling codes, wherein the said means for clearing out said stages includes means operable a given period of time after said voltage level has been absent to effect the clearing of said stages prior to the receipt of a calling code.

6. The decoder of claim wherein each said stage includes an input winding to drive said stage to a clear condition and the said pattern connection to said generators is made by a series of connectors linking certain of said stages of said generators to accomplish said pattern.

7. The decoder of claim 5 wherein there is included a separate connector means for connecting said stages to said generator in said pattern to provide said serial comparison of the pattern of pulses provided by said generators.

8. The decoder of claim 5 wherein there is included as part of such source a filter responsive to the presence of a tone input thereto and said on-off waveform is comprised of the presence of absence of said tone.

9. The decoder of claim 5 wherein there is included as a part of said source first and second filters each responsive to first and second tones and said on-off voltage waveform is comprised of the first and second tones representing on and off conditions.

10. In a selective signalling system the combination comprising an encoder for providing a calling code and a plurality of decoders, one for each calling code, the encoder including means to register a series of numbers as a given calling code and means responsive to registration of a complete calling code to translate said numbers into a waveform of given time duration comprised of a series of on or off voltage conditions, each decoder generator means responsive to said waveform to translate said condition into a series of on-off pulses, a register of bistable state stages coupled for serial transfer, means in each decoder responsive to said pulses to apply an advance drive to said stages to advance a given state therealong, and means in each register to effect a comparison of each pulse of said sequence with the sequence assigned to said decoder to permit the advance of a given state therealong to produce an output signal if said sequence is correct whereby each decoder or said system responds to said waveform but only one decoder further produces an output signal, wherein there is included means responsive to the absence of a voltage level input to said decoder to drive the generator associated with the absence of a voltage level continuously between calling codes, wherein the decoder includes means for clearing out said register a given period after the cessation of an on voltage condition.

11. The system of claim 10 wherein each decoder includes a plurality of connectors whereby to permit a change in the sequence of compared pulses to effectively change the code assigned to said decoder.

37 3 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,596,181 Dated July 27, 1971 Inventor(s) EDWARD CAMP DOWLING ET AL It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

fm Column 16, claim 1, line L Z, after "said" should be inserted shift register to produce an on and off waveform,

Same column, same claim, line 58, "nest" should be next Column 18, claim 8, line 2, "of" should be -R m or Same column, claim 10, line 15, after "decoder" should be inserted including Signed and sealed this 11th day of January 1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Air-testing; Officer Acting Commissioner of Patents

Claims

1. A circuit for generating a message code comprised of a series of set and clear states made up of a series of distinct subseries of set and clear states comprising a register including a series of bistable stages capable of storing Set and clear states, said stages being connected for serial transfer, first input means to inject a subseries in said register, translating means responsive to the output of said drive means operable to on and off conditions with said on condition effecting a repeated drive to said stages to transfer the states stored therein, first control means responsive to each operation of said first input means to actuate said drive means to the on condition and second control means to actuate said drive means to the off condition, second input means connected to a first subseries of stages in the first portion of said register, third input means connected to a stage adjacent to the first portion of said register, the said third input means operating to inject a tag bit in said register prior to the input of a message code, first output means connected to the first stage of each successive subseries of stages after the second and energized by the input of a set state, said first output means being connected to operate said second control means whereby following each input of a subseries the said register is caused to be driven to advance the subseries until said tag bit energizes the nest output means whereupon transfer is halted until the next input.

6. The decoder of claim 5 wherein each said stage includes an input winding to drive said stage to a clear condition and the said pattern connection to said generators is made by a series of connectors linking certain of said stages of said generators to accomplish said pattern.