US3449723A - Control system for interleave memory - Google Patents

Control system for interleave memory Download PDF

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Publication number
US3449723A
US3449723A US578744A US3449723DA US3449723A US 3449723 A US3449723 A US 3449723A US 578744 A US578744 A US 578744A US 3449723D A US3449723D A US 3449723DA US 3449723 A US3449723 A US 3449723A
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United States
Prior art keywords
control system
interleave memory
june
sheet
filed sept
Prior art date
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Expired - Lifetime
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US578744A
Inventor
David W Anderson
John V Mizzi
Francis J Sparacio
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Description

June 10, 1969 p, w. ANDERSON ETAL 3,449,723
CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12. 1966 Sheet I of 71 FIG. 1 FEXTENDED 111111 STORAGE L cm 1 1os 510111195 11m SELECTOR SELECTOR SELECTOR 551501011 WNW 011111 SEL'R SELR CHANNEL CHANNEL 0111mm CHANNEL OPERATORS sun sue CONSOLE 011111 011111 1 l 122 122 129 TAPE TAPE onuu 0111111 '09 VPRINTER cu cu cu cu cu J 128 F on PRINTER SWITCH nnuu mwu 0m 08 111111 STORE STORE CELL ago/P1111011 121 1 /1s5 51111150 FILE D151; DOUBLE CONNECTION m L 109 TAPE To OTHER ADAPTER 1 1111115 5151511 126 PRINTER M4 v 1o9 0011115011011 g PRINTER x325" Q c1110 mus msmv msmv ago/P1111011 cu cu urms 110 11s 5 11111111111 DISPLAY PRmTER 1/0 UNITS 109 011 1 111111511 MANUAL 1/0 108 INVENTORS c1110 11111111 w. ANDERSON READ/PUNCH 101111 1 111221 FRANCIS .1 SPARACIO ATTORNEY June 1969 D. w. ANDERSON ETAL 3, 4 ,7
CQNTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 Sheet 2 of 71 MAIN E sroms g m 434 I E PSCE 1 mm n cE SPF l km STORAGE mum 439 cousou OPERATORS CONSOLE June 1969 o. w. ANDERSON ETAL 3,449,723
CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 Sheet 3 of '21 FIG. 3
104 105 l "Am /3 EXTENDED 138 STORAGE SPF aroma 061 A81 081 AB! 1%}, CLZB cm w ma cus TOI/O P565 umrs 1s: 1 E BOX I l l 143 I new I I cm men I BOX DB I CW (FXPU) 'c s i I 134/ 1024 1 031 I ms BITS I cuss I 191 I I I mums POINT ans T (mu) I CONSOLE M6 BIS L I 081 CL28 }ro SELECTUR H u 1 cm 0 A NEL 22 June 10, 1969 o. w. ANDERSON ETAL 3,449,723
CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 Sheet 4 of 71 I BOX I R TEMP 44- 4 x 45 TEMP 447 4 I48 4 450 4 4 .4 HII 44451 BUF ER 4+0 I BB LI REG LB I I 454 452 45:4 44451 BUFFER 44-4 4 4 4 IBBRFRFBT] IIUURFREUI IUIURFREBI INST BUFFEII 4+4 44m BUFFER 445 i i i i i i 45B IP-I 444s1 BUFFER 444 4 I I I I 4444 I OPERATING 44cc L T T T T 464 MIR-IR L 4 4 4 I M I T I I 4 1 SELECT T T 7g? T 1 I GPR 460/ l 1 AI F 466 UP D 467 DECODE 424 444454 T I 22 40 FXOS CONTROLS T I 483 TOFXOS I I I I I I I I I I I I 44451 BUFFER 4+6 BLCTR Us I I I I I I I I I I I I June 10, 1969 D. w. ANDERSON ETAL CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 Sheet an is: 2 \lUiT 2;; 2: [L2 EE x B T 5:133
in? @U QQFA| 1H? N lHT rAl II E 222% xom H :2: m: 3585 2 4 :2: P3. 2. 5:: Q mi 2 June 10, 1969 w. ANDERSON ETAL 3,449,723
CONTROL SYSTEM FOR INTERLEAVE MEMORY Sheet Filed Sept. 12, 1966 FIG. 6A
199 FROM mu 142{ 550 I111 1111 [III I BOX S 123 5 0 W W m II a M R FROM I Box DIRECI REG T0 PSCE 157 DIRECT IN BUS DATA REG T0 PSCE 137 DECREIENT 1 TO I BOX 512 BITS cva DECODE 412 2s4 June 10, 1969 w. ANDERSON ETAL 3,449,723
CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12. 1966 Sheet of 21 FIG. 6B
11 BUS// 412 25s 10111250540111 115001111; IRER l 1 511111105 DECODE r 020005 1STORE Bus .150 05 050002 1 1 I F101 221 K 311 CODE FROM 0 100x134 To STORE 22 511121211 DATA BUFFERS 244 $2111 32 FORCE 0515mm" LEFT 0R RIGHT DECIML SIG" June 10, 1969 w. ANDERSON ETAL 3,449,723
CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 Sheet m of '21 FIG. 8 MPXR CHNL 131-\ 10s 122 I Psc 260 I l s EL n O I soc I CHM I MSCE M s I 104 I l J I I I 261 262 BC I CPU SELR Ii CHNI. I Sc I 122 EMS \105 FIG. 9 26th I x 266 I CCCINIFCE I BUS CONTROL I use I I- .I CPU I 268 269 215 15 I F" CPU I I I I 550 I EMS INI 264\ I 240 3A3 I 240 HOUSE- IIUEUE 5A8 I KEEPING PRIORITY 272 550 I 1s5 OUEUE I m I cm cm EMS m I 265 (MARK) EMS REG BUS I I 210 I IA BUS I I I MSCE I RU IcccmrFcE :2 A l H E; 1 5% 22 22 Sheet 2 D. W. ANDERSON ETAL CONTROL SYSTEM FOR INTERLEAVE MEMORY M a: o 358 o E w 358 E 1 x; H Q? w an s: v 1" M J .I|\( J a a Q 0 2 O m E 3+ 556%. wzimoz, 556mm 953 Ema: V
l 1 IL r W June 10, 1969 Filed Sept. 12, 1966 D.W.ANDERSON ETAL 3,449,723
CONTROL SYSTEM FOR INTERLEAVE MEMORY Sheet /3 of 71 V T W 1 q 3 102559 v.5: 1 2 k z .w hww Q; o w 5 JITILE W 2:30: :2. o SE28 X: H E w E E HMNZ L m $231 FEZB wmnaP x25 0 i; 1 5 E C s V l H I. I 5 Q3 2 a? a Q: am H \22 June 10, 1969 Filed Sept. 12. 1966 mm: 6E 52 June 10, 1969 o. w. ANDERSON ETAL 3,449,733
CONTRQL SYSTEM FOR INTERLEAVE MEMQRY Sheet 4 of 71 Filed Sept. 12, 1966 E: 213 m $2. a: 22% A 1 o M $3 mo Mani mo E s: Q E it an I J J 7 22 4 M L w mo 3: M 1183; as 7 M mm: 23 \EQ M .T. a: 25; 22 E. M J M as 5 M E\ mm? g2; mm o aw m x r mo: e: as: w 22 i a: (I EE 05 2e 22 ts 1 E W wurs q w M DE 5 22K 151 n 2: U 2 1 W NW3 WW mo m5 8% o a: M 25%; 2: E5 k mo 5: a: W 02 E 2o: 5:: E N 2: I. N 65 E H 2: 1 $55; a2 a2 a: :01: H H mo :5 2 OSJ *J E 81 ff] E2 1 %5 :21 iii? w a: z E -27 5: $2 $3 'L W 1 0% 0O 07* as June 10, 1969 n. w. ANDERSON ETAL 3,449,723
CONTROL SYSTEM FOR INTERLEAVE MEMORY Sheet of 71 Filed Sept. 12. 1966 June 10, 1969 o. w. ANDERSON ETAL 3,449,723
CONTROL SYSTEM FOR INTERLEAVE MEMORY Filed Sept. 12, 1966 Sheet June 10, 1969 o, w. ANDERSON ETAL 3,449,723
CONTRQL SYSTEM FOR INTERLEAVE MEMORY Sheet Filed Sept. 12. 1966 @2 v E 02;: E E 5 ME an a; 2 2m 2 2w 2 2w 2 \2; Mia 31 :3 :2: 8m :5 :2: N2 :3 =2: 2 E0 12: a: $7 $2? ET A J E -v Z x: Z 5; N; E 5 m: a: $3 2 225 2. 2 is; E 2 225 m: 2 z: 28 me 25 20% Q; 32 0; :3: L $32: wt V fi KO GO gm? GO m 32A- E0 How 01 wmqw Z 5: \5: is: QE E 11 :2 L o E E mo /1 m0 /1 m0 mo 33/ wwc 2w .11 h I. a: 2mm 3: 5mm 51 t 2Z2 \33 \m 3: $2 1& n 2 5 :3 EW 2:3 :2 was "r02 0: I 2 F L mo RN 5; a /1 0 /1 IO IO E0 $2 $2 $2 w 41 i H z: 0: :2 $2 ma: 2: Q N 2m 52 22 m 3 is =8 30;: 1 2m 2 mo I. M 5w 5 L L .51 Q mo mo mo W1 mo :2 T1 M L 2. ME 32 2: m2: 8: as 21 E n ma June 10, 1969 w. ANDERSON ETAL 3,449,723
CQNTROL SYSTEM FOR INTERLEAVE MEMORY Sheet of 71 Filed Sept. 12, 1966 w fi fl f 1 1% i113? :2 N 0 2 z 3 3: A m m T J5 mo 1.8m A M i M H; $8 N j 32 2f .5 :25! ET K22 M Q28 2: 58 53 h E0 QM-022d Y(EON a i q a A M F Th 22 as m M mo W U W a v M u E. \i as W a M a: wlrlifiillii r 5 2 u 5? w E If M A 2:22: S Effi r M 35 $592 V W W H M9205 w E 1 mm i 3025mm: 5 M 5 ii W a w :2 n 1 1 f mow q 2? W T: p i t E T I l A "Fl 1n x I 1 yf\l\ x {I H m is E E l3 an. ({llllhlkll\ J2 ma 5! 022
US578744A 1966-09-12 1966-09-12 Control system for interleave memory Expired - Lifetime US3449723A (en)

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US57874566A 1966-09-12 1966-09-12
US57874466A 1966-09-12 1966-09-12

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DE (1) DE1549479B1 (en)
FR (1) FR1538070A (en)
GB (1) GB1151041A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699530A (en) * 1970-12-30 1972-10-17 Ibm Input/output system with dedicated channel buffering
US3918031A (en) * 1971-10-26 1975-11-04 Texas Instruments Inc Dual mode bulk memory extension system for a data processing
EP0232827A2 (en) * 1986-02-04 1987-08-19 Hitachi, Ltd. Vector processor
US4729093A (en) * 1984-09-26 1988-03-01 Motorola, Inc. Microcomputer which prioritizes instruction prefetch requests and data operand requests
US5278800A (en) * 1991-10-31 1994-01-11 International Business Machines Corporation Memory system and unique memory chip allowing island interlace
US5692121A (en) * 1995-04-14 1997-11-25 International Business Machines Corporation Recovery unit for mirrored processors
US5701434A (en) * 1995-03-16 1997-12-23 Hitachi, Ltd. Interleave memory controller with a common access queue

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3638198A (en) * 1969-07-09 1972-01-25 Burroughs Corp Priority resolution network for input/output exchange
US3593315A (en) * 1969-09-17 1971-07-13 Burroughs Corp Method and apparatus for deallocating small memory spaces assigned to a computer program
US3694074A (en) * 1970-03-05 1972-09-26 Robert W Huboi Photographic printing system
US4048623A (en) * 1974-09-25 1977-09-13 Data General Corporation Data processing system
US4176394A (en) * 1977-06-13 1979-11-27 Sperry Rand Corporation Apparatus for maintaining a history of the most recently executed instructions in a digital computer
US4228500A (en) * 1978-03-27 1980-10-14 Honeywell Information Systems Inc. Command stacking apparatus for use in a memory controller
US4707781A (en) * 1979-01-09 1987-11-17 Chopp Computer Corp. Shared memory computer method and apparatus
WO1980001421A1 (en) * 1979-01-09 1980-07-10 Sullivan Computer Shared memory computer method and apparatus
US4484262A (en) * 1979-01-09 1984-11-20 Sullivan Herbert W Shared memory computer method and apparatus
US4541045A (en) * 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
GB8401804D0 (en) * 1984-01-24 1984-02-29 Int Computers Ltd Data storage apparatus
AU553416B2 (en) * 1984-02-24 1986-07-17 Fujitsu Limited Pipeline processing
US4805098A (en) * 1986-05-05 1989-02-14 Mips Computer Systems, Inc. Write buffer
JPH0631957B2 (en) * 1987-02-06 1994-04-27 ヤマハ株式会社 Electronic musical instrument
US4953079A (en) * 1988-03-24 1990-08-28 Gould Inc. Cache memory address modifier for dynamic alteration of cache block fetch sequence
US5325523A (en) * 1991-04-10 1994-06-28 International Business Machines Corporation Method for deleting objects from library resident optical disks by accumulating pending delete requests
US20080189479A1 (en) * 2007-02-02 2008-08-07 Sigmatel, Inc. Device, system and method for controlling memory operations

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3029414A (en) * 1958-08-11 1962-04-10 Honeywell Regulator Co Information handling apparatus
US3061192A (en) * 1958-08-18 1962-10-30 Sylvania Electric Prod Data processing system
US3200380A (en) * 1961-02-16 1965-08-10 Burroughs Corp Data processing system
US3242467A (en) * 1960-06-07 1966-03-22 Ibm Temporary storage register
US3312943A (en) * 1963-02-28 1967-04-04 Westinghouse Electric Corp Computer organization

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE26087E (en) * 1959-12-30 1966-09-20 Multi-computer system including multiplexed memories. lookahead, and address interleaving features
US3234524A (en) * 1962-05-28 1966-02-08 Ibm Push-down memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3029414A (en) * 1958-08-11 1962-04-10 Honeywell Regulator Co Information handling apparatus
US3061192A (en) * 1958-08-18 1962-10-30 Sylvania Electric Prod Data processing system
US3242467A (en) * 1960-06-07 1966-03-22 Ibm Temporary storage register
US3200380A (en) * 1961-02-16 1965-08-10 Burroughs Corp Data processing system
US3312943A (en) * 1963-02-28 1967-04-04 Westinghouse Electric Corp Computer organization

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699530A (en) * 1970-12-30 1972-10-17 Ibm Input/output system with dedicated channel buffering
US3918031A (en) * 1971-10-26 1975-11-04 Texas Instruments Inc Dual mode bulk memory extension system for a data processing
US4729093A (en) * 1984-09-26 1988-03-01 Motorola, Inc. Microcomputer which prioritizes instruction prefetch requests and data operand requests
EP0232827A2 (en) * 1986-02-04 1987-08-19 Hitachi, Ltd. Vector processor
EP0232827A3 (en) * 1986-02-04 1989-11-29 Hitachi, Ltd. Vector processor
US5278800A (en) * 1991-10-31 1994-01-11 International Business Machines Corporation Memory system and unique memory chip allowing island interlace
US5701434A (en) * 1995-03-16 1997-12-23 Hitachi, Ltd. Interleave memory controller with a common access queue
US5692121A (en) * 1995-04-14 1997-11-25 International Business Machines Corporation Recovery unit for mirrored processors

Also Published As

Publication number Publication date
US3449724A (en) 1969-06-10
FR1538070A (en) 1968-08-30
DE1549479B1 (en) 1971-06-03
GB1151041A (en) 1969-05-07

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