US20150357274A1 - Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV - Google Patents

Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV Download PDF

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US20150357274A1
US20150357274A1 US14/832,644 US201514832644A US2015357274A1 US 20150357274 A1 US20150357274 A1 US 20150357274A1 US 201514832644 A US201514832644 A US 201514832644A US 2015357274 A1 US2015357274 A1 US 2015357274A1
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substrate
semiconductor die
encapsulant
semiconductor device
conductive
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US14/832,644
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Daesik Choi
Young Jin Woo
Taewoo Lee
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Priority to US14/832,644 priority Critical patent/US20150357274A1/en
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Definitions

  • the present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a vertical interconnect using TSV and TMV in fan-out wafer level chip scale package (Fo-WLCSP).
  • Fo-WLCSP fan-out wafer level chip scale package
  • Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
  • LED light emitting diode
  • MOSFET power metal oxide semiconductor field effect transistor
  • Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays.
  • Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
  • Semiconductor devices exploit the electrical properties of semiconductor materials.
  • the atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
  • a semiconductor device contains active and passive electrical structures.
  • Active structures including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current.
  • Passive structures including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions.
  • the passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
  • Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components.
  • Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
  • One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products.
  • a smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
  • a conventional Fo-WLCSP contains a flipchip semiconductor die and encapsulant formed over the semiconductor die.
  • An interconnect structure is typically formed over the semiconductor die and encapsulant for z-direction vertical interconnect.
  • the flipchip semiconductor die is electrically connected to the interconnect structure with bumps.
  • the bump interconnect makes package stacking difficult to achieve.
  • the bumps are susceptible to delamination, particularly for applications requiring a fine interconnect pitch.
  • Another Fo-WLCSP interconnect structure is shown in U.S. Pat. No. 7,528,009 ('009 patent).
  • a portion of the bottom silicon layer is removed between adjacent semiconductor die.
  • An insulating layer is formed in the removed silicon area.
  • a portion of the insulating layer is removed and an electrically conductive material is deposited to form a relatively large z-direction electrical interconnect for the semiconductor die.
  • the large interconnect structure described in the '009 patent increases the pitch of the interconnect and size of the package, which is counter to general miniaturization demands.
  • the present invention is a semiconductor device comprising a substrate separated from a substrate panel.
  • the substrate includes a first surface and a second surface opposite the first surface.
  • a first semiconductor die is disposed over the first surface of the substrate.
  • An encapsulant is deposited over the first semiconductor die and the first surface of the substrate to leave a peripheral ring of the encapsulant around an outer edge of the substrate after singulation through the encapsulant.
  • An interconnect structure is formed over the second surface of the substrate.
  • the present invention is a semiconductor device comprising a substrate including a first surface and a second surface opposite the first surface.
  • a first semiconductor die is disposed over the first surface of the substrate.
  • An encapsulant is deposited over the first semiconductor die and the first surface of the substrate to form an encapsulated assembly with the encapsulant disposed around an outer edge of the substrate.
  • the present invention is a semiconductor device comprising a first substrate separated from a substrate panel.
  • a second substrate is separated from the first substrate by a space.
  • a first semiconductor die is disposed over the first substrate.
  • An encapsulant is deposited over the first semiconductor die and in the space between the first and second substrates with the encapsulant disposed over an outer edge of the first and second substrates.
  • the present invention is a semiconductor device comprising a substrate separated from a substrate panel.
  • a semiconductor die is disposed over the substrate.
  • An encapsulant is deposited over the semiconductor die with the encapsulant disposed around an outer edge of the substrate.
  • FIG. 1 illustrates a PCB with different types of packages mounted to its surface
  • FIGS. 2 a - 2 c illustrate further detail of the representative semiconductor packages mounted to the PCB
  • FIGS. 3 a - 3 j illustrate a process of forming a vertical interconnect structure using TSV and TMV in a Fo-WLCSP
  • FIG. 4 illustrates the Fo-WLCSP with a TSV and TMV vertical interconnect structure
  • FIG. 5 illustrates stacked Fo-WLCSP each with a TSV and TMV vertical interconnect structure
  • FIG. 6 illustrates another embodiment of stacked Fo-WLCSP each with a TSV and TMV vertical interconnect structure
  • FIG. 7 illustrates the Fo-WLCSP with a TMV formed in the encapsulant channel
  • FIG. 8 illustrates tiered stacking of different size Fo-WLCSP each with a TSV and TMV vertical interconnect structure
  • FIG. 9 illustrates stacking of same size Fo-WLCSP each with a TSV and TMV vertical interconnect structure
  • FIG. 10 illustrates stacking Fo-WLCSP on opposite sides of TSV wafer.
  • FIG. 11 illustrates stacking an ISM and Fo-WLCSP with a TSV and TMV vertical interconnect structure.
  • Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer.
  • Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits.
  • Active electrical components such as transistors and diodes, have the ability to control the flow of electrical current.
  • Passive electrical components such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.
  • Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization.
  • Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion.
  • the doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current.
  • Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.
  • Active and passive components are formed by layers of materials with different electrical properties.
  • the layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • electrolytic plating electroless plating processes.
  • Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.
  • the layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned.
  • a pattern is transferred from a photomask to the photoresist using light.
  • the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned.
  • the remainder of the photoresist is removed, leaving behind a patterned layer.
  • some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.
  • Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.
  • Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
  • the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes.
  • the wafer is singulated using a laser cutting tool or saw blade.
  • the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components.
  • Contact pads formed over the semiconductor die are then connected to contact pads within the package.
  • the electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds.
  • An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation.
  • the finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
  • FIG. 1 illustrates electronic device 50 having a chip carrier substrate or printed circuit board (PCB) 52 with a plurality of semiconductor packages mounted on its surface.
  • Electronic device 50 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in FIG. 1 for purposes of illustration.
  • Electronic device 50 may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions.
  • electronic device 50 may be a subcomponent of a larger system.
  • electronic device 50 may be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device.
  • PDA personal digital assistant
  • DVC digital video camera
  • electronic device 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer.
  • the semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.
  • ASIC application specific integrated circuits
  • the miniaturization and the weight reduction are essential for these products to be accepted by the market.
  • the distance between semiconductor devices must be decreased to achieve higher density.
  • PCB 52 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB.
  • Conductive signal traces 54 are formed over a surface or within layers of PCB 52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 54 also provide power and ground connections to each of the semiconductor packages.
  • a semiconductor device has two packaging levels.
  • First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier.
  • Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB.
  • a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
  • first level packaging including wire bond package 56 and flip chip 58
  • second level packaging including ball grid array (BGA) 60 , bump chip carrier (BCC) 62 , dual in-line package (DIP) 64 , land grid array (LGA) 66 , multi-chip module (MCM) 68 , quad flat non-leaded package (QFN) 70 , and quad flat package 72 .
  • BGA ball grid array
  • BCC bump chip carrier
  • DIP dual in-line package
  • LGA land grid array
  • MCM multi-chip module
  • QFN quad flat non-leaded package
  • quad flat package 72 quad flat package
  • electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages.
  • manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
  • FIGS. 2 a - 2 c show exemplary semiconductor packages.
  • FIG. 2 a illustrates further detail of DIP 64 mounted on PCB 52 .
  • Semiconductor die 74 includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die.
  • the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die 74 .
  • Contact pads 76 are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die 74 .
  • semiconductor die 74 is mounted to an intermediate carrier 78 using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin.
  • the package body includes an insulative packaging material such as polymer or ceramic.
  • Conductor leads 80 and wire bonds 82 provide electrical interconnect between semiconductor die 74 and PCB 52 .
  • Encapsulant 84 is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die 74 or wire bonds 82 .
  • FIG. 2 b illustrates further detail of BCC 62 mounted on PCB 52 .
  • Semiconductor die 88 is mounted over carrier 90 using an underfill or epoxy-resin adhesive material 92 .
  • Wire bonds 94 provide first level packaging interconnect between contact pads 96 and 98 .
  • Molding compound or encapsulant 100 is deposited over semiconductor die 88 and wire bonds 94 to provide physical support and electrical isolation for the device.
  • Contact pads 102 are formed over a surface of PCB 52 using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation.
  • Contact pads 102 are electrically connected to one or more conductive signal traces 54 in PCB 52 .
  • Bumps 104 are formed between contact pads 98 of BCC 62 and contact pads 102 of PCB 52 .
  • semiconductor die 58 is mounted face down to intermediate carrier 106 with a flip chip style first level packaging.
  • Active region 108 of semiconductor die 58 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die.
  • the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region 108 .
  • Semiconductor die 58 is electrically and mechanically connected to carrier 106 through bumps 110 .
  • BGA 60 is electrically and mechanically connected to PCB 52 with a BGA style second level packaging using bumps 112 .
  • Semiconductor die 58 is electrically connected to conductive signal traces 54 in PCB 52 through bumps 110 , signal lines 114 , and bumps 112 .
  • a molding compound or encapsulant 116 is deposited over semiconductor die 58 and carrier 106 to provide physical support and electrical isolation for the device.
  • the flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die 58 to conduction tracks on PCB 52 in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance.
  • the semiconductor die 58 can be mechanically and electrically connected directly to PCB 52 using flip chip style first level packaging without intermediate carrier 106 .
  • FIGS. 3 a - 3 j illustrate, in relation to FIGS. 1 and 2 a - 2 c , a process of forming a vertical interconnect structure using TSV and TMV in a Fo-WLCSP.
  • a substrate or carrier 120 contains temporary or sacrificial base material such as silicon, polymer, polymer composite, metal, ceramic, glass, glass epoxy, beryllium oxide, or other suitable low-cost, rigid material for structural support.
  • a semiconductor wafer 122 contains a base substrate material, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support.
  • a plurality of vias is formed through semiconductor wafer 122 using mechanical drilling, laser drilling, or deep reactive ion etching (DRIE).
  • the vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction conductive through silicon vias (TSV) 124 .
  • TSV wafer 122 - 124 is mounted to carrier 120 , as shown in FIG. 3 b.
  • a channel 126 is cut through semiconductor wafer 122 down to carrier 120 using saw blade or laser cutting tool 127 to create a plurality of TSV wafer portions or segments 128 .
  • semiconductor die 130 has an active surface 132 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
  • the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 132 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit.
  • DSP digital signal processor
  • Semiconductor die 130 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.
  • semiconductor die 130 is a flipchip type semiconductor die.
  • An electrically conductive layer 134 is formed over active surface 132 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process.
  • Conductive layer 134 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • Conductive layer 134 operates as contact pads electrically connected to the circuits on active surface 132 .
  • Semiconductor die 130 are mounted to TSV wafer segments 128 with die attach adhesive 136 .
  • Semiconductor die 130 each have smaller footprint than TSV wafer segment 128 . Accordingly, TSV 124 a around a perimeter of wafer segment 128 are outside the footprint of semiconductor die 130 and the remaining TSV 124 b are disposed under semiconductor die 130 .
  • an encapsulant or molding compound 140 is deposited over carrier 120 , semiconductor die 130 , and TSV wafer segments 128 , including into channel 126 , using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
  • Encapsulant 140 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 140 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • a plurality of vias 142 is formed through encapsulant 140 over TSV 124 a and contact pads 134 using mechanical drilling, laser drilling, mold chase, or DRIE.
  • the vias 142 are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive through mold vias or pillars (TMV) 144 , as shown in FIG. 3 g .
  • Conductive TMV 144 a are electrically connected to TSV 124 a
  • conductive TMV 144 b are electrically connected to contact pads 134 .
  • the formation of vias 142 and fill with conductive material to form conductive TMV 144 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • an electrically conductive layer or redistribution layer (RDL) 146 is formed over encapsulant 140 and conductive TMV 144 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process.
  • Conductive layer 146 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • Conductive layer 146 is electrically connected to conductive TMV 144 a and 144 b .
  • Additional RDL 146 can be formed over encapsulant 140 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 130 .
  • an insulating or passivation layer 148 is formed over encapsulant 140 and conductive layer 146 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation.
  • the insulating layer 148 can be one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties.
  • a portion of insulating layer 148 is removed by an etching process to expose conductive layer 146 for bump formation or external electrical interconnect.
  • carrier 120 is removed by chemical etching, mechanical peel-off, CMP, mechanical grinding, thermal bake, laser scanning, wet stripping, UV light, or heat.
  • An electrically conductive bump material is deposited over the exposed conductive layer 146 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process.
  • the bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution.
  • the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder.
  • the bump material is bonded to conductive layer 146 using a suitable attachment or bonding process.
  • the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps 150 .
  • bumps 150 are reflowed a second time to improve electrical contact to conductive layer 146 .
  • An under bumps metallization (UBM) can be formed under bumps 150 .
  • the bumps can also be compression bonded to conductive layer 146 .
  • Bumps 150 represent one type of interconnect structure that can be formed over conductive layer 146 .
  • the interconnect structure can also use bond wires, stud bump, micro bump, or other electrical interconnect.
  • Semiconductor die 130 and encapsulant 140 is singulated using saw blade or laser cutting tool 152 to separate the individual semiconductor die 130 into Fo-WLCSP 154 , as shown in FIG. 4 .
  • Semiconductor die 130 is electrically connected to conductive TMV 144 a and 144 b , conductive layer 146 , and conductive TSV 124 a and 124 b in wafer segment 128 .
  • TSV 124 a and 124 b can be electrically common or electrically isolated depending on the design and function of semiconductor die 130 .
  • the combination of conductive TSV 124 and conductive TMV 144 provide a fine pitch z-direction electrical interconnect for semiconductor die 130 , which reduces the size of Fo-WLCSP 154 .
  • TSV wafer segment 128 has a CTE similar to semiconductor die 130 to reduce thermal stress.
  • Fo-WLCSP 154 is suitable for package-on-package (PoP) or package-in-package (PiP) applications.
  • FIG. 5 shows Fo-WLCSP 156 configured similar to Fo-WLCSP 154 .
  • Fo-WLCSP 156 is stacked over Fo-WLCSP 154 and electrically connected with bumps 158 formed between conductive layer 146 of Fo-WLCSP 154 and TSV 124 a of Fo-WLCSP 156 .
  • semiconductor die 130 in Fo-WLCSP 154 and 156 are electrically connected through conductive TSV 124 , TMV 144 , conductive layer 146 , and bumps 158 .
  • FIG. 6 shows an embodiment of Fo-WLCSP 159 , similar to FIG. 4 , with semiconductor die 160 mounted over insulating layer 148 with die attach adhesive 162 .
  • the stacked semiconductor die 130 and 160 increase the functional density of Fo-WLCSP 159 .
  • Semiconductor die 160 has an active surface 164 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
  • the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 164 to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit.
  • Semiconductor die 160 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.
  • Contact pads 166 are formed on active surface 164 and electrically connected to the circuits on the active surface.
  • Encapsulant or molding compound 170 is deposited over semiconductor die 160 and insulating layer 148 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
  • Encapsulant 170 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.
  • Encapsulant 170 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • An electrically conductive layer or RDL 174 is formed over encapsulant 170 and conductive TMV 172 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process.
  • Conductive layer 174 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • Conductive layer 174 is electrically connected to conductive TMV 172 a and 172 b .
  • Additional RDL 174 can be formed over encapsulant 170 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 160 .
  • An insulating or passivation layer 176 is formed over encapsulant 170 and conductive layer 174 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation.
  • the insulating layer 176 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.
  • a portion of insulating layer 176 is removed by an etching process to expose conductive layer 174 for bump formation or external electrical interconnect.
  • Semiconductor die 130 and 160 are electrically connected through conductive TMV 144 , TMV 172 , TSV 124 , and conductive layers 146 and 174 .
  • FIG. 7 shows an embodiment of Fo-WLCSP 180 , similar to FIG. 4 , with conductive TMV 182 formed through encapsulant 140 in channel 126 between TSV wafer segments 128 . A portion of insulating layer 148 is removed by an etching process to expose conductive TMV 182 for bump formation or external electrical interconnect.
  • FIG. 8 shows an embodiment of Fo-WLCSP 188 , continuing from FIG. 3 d , with semiconductor die 190 mounted over semiconductor die 130 with die attach adhesive 192 .
  • Semiconductor die 130 and 190 are different in size and therefore stacked in a tiered arrangement.
  • the tiered semiconductor die 130 and 190 increase the functional density of Fo-WLCSP 188 .
  • Semiconductor die 190 has an active surface 194 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
  • the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 194 to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit.
  • Semiconductor die 190 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.
  • Contact pads 196 are formed on active surface 194 and electrically connected to the circuits on the active surface.
  • Encapsulant or molding compound 200 is deposited over semiconductor die 130 and 190 and TSV wafer segment 128 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
  • Encapsulant 200 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.
  • Encapsulant 200 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • a plurality of vias is formed through encapsulant 200 down to contact pads 134 and 196 and TSV 124 a using mechanical drilling, laser drilling, mold chase, or DRIE.
  • the vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive TMV 202 .
  • Conductive TMV 202 a are electrically connected to contact pads 196
  • conductive TMV 202 b are electrically connected to contact pads 134
  • conductive TMV 202 c are electrically connected to TSV 124 a .
  • the formation of vias and fill with conductive material to form conductive TMV 202 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • An electrically conductive layer or RDL 204 is formed over encapsulant 200 and conductive TMV 202 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process.
  • Conductive layer 204 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • Conductive layer 204 is electrically connected to conductive TMV 202 a and 202 b .
  • Additional RDL 204 can be formed over encapsulant 200 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 130 and 190 .
  • An insulating or passivation layer 206 is formed over encapsulant 200 and conductive layer 204 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation.
  • the insulating layer 206 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.
  • a portion of insulating layer 206 is removed by an etching process to expose conductive layer 204 and conductive vias 202 c for bump formation or external electrical interconnect.
  • Semiconductor die 130 and 190 are electrically connected through conductive TMV 202 , TSV 124 , and conductive layer 204 .
  • a plurality of bumps 207 is formed over TSV 124 a and 124 b.
  • FIG. 9 shows an embodiment of Fo-WLCSP 208 , continuing from FIG. 3 c , with semiconductor die 210 mounted over TSV wafer segment 128 .
  • semiconductor die 210 is a flipchip type semiconductor die with bumps 212 formed between contact pads 216 and TSV 124 b .
  • Contact pads 216 are formed on active surface 214 and electrically connected to the circuits on the active surface.
  • Semiconductor die 220 is mounted back-to-back with semiconductor die 210 with die attach adhesive 222 .
  • Semiconductor die 210 and 220 are similar in size. The stacked semiconductor die 210 and 220 increase the functional density of Fo-WLCSP 208 .
  • Contact pads 226 are formed on active surface 224 of semiconductor die 220 and electrically connected to the circuits on the active surface.
  • Semiconductor die 210 and 220 each have an active surface containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
  • the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit.
  • IPDs such as inductors, capacitors, and resistors, for RF signal processing.
  • An encapsulant or molding compound 230 is deposited over semiconductor die 210 and 220 and TSV wafer segment 128 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
  • Encapsulant 230 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.
  • Encapsulant 230 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • a plurality of vias is formed through encapsulant 230 down to contact pads 226 and TSV 124 a using mechanical drilling, laser drilling, mold chase, or DRIE.
  • the vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive TMV 232 .
  • Conductive TMV 232 a are electrically connected to contact pads 226 and conductive TMV 232 b are electrically connected to TSV 124 a .
  • the formation of vias and fill with conductive material to form conductive TMV 232 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • An electrically conductive layer or RDL 234 is formed over encapsulant 230 and conductive TMV 232 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process.
  • Conductive layer 234 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • Conductive layer 234 is electrically connected to conductive TMV 232 a and 232 b .
  • Additional RDL 234 can be formed over encapsulant 230 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 210 and 220 .
  • An insulating or passivation layer 236 is formed over encapsulant 230 and conductive layer 234 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation.
  • the insulating layer 236 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.
  • a portion of insulating layer 236 is removed by an etching process to expose conductive layer 234 for bump formation or external electrical interconnect.
  • Semiconductor die 210 and 220 are electrically connected through conductive TMV 232 , TSV 124 , and conductive layer 234 .
  • a plurality of bumps 238 is formed over TSV 124 a and 124 b.
  • FIG. 10 shows an embodiment of Fo-WLCSP 240 , continuing from FIG. 3 c , with semiconductor die 242 mounted over surface 244 of TSV wafer segment 128 with die attach adhesive layer 246 .
  • Contact pads 248 are formed on active surface 250 of semiconductor die 242 and electrically connected to the circuits on the active surface.
  • Semiconductor die 252 is mounted over surface 254 of TSV wafer segment 128 , opposite surface 244 , with die attach adhesive layer 256 .
  • Contact pads 258 are formed on active surface 260 of semiconductor die 252 and electrically connected to the circuits on the active surface.
  • the semiconductor die 242 and 252 stacked on opposite surfaces 244 and 254 of TSV wafer segment 128 increase the functional density of Fo-WLCSP 240 .
  • Semiconductor die 242 and 252 each have an active surface containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die.
  • the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit.
  • semiconductor die 242 and 252 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.
  • An encapsulant or molding compound 262 is deposited over semiconductor die 242 and 252 and surfaces 244 and 254 of TSV wafer segment 128 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
  • Encapsulant 262 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.
  • Encapsulant 262 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • a plurality of vias is formed through encapsulant 262 down to contact pads 248 and 258 and both sides of TSV 124 a using mechanical drilling, laser drilling, mold chase, or DRIE.
  • the vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive TMV 264 and 266 .
  • Conductive TMV 264 a are electrically connected to contact pads 248 and conductive TMV 264 b are electrically connected to one side of TSV 124 a .
  • Conductive TMV 266 a are electrically connected to contact pads 258 and conductive TMV 266 b are electrically connected to an opposite side of TSV 124 a .
  • the formation of vias and fill with conductive material to form conductive TMV 264 and 266 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • An electrically conductive layer or RDL 268 is formed over encapsulant 262 and conductive TMV 264 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process.
  • Conductive layer 268 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.
  • Conductive layer 268 is electrically connected to conductive TMV 264 a and 264 b .
  • Additional RDL 268 can be formed over encapsulant 262 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 242 and 252 .
  • An insulating or passivation layer 270 is formed over encapsulant 262 and conductive layer 268 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation.
  • the insulating layer 270 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.
  • a portion of insulating layer 270 is removed by an etching process to expose conductive layer 268 for bump formation or external electrical interconnect.
  • Semiconductor die 242 and 252 are electrically connected through conductive TMV 264 , TMV 266 , TSV 124 , and conductive layer 268 .
  • a plurality of bumps 272 is formed over TMV 266 a and 266 b.
  • FIG. 11 shows an embodiment of Fo-WLCSP 280 , continuing from FIG. 3 c , with semiconductor die 282 mounted over TSV wafer segment 128 with bumps 284 .
  • semiconductor die 282 is a flipchip type semiconductor die with bumps 284 formed between contact pads 288 and TSV 124 b .
  • Contact pads 288 are formed on active surface 286 and electrically connected to the circuits on the active surface.
  • An internal stacking module (ISM) 290 is mounted to a back surface of semiconductor die 282 with die attach adhesive 291 .
  • ISM 290 contains semiconductor die 292 mounted to substrate 294 and electrically connected to conductive layers 295 in the substrate with bond wires 296 .
  • An encapsulant 298 is deposited over semiconductor die 292 , substrate 294 , and bond wires 296 .
  • An encapsulant or molding compound 300 is deposited over semiconductor die 282 , ISM 290 , and TSV wafer segment 128 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator.
  • Encapsulant 300 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.
  • Encapsulant 300 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • a plurality of vias is formed through encapsulant 300 down to TSV 124 a using mechanical drilling, laser drilling, mold chase, or DRIE.
  • the vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive TMV 302 .
  • Conductive TMV 302 are electrically connected to TSV 124 a .
  • the formation of vias and fill with conductive material to form conductive TMV 302 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • An insulating or passivation layer 306 is formed over encapsulant 300 and conductive layer 304 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation.
  • the insulating layer 306 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.
  • a portion of insulating layer 306 is removed by an etching process to expose conductive layer 304 for bump formation or external electrical interconnect.
  • Semiconductor die 282 and ISM 290 are electrically connected through conductive TMV 302 , TSV 124 , and conductive layer 304 .
  • a plurality of bumps 308 is formed over TSV 124 a and 124 b.

Abstract

A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV.

Description

    CLAIM TO DOMESTIC PRIORITY
  • The present application is a division of U.S. patent application Ser. No. 13/943,735, filed Jul. 16, 2013, which is a continuation of U.S. patent application Ser. No. 12/852,433, now U.S. Pat. No. 8,895,440, filed Aug. 6, 2010, which applications are incorporated herein by reference.
  • FIELD OF THE INVENTION
  • The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a vertical interconnect using TSV and TMV in fan-out wafer level chip scale package (Fo-WLCSP).
  • BACKGROUND OF THE INVENTION
  • Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
  • Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
  • Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
  • A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
  • Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
  • One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
  • Most if not all Fo-WLCSP require a z-direction electrical interconnect structure for signal routing and package integration. Conventional Fo-WLCSP z-direction electrical interconnect structures exhibit one or more limitations. In one example, a conventional Fo-WLCSP contains a flipchip semiconductor die and encapsulant formed over the semiconductor die. An interconnect structure is typically formed over the semiconductor die and encapsulant for z-direction vertical interconnect. The flipchip semiconductor die is electrically connected to the interconnect structure with bumps. The bump interconnect makes package stacking difficult to achieve. In addition, the bumps are susceptible to delamination, particularly for applications requiring a fine interconnect pitch.
  • Another Fo-WLCSP interconnect structure is shown in U.S. Pat. No. 7,528,009 ('009 patent). A portion of the bottom silicon layer is removed between adjacent semiconductor die. An insulating layer is formed in the removed silicon area. A portion of the insulating layer is removed and an electrically conductive material is deposited to form a relatively large z-direction electrical interconnect for the semiconductor die. The large interconnect structure described in the '009 patent increases the pitch of the interconnect and size of the package, which is counter to general miniaturization demands.
  • SUMMARY OF THE INVENTION
  • A need exists for a simple and cost effective Fo-WLCSP interconnect structure for applications requiring a fine interconnect pitch and vertical package integration. Accordingly, in one embodiment, the present invention is a semiconductor device comprising a substrate separated from a substrate panel. The substrate includes a first surface and a second surface opposite the first surface. A first semiconductor die is disposed over the first surface of the substrate. An encapsulant is deposited over the first semiconductor die and the first surface of the substrate to leave a peripheral ring of the encapsulant around an outer edge of the substrate after singulation through the encapsulant. An interconnect structure is formed over the second surface of the substrate.
  • In another embodiment, the present invention is a semiconductor device comprising a substrate including a first surface and a second surface opposite the first surface. A first semiconductor die is disposed over the first surface of the substrate. An encapsulant is deposited over the first semiconductor die and the first surface of the substrate to form an encapsulated assembly with the encapsulant disposed around an outer edge of the substrate.
  • In another embodiment, the present invention is a semiconductor device comprising a first substrate separated from a substrate panel. A second substrate is separated from the first substrate by a space. A first semiconductor die is disposed over the first substrate. An encapsulant is deposited over the first semiconductor die and in the space between the first and second substrates with the encapsulant disposed over an outer edge of the first and second substrates.
  • In another embodiment, the present invention is a semiconductor device comprising a substrate separated from a substrate panel. A semiconductor die is disposed over the substrate. An encapsulant is deposited over the semiconductor die with the encapsulant disposed around an outer edge of the substrate.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a PCB with different types of packages mounted to its surface;
  • FIGS. 2 a-2 c illustrate further detail of the representative semiconductor packages mounted to the PCB;
  • FIGS. 3 a-3 j illustrate a process of forming a vertical interconnect structure using TSV and TMV in a Fo-WLCSP;
  • FIG. 4 illustrates the Fo-WLCSP with a TSV and TMV vertical interconnect structure;
  • FIG. 5 illustrates stacked Fo-WLCSP each with a TSV and TMV vertical interconnect structure;
  • FIG. 6 illustrates another embodiment of stacked Fo-WLCSP each with a TSV and TMV vertical interconnect structure;
  • FIG. 7 illustrates the Fo-WLCSP with a TMV formed in the encapsulant channel;
  • FIG. 8 illustrates tiered stacking of different size Fo-WLCSP each with a TSV and TMV vertical interconnect structure;
  • FIG. 9 illustrates stacking of same size Fo-WLCSP each with a TSV and TMV vertical interconnect structure;
  • FIG. 10 illustrates stacking Fo-WLCSP on opposite sides of TSV wafer; and
  • FIG. 11 illustrates stacking an ISM and Fo-WLCSP with a TSV and TMV vertical interconnect structure.
  • DETAILED DESCRIPTION OF THE DRAWINGS
  • The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
  • Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.
  • Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.
  • Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.
  • The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.
  • Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.
  • Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation. To singulate the die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
  • FIG. 1 illustrates electronic device 50 having a chip carrier substrate or printed circuit board (PCB) 52 with a plurality of semiconductor packages mounted on its surface. Electronic device 50 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown in FIG. 1 for purposes of illustration.
  • Electronic device 50 may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 may be a subcomponent of a larger system. For example, electronic device 50 may be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. The miniaturization and the weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.
  • In FIG. 1, PCB 52 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces 54 are formed over a surface or within layers of PCB 52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 54 also provide power and ground connections to each of the semiconductor packages.
  • In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.
  • For the purpose of illustration, several types of first level packaging, including wire bond package 56 and flip chip 58, are shown on PCB 52. Additionally, several types of second level packaging, including ball grid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package (DIP) 64, land grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70, and quad flat package 72, are shown mounted on PCB 52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
  • FIGS. 2 a-2 c show exemplary semiconductor packages. FIG. 2 a illustrates further detail of DIP 64 mounted on PCB 52. Semiconductor die 74 includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die 74. Contact pads 76 are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die 74. During assembly of DIP 64, semiconductor die 74 is mounted to an intermediate carrier 78 using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads 80 and wire bonds 82 provide electrical interconnect between semiconductor die 74 and PCB 52. Encapsulant 84 is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die 74 or wire bonds 82.
  • FIG. 2 b illustrates further detail of BCC 62 mounted on PCB 52. Semiconductor die 88 is mounted over carrier 90 using an underfill or epoxy-resin adhesive material 92. Wire bonds 94 provide first level packaging interconnect between contact pads 96 and 98. Molding compound or encapsulant 100 is deposited over semiconductor die 88 and wire bonds 94 to provide physical support and electrical isolation for the device. Contact pads 102 are formed over a surface of PCB 52 using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads 102 are electrically connected to one or more conductive signal traces 54 in PCB 52. Bumps 104 are formed between contact pads 98 of BCC 62 and contact pads 102 of PCB 52.
  • In FIG. 2 c, semiconductor die 58 is mounted face down to intermediate carrier 106 with a flip chip style first level packaging. Active region 108 of semiconductor die 58 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region 108. Semiconductor die 58 is electrically and mechanically connected to carrier 106 through bumps 110.
  • BGA 60 is electrically and mechanically connected to PCB 52 with a BGA style second level packaging using bumps 112. Semiconductor die 58 is electrically connected to conductive signal traces 54 in PCB 52 through bumps 110, signal lines 114, and bumps 112. A molding compound or encapsulant 116 is deposited over semiconductor die 58 and carrier 106 to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die 58 to conduction tracks on PCB 52 in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can be mechanically and electrically connected directly to PCB 52 using flip chip style first level packaging without intermediate carrier 106.
  • FIGS. 3 a-3 j illustrate, in relation to FIGS. 1 and 2 a-2 c, a process of forming a vertical interconnect structure using TSV and TMV in a Fo-WLCSP. In FIG. 3 a, a substrate or carrier 120 contains temporary or sacrificial base material such as silicon, polymer, polymer composite, metal, ceramic, glass, glass epoxy, beryllium oxide, or other suitable low-cost, rigid material for structural support.
  • A semiconductor wafer 122 contains a base substrate material, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of vias is formed through semiconductor wafer 122 using mechanical drilling, laser drilling, or deep reactive ion etching (DRIE). The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction conductive through silicon vias (TSV) 124. TSV wafer 122-124 is mounted to carrier 120, as shown in FIG. 3 b.
  • In FIG. 3 c, a channel 126 is cut through semiconductor wafer 122 down to carrier 120 using saw blade or laser cutting tool 127 to create a plurality of TSV wafer portions or segments 128.
  • In FIG. 3 d, semiconductor die 130 has an active surface 132 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 132 to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die 130 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. In one embodiment, semiconductor die 130 is a flipchip type semiconductor die.
  • An electrically conductive layer 134 is formed over active surface 132 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 134 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 134 operates as contact pads electrically connected to the circuits on active surface 132.
  • Semiconductor die 130 are mounted to TSV wafer segments 128 with die attach adhesive 136. Semiconductor die 130 each have smaller footprint than TSV wafer segment 128. Accordingly, TSV 124 a around a perimeter of wafer segment 128 are outside the footprint of semiconductor die 130 and the remaining TSV 124 b are disposed under semiconductor die 130.
  • In FIG. 3 e, an encapsulant or molding compound 140 is deposited over carrier 120, semiconductor die 130, and TSV wafer segments 128, including into channel 126, using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 140 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 140 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • In FIG. 3 f, a plurality of vias 142 is formed through encapsulant 140 over TSV 124 a and contact pads 134 using mechanical drilling, laser drilling, mold chase, or DRIE. The vias 142 are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive through mold vias or pillars (TMV) 144, as shown in FIG. 3 g. Conductive TMV 144 a are electrically connected to TSV 124 a, and conductive TMV 144 b are electrically connected to contact pads 134. The formation of vias 142 and fill with conductive material to form conductive TMV 144 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • In FIG. 3 h, an electrically conductive layer or redistribution layer (RDL) 146 is formed over encapsulant 140 and conductive TMV 144 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 146 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 146 is electrically connected to conductive TMV 144 a and 144 b. Additional RDL 146 can be formed over encapsulant 140 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 130.
  • In FIG. 3 i, an insulating or passivation layer 148 is formed over encapsulant 140 and conductive layer 146 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer 148 can be one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties. A portion of insulating layer 148 is removed by an etching process to expose conductive layer 146 for bump formation or external electrical interconnect.
  • In FIG. 3 j, carrier 120 is removed by chemical etching, mechanical peel-off, CMP, mechanical grinding, thermal bake, laser scanning, wet stripping, UV light, or heat. An electrically conductive bump material is deposited over the exposed conductive layer 146 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 146 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps 150. In some applications, bumps 150 are reflowed a second time to improve electrical contact to conductive layer 146. An under bumps metallization (UBM) can be formed under bumps 150. The bumps can also be compression bonded to conductive layer 146. Bumps 150 represent one type of interconnect structure that can be formed over conductive layer 146. The interconnect structure can also use bond wires, stud bump, micro bump, or other electrical interconnect.
  • Semiconductor die 130 and encapsulant 140 is singulated using saw blade or laser cutting tool 152 to separate the individual semiconductor die 130 into Fo-WLCSP 154, as shown in FIG. 4. Semiconductor die 130 is electrically connected to conductive TMV 144 a and 144 b, conductive layer 146, and conductive TSV 124 a and 124 b in wafer segment 128. TSV 124 a and 124 b can be electrically common or electrically isolated depending on the design and function of semiconductor die 130. The combination of conductive TSV 124 and conductive TMV 144 provide a fine pitch z-direction electrical interconnect for semiconductor die 130, which reduces the size of Fo-WLCSP 154. TSV wafer segment 128 has a CTE similar to semiconductor die 130 to reduce thermal stress.
  • Fo-WLCSP 154 is suitable for package-on-package (PoP) or package-in-package (PiP) applications. FIG. 5 shows Fo-WLCSP 156 configured similar to Fo-WLCSP 154. Fo-WLCSP 156 is stacked over Fo-WLCSP 154 and electrically connected with bumps 158 formed between conductive layer 146 of Fo-WLCSP 154 and TSV 124 a of Fo-WLCSP 156. Accordingly, semiconductor die 130 in Fo- WLCSP 154 and 156 are electrically connected through conductive TSV 124, TMV 144, conductive layer 146, and bumps 158.
  • FIG. 6 shows an embodiment of Fo-WLCSP 159, similar to FIG. 4, with semiconductor die 160 mounted over insulating layer 148 with die attach adhesive 162. The stacked semiconductor die 130 and 160 increase the functional density of Fo-WLCSP 159. Semiconductor die 160 has an active surface 164 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 164 to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die 160 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. Contact pads 166 are formed on active surface 164 and electrically connected to the circuits on the active surface.
  • An encapsulant or molding compound 170 is deposited over semiconductor die 160 and insulating layer 148 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 170 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 170 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • A plurality of vias is formed through encapsulant 170 down to the exposed conductive layer 146 and contact pads 166 using mechanical drilling, laser drilling, mold chase, or DRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive TMV 172. Conductive TMV 172 a are electrically connected to conductive layer 146, and conductive TMV 172 b are electrically connected to contact pads 166. The formation of vias and fill with conductive material to form conductive TMV 172 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • An electrically conductive layer or RDL 174 is formed over encapsulant 170 and conductive TMV 172 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 174 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 174 is electrically connected to conductive TMV 172 a and 172 b. Additional RDL 174 can be formed over encapsulant 170 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 160.
  • An insulating or passivation layer 176 is formed over encapsulant 170 and conductive layer 174 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer 176 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer 176 is removed by an etching process to expose conductive layer 174 for bump formation or external electrical interconnect. Semiconductor die 130 and 160 are electrically connected through conductive TMV 144, TMV 172, TSV 124, and conductive layers 146 and 174.
  • FIG. 7 shows an embodiment of Fo-WLCSP 180, similar to FIG. 4, with conductive TMV 182 formed through encapsulant 140 in channel 126 between TSV wafer segments 128. A portion of insulating layer 148 is removed by an etching process to expose conductive TMV 182 for bump formation or external electrical interconnect.
  • FIG. 8 shows an embodiment of Fo-WLCSP 188, continuing from FIG. 3 d, with semiconductor die 190 mounted over semiconductor die 130 with die attach adhesive 192. Semiconductor die 130 and 190 are different in size and therefore stacked in a tiered arrangement. The tiered semiconductor die 130 and 190 increase the functional density of Fo-WLCSP 188. Semiconductor die 190 has an active surface 194 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 194 to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die 190 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing. Contact pads 196 are formed on active surface 194 and electrically connected to the circuits on the active surface.
  • An encapsulant or molding compound 200 is deposited over semiconductor die 130 and 190 and TSV wafer segment 128 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 200 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 200 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • A plurality of vias is formed through encapsulant 200 down to contact pads 134 and 196 and TSV 124 a using mechanical drilling, laser drilling, mold chase, or DRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive TMV 202. Conductive TMV 202 a are electrically connected to contact pads 196, conductive TMV 202 b are electrically connected to contact pads 134, and conductive TMV 202 c are electrically connected to TSV 124 a. The formation of vias and fill with conductive material to form conductive TMV 202 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • An electrically conductive layer or RDL 204 is formed over encapsulant 200 and conductive TMV 202 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 204 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 204 is electrically connected to conductive TMV 202 a and 202 b. Additional RDL 204 can be formed over encapsulant 200 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 130 and 190.
  • An insulating or passivation layer 206 is formed over encapsulant 200 and conductive layer 204 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer 206 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer 206 is removed by an etching process to expose conductive layer 204 and conductive vias 202 c for bump formation or external electrical interconnect. Semiconductor die 130 and 190 are electrically connected through conductive TMV 202, TSV 124, and conductive layer 204. A plurality of bumps 207 is formed over TSV 124 a and 124 b.
  • FIG. 9 shows an embodiment of Fo-WLCSP 208, continuing from FIG. 3 c, with semiconductor die 210 mounted over TSV wafer segment 128. In one embodiment, semiconductor die 210 is a flipchip type semiconductor die with bumps 212 formed between contact pads 216 and TSV 124 b. Contact pads 216 are formed on active surface 214 and electrically connected to the circuits on the active surface. Semiconductor die 220 is mounted back-to-back with semiconductor die 210 with die attach adhesive 222. Semiconductor die 210 and 220 are similar in size. The stacked semiconductor die 210 and 220 increase the functional density of Fo-WLCSP 208. Contact pads 226 are formed on active surface 224 of semiconductor die 220 and electrically connected to the circuits on the active surface. Semiconductor die 210 and 220 each have an active surface containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die 210 and 220 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.
  • An encapsulant or molding compound 230 is deposited over semiconductor die 210 and 220 and TSV wafer segment 128 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 230 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 230 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • A plurality of vias is formed through encapsulant 230 down to contact pads 226 and TSV 124 a using mechanical drilling, laser drilling, mold chase, or DRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive TMV 232. Conductive TMV 232 a are electrically connected to contact pads 226 and conductive TMV 232 b are electrically connected to TSV 124 a. The formation of vias and fill with conductive material to form conductive TMV 232 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • An electrically conductive layer or RDL 234 is formed over encapsulant 230 and conductive TMV 232 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 234 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 234 is electrically connected to conductive TMV 232 a and 232 b. Additional RDL 234 can be formed over encapsulant 230 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 210 and 220.
  • An insulating or passivation layer 236 is formed over encapsulant 230 and conductive layer 234 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer 236 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer 236 is removed by an etching process to expose conductive layer 234 for bump formation or external electrical interconnect. Semiconductor die 210 and 220 are electrically connected through conductive TMV 232, TSV 124, and conductive layer 234. A plurality of bumps 238 is formed over TSV 124 a and 124 b.
  • FIG. 10 shows an embodiment of Fo-WLCSP 240, continuing from FIG. 3 c, with semiconductor die 242 mounted over surface 244 of TSV wafer segment 128 with die attach adhesive layer 246. Contact pads 248 are formed on active surface 250 of semiconductor die 242 and electrically connected to the circuits on the active surface. Semiconductor die 252 is mounted over surface 254 of TSV wafer segment 128, opposite surface 244, with die attach adhesive layer 256. Contact pads 258 are formed on active surface 260 of semiconductor die 252 and electrically connected to the circuits on the active surface. The semiconductor die 242 and 252 stacked on opposite surfaces 244 and 254 of TSV wafer segment 128 increase the functional density of Fo-WLCSP 240. Semiconductor die 242 and 252 each have an active surface containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die 242 and 252 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.
  • An encapsulant or molding compound 262 is deposited over semiconductor die 242 and 252 and surfaces 244 and 254 of TSV wafer segment 128 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 262 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 262 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • A plurality of vias is formed through encapsulant 262 down to contact pads 248 and 258 and both sides of TSV 124 a using mechanical drilling, laser drilling, mold chase, or DRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive TMV 264 and 266. Conductive TMV 264 a are electrically connected to contact pads 248 and conductive TMV 264 b are electrically connected to one side of TSV 124 a. Conductive TMV 266 a are electrically connected to contact pads 258 and conductive TMV 266 b are electrically connected to an opposite side of TSV 124 a. The formation of vias and fill with conductive material to form conductive TMV 264 and 266 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • An electrically conductive layer or RDL 268 is formed over encapsulant 262 and conductive TMV 264 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 268 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 268 is electrically connected to conductive TMV 264 a and 264 b. Additional RDL 268 can be formed over encapsulant 262 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 242 and 252.
  • An insulating or passivation layer 270 is formed over encapsulant 262 and conductive layer 268 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer 270 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer 270 is removed by an etching process to expose conductive layer 268 for bump formation or external electrical interconnect. Semiconductor die 242 and 252 are electrically connected through conductive TMV 264, TMV 266, TSV 124, and conductive layer 268. A plurality of bumps 272 is formed over TMV 266 a and 266 b.
  • FIG. 11 shows an embodiment of Fo-WLCSP 280, continuing from FIG. 3 c, with semiconductor die 282 mounted over TSV wafer segment 128 with bumps 284. In one embodiment, semiconductor die 282 is a flipchip type semiconductor die with bumps 284 formed between contact pads 288 and TSV 124 b. Contact pads 288 are formed on active surface 286 and electrically connected to the circuits on the active surface. An internal stacking module (ISM) 290 is mounted to a back surface of semiconductor die 282 with die attach adhesive 291. ISM 290 contains semiconductor die 292 mounted to substrate 294 and electrically connected to conductive layers 295 in the substrate with bond wires 296. An encapsulant 298 is deposited over semiconductor die 292, substrate 294, and bond wires 296.
  • An encapsulant or molding compound 300 is deposited over semiconductor die 282, ISM 290, and TSV wafer segment 128 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 300 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 300 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.
  • A plurality of vias is formed through encapsulant 300 down to TSV 124 a using mechanical drilling, laser drilling, mold chase, or DRIE. The vias are filled with Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, screen printing, or other suitable metal deposition process to form z-direction conductive TMV 302. Conductive TMV 302 are electrically connected to TSV 124 a. The formation of vias and fill with conductive material to form conductive TMV 302 is performed during the same manufacturing step, which reduces cost in a mass production environment.
  • An electrically conductive layer or RDL 304 is formed over encapsulant 300 and conductive TMV 302 using patterning and screen printing, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 304 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 304 is electrically connected to conductive TMV 302 and substrate 294. Additional RDL 304 can be formed over encapsulant 300 in an electrically common or electrically isolated arrangement depending on the design and function of semiconductor die 282 and ISM 290.
  • An insulating or passivation layer 306 is formed over encapsulant 300 and conductive layer 304 by PVD, CVD, printing, spin coating, spray coating, or thermal oxidation. The insulating layer 306 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion of insulating layer 306 is removed by an etching process to expose conductive layer 304 for bump formation or external electrical interconnect. Semiconductor die 282 and ISM 290 are electrically connected through conductive TMV 302, TSV 124, and conductive layer 304. A plurality of bumps 308 is formed over TSV 124 a and 124 b.
  • While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims (25)

What is claimed:
1. A semiconductor device, comprising:
a substrate separated from a substrate panel, the substrate including a first surface and a second surface opposite the first surface;
a first semiconductor die disposed over the first surface of the substrate;
an encapsulant deposited over the first semiconductor die and the first surface of the substrate to leave a peripheral ring of the encapsulant around an outer edge of the substrate after singulation through the encapsulant; and
an interconnect structure formed over the second surface of the substrate.
2. The semiconductor device of claim 1, wherein the interconnect structure includes a bump.
3. The semiconductor device of claim 1, further including a plurality of bumps formed over the first semiconductor die and electrically connected to a conductive layer on the first surface of the substrate.
4. The semiconductor device of claim 1, further including a conductive layer formed over the substrate to provide electrical routing.
5. The semiconductor device of claim 1, further including a conductive via formed through the substrate.
6. The semiconductor device of claim 1, further including a second semiconductor die disposed over the substrate.
7. A semiconductor device, comprising:
a substrate including a first surface and a second surface opposite the first surface;
a first semiconductor die disposed over the first surface of the substrate; and
an encapsulant deposited over the first semiconductor die and the first surface of the substrate to form an encapsulated assembly with the encapsulant disposed around an outer edge of the substrate.
8. The semiconductor device of claim 7, further including a plurality of bumps formed over the first surface of the substrate.
9. The semiconductor device of claim 7, further including a conductive via formed through the substrate to provide electrical routing.
10. The semiconductor device of claim 7, further including a conductive layer formed over the first surface of the substrate.
11. The semiconductor device of claim 10, further including a plurality of stud bumps formed over the substrate and electrically connected to the conductive layer.
12. The semiconductor device of claim 7, wherein a peripheral ring of encapsulant remains from singulation of the encapsulated assembly through the encapsulant and the encapsulant covers the outer edge of the substrate entirely.
13. The semiconductor device of claim 7, further including a second semiconductor die disposed over the substrate.
14. A semiconductor device, comprising:
a first substrate separated from a substrate panel;
a second substrate separated from the first substrate by a space;
a first semiconductor die disposed over the first substrate; and
an encapsulant deposited over the first semiconductor die and in the space between the first and second substrates with the encapsulant disposed over an outer edge of the first and second substrates.
15. The semiconductor device of claim 14, further including a plurality of bumps disposed over a surface of the first substrate.
16. The semiconductor device of claim 14, further including a conductive via formed through the first substrate to provide electrical routing.
17. The semiconductor device of claim 14, further including a conductive layer formed over a surface of the first substrate.
18. The semiconductor device of claim 17, further including a plurality of stud bumps formed over the first substrate and electrically connected to the conductive layer on the surface of the first substrate.
19. The semiconductor device of claim 14, further including a second semiconductor die disposed over the second substrate.
20. A semiconductor device, comprising:
a substrate separated from a substrate panel;
a semiconductor die disposed over the substrate; and
an encapsulant deposited over the semiconductor die with the encapsulant disposed around an outer edge of the substrate.
21. The semiconductor device of claim 20, further including an interconnect structure formed between the semiconductor die and substrate.
22. The semiconductor device of claim 20, further including a conductive layer formed over a surface of the substrate.
23. The semiconductor device of claim 22, further including a plurality of bumps or stud bumps formed over the substrate and electrically connected to the conductive layer.
24. The semiconductor device of claim 20, further including a conductive via formed through the substrate to provide electrical routing through the substrate.
25. The semiconductor device of claim 20, further including a conductive via formed through the encapsulant and extending to the substrate.
US14/832,644 2010-08-06 2015-08-21 Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV Abandoned US20150357274A1 (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150206863A1 (en) * 2014-01-21 2015-07-23 International Business Machines Corporation Semiconductor TSV device package to which other semiconductor device package can be later attached
US20150235919A1 (en) * 2012-07-24 2015-08-20 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component having an electrically insulating element
US20190371694A1 (en) * 2018-05-30 2019-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and methods of forming the same
US20200091026A1 (en) * 2018-09-13 2020-03-19 Dialog Semiconductor (Uk) Limited Wafer Level Chip Scale Package Structure
EP3712623A1 (en) * 2019-03-22 2020-09-23 Melexis Technologies SA Current sensor
CN112992956A (en) * 2021-05-17 2021-06-18 甬矽电子(宁波)股份有限公司 Chip packaging structure, chip packaging method and electronic equipment
US20220108967A1 (en) * 2017-06-30 2022-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure

Families Citing this family (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US9171769B2 (en) * 2010-12-06 2015-10-27 Stats Chippac, Ltd. Semiconductor device and method of forming openings through encapsulant to reduce warpage and stress on semiconductor package
US20120187545A1 (en) * 2011-01-24 2012-07-26 Broadcom Corporation Direct through via wafer level fanout package
JP5750937B2 (en) * 2011-02-25 2015-07-22 富士通株式会社 Semiconductor device and manufacturing method thereof
US9324659B2 (en) * 2011-08-01 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die
US8698297B2 (en) * 2011-09-23 2014-04-15 Stats Chippac Ltd. Integrated circuit packaging system with stack device
US8803322B2 (en) 2011-10-13 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through substrate via structures and methods of forming the same
US20130154106A1 (en) * 2011-12-14 2013-06-20 Broadcom Corporation Stacked Packaging Using Reconstituted Wafers
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9263412B2 (en) * 2012-03-09 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged semiconductor devices
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US20130297981A1 (en) * 2012-05-01 2013-11-07 Qualcomm Incorporated Low cost high throughput tsv/microbump probe
US10153179B2 (en) 2012-08-24 2018-12-11 Taiwan Semiconductor Manufacturing Company Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
DE102013104111B4 (en) 2012-08-24 2018-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. A method of forming a package-on-package (PoP) device having a carrier discard control for three-dimensionally integrated circuit (3DIC) stacking
US9111896B2 (en) 2012-08-24 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package semiconductor device
US8872326B2 (en) 2012-08-29 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional (3D) fan-out packaging mechanisms
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9443797B2 (en) 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9391041B2 (en) * 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US9275969B2 (en) * 2012-12-17 2016-03-01 Intel Corporation Optical interconnect on bumpless build-up layer package
US8729714B1 (en) 2012-12-31 2014-05-20 Intel Mobile Communications GmbH Flip-chip wafer level package and methods thereof
US9041212B2 (en) 2013-03-06 2015-05-26 Qualcomm Incorporated Thermal design and electrical routing for multiple stacked packages using through via insert (TVI)
US8786069B1 (en) 2013-03-15 2014-07-22 Invensas Corporation Reconfigurable pop
TWI555166B (en) * 2013-06-18 2016-10-21 矽品精密工業股份有限公司 Stack package and method of manufacture
KR102099878B1 (en) * 2013-07-11 2020-04-10 삼성전자 주식회사 Semiconductor Package
CN103400823A (en) * 2013-07-30 2013-11-20 华进半导体封装先导技术研发中心有限公司 Fine spacing laminated packaging structure containing copper pillar and packaging method
US9159701B2 (en) * 2013-09-17 2015-10-13 Infineon Technologies Ag Method of manufacturing a chip package, chip package, method of manufacturing a chip assembly and chip assembly
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
DE102013222200A1 (en) * 2013-10-31 2015-08-27 Osram Opto Semiconductors Gmbh Electronic component and method for manufacturing an electronic component
KR101631934B1 (en) * 2013-11-13 2016-06-21 앰코 테크놀로지 코리아 주식회사 Semiconductor package structure and manufacturing method thereof
TWI608564B (en) * 2013-12-10 2017-12-11 艾馬克科技公司 Semiconductor device
US9524942B2 (en) 2013-12-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-substrate packaging on carrier
US9299677B2 (en) * 2013-12-31 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package with multiple plane I/O structure
US9349680B2 (en) * 2014-01-05 2016-05-24 Infineon Technologies Austria Ag Chip arrangement and method of manufacturing the same
CN103730379A (en) * 2014-01-16 2014-04-16 苏州晶方半导体科技股份有限公司 Chip packaging method and structure
JP6320799B2 (en) * 2014-03-07 2018-05-09 住友重機械工業株式会社 Manufacturing method of semiconductor device
US9209110B2 (en) 2014-05-07 2015-12-08 Qualcomm Incorporated Integrated device comprising wires as vias in an encapsulation layer
TWI560815B (en) * 2014-05-09 2016-12-01 Siliconware Precision Industries Co Ltd Semiconductor packages, methods for fabricating the same and carrier structures
US20150340308A1 (en) * 2014-05-21 2015-11-26 Broadcom Corporation Reconstituted interposer semiconductor package
US9595485B2 (en) * 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
WO2016025478A1 (en) * 2014-08-11 2016-02-18 Massachusetts Institute Of Technology Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure
TWI584387B (en) * 2014-08-15 2017-05-21 矽品精密工業股份有限公司 Method of manufacturing package structure
KR101563909B1 (en) * 2014-08-19 2015-10-28 앰코 테크놀로지 코리아 주식회사 Method for manufacturing Package On Package
US10177115B2 (en) 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
CN104538375A (en) * 2014-12-30 2015-04-22 华天科技(西安)有限公司 Fan-out PoP packaging structure and manufacturing method thereof
KR102265243B1 (en) * 2015-01-08 2021-06-17 삼성전자주식회사 Semiconductor Package and method for manufacturing the same
CN104835808A (en) * 2015-03-16 2015-08-12 苏州晶方半导体科技股份有限公司 Chip packaging method and chip packaging structure
US9564419B2 (en) 2015-03-26 2017-02-07 Macronix International Co., Ltd. Semiconductor package structure and method for manufacturing the same
TWI587449B (en) * 2015-03-26 2017-06-11 旺宏電子股份有限公司 Semiconductor package structure and method for manufacturing the same
CN106158775A (en) * 2015-03-31 2016-11-23 旺宏电子股份有限公司 Semiconductor package and manufacture method thereof
US9601471B2 (en) * 2015-04-23 2017-03-21 Apple Inc. Three layer stack structure
US10424563B2 (en) * 2015-05-19 2019-09-24 Mediatek Inc. Semiconductor package assembly and method for forming the same
JP6421083B2 (en) * 2015-06-15 2018-11-07 株式会社東芝 Manufacturing method of semiconductor device
US10134972B2 (en) 2015-07-23 2018-11-20 Massachusetts Institute Of Technology Qubit and coupler circuit structures and coupling techniques
WO2017015432A1 (en) 2015-07-23 2017-01-26 Massachusetts Institute Of Technology Superconducting integrated circuit
CN106486453A (en) * 2015-08-25 2017-03-08 力成科技股份有限公司 A kind of capital interconnection kenel semiconductor packaging structure and its manufacture method
US9905436B2 (en) 2015-09-24 2018-02-27 Sts Semiconductor & Telecommunications Co., Ltd. Wafer level fan-out package and method for manufacturing the same
US9524959B1 (en) 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
WO2017079424A1 (en) 2015-11-05 2017-05-11 Massachusetts Institute Of Technology Shielded through via structures and methods for fabricating shielded through via structures
US10242968B2 (en) 2015-11-05 2019-03-26 Massachusetts Institute Of Technology Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages
JP6584939B2 (en) * 2015-12-10 2019-10-02 新光電気工業株式会社 Wiring board, semiconductor package, semiconductor device, wiring board manufacturing method, and semiconductor package manufacturing method
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
DE102016107792B4 (en) * 2016-04-27 2022-01-27 Infineon Technologies Ag Pack and semi-finished product with a vertical connection between support and bracket and method of making a pack and a batch of packs
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10727207B2 (en) 2016-07-07 2020-07-28 Agency For Science, Technology And Research Semiconductor packaging structure and method of forming the same
US10381541B2 (en) 2016-10-11 2019-08-13 Massachusetts Institute Of Technology Cryogenic electronic packages and methods for fabricating cryogenic electronic packages
US9935079B1 (en) 2016-12-08 2018-04-03 Nxp Usa, Inc. Laser sintered interconnections between die
DE102016124270A1 (en) * 2016-12-13 2018-06-14 Infineon Technologies Ag SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE
CN108288616B (en) 2016-12-14 2023-04-07 成真股份有限公司 Chip package
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
CN109300794B (en) * 2017-07-25 2021-02-02 中芯国际集成电路制造(上海)有限公司 Package structure and method for forming the same
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
TWI699012B (en) * 2018-02-21 2020-07-11 華立捷科技股份有限公司 Package structure and package method of a light-emitting chip
US10356903B1 (en) 2018-03-28 2019-07-16 Apple Inc. System-in-package including opposing circuit boards
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10930633B2 (en) * 2018-06-29 2021-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer design for package integration
US20200035629A1 (en) * 2018-07-26 2020-01-30 Nanya Technology Corporation Packaged semiconductor device and method for preparing the same
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US11476200B2 (en) * 2018-12-20 2022-10-18 Nanya Technology Corporation Semiconductor package structure having stacked die structure
CN110027123B (en) * 2018-12-27 2021-03-16 李宗杰 Quartz photoetching wafer and cutting technology
US10867966B2 (en) * 2019-04-29 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure, package-on-package structure and method of fabricating the same
JP7406314B2 (en) * 2019-06-24 2023-12-27 キヤノン株式会社 electronic modules and equipment
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10602612B1 (en) 2019-07-15 2020-03-24 Apple Inc. Vertical module and perpendicular pin array interconnect for stacked circuit board structure
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11264358B2 (en) 2019-09-11 2022-03-01 Google Llc ASIC package with photonics and vertical power delivery
US11410902B2 (en) * 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11145627B2 (en) 2019-10-04 2021-10-12 Winbond Electronics Corp. Semiconductor package and manufacturing method thereof
US11502024B2 (en) * 2020-01-21 2022-11-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11276668B2 (en) 2020-02-12 2022-03-15 Google Llc Backside integrated voltage regulator for integrated circuits
US11342282B2 (en) * 2020-02-21 2022-05-24 Advanced Semiconductor Engineering, Inc. Semiconductor device package including a reinforcement structure on an electronic component and method of manufacturing the same
US11289130B2 (en) 2020-08-20 2022-03-29 Macronix International Co., Ltd. Memory device
US11557565B2 (en) 2020-10-06 2023-01-17 Nxp Usa, Inc. Semiconductor device assembly and method therefor
TWI749860B (en) * 2020-11-10 2021-12-11 菱生精密工業股份有限公司 Chip packaging method
US11502054B2 (en) 2020-11-11 2022-11-15 Nxp Usa, Inc. Semiconductor device assembly and method therefor

Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030116836A1 (en) * 2001-12-21 2003-06-26 Siliconware Precision Industries Co., Ltd. Semiconductor package with enhanced electrical and thermal performance and method for fabricating the same
US20040070064A1 (en) * 2002-10-15 2004-04-15 Tae Yamane Semiconductor device and fabrication method of the same
US20040119166A1 (en) * 2002-11-05 2004-06-24 Masahiro Sunohara Semiconductor device and method of manufacturing the same
US20040183192A1 (en) * 2003-01-31 2004-09-23 Masashi Otsuka Semiconductor device assembled into a chip size package
US20070059862A1 (en) * 2002-08-27 2007-03-15 Eng Meow K Multiple chip semiconductor package
US20070176298A1 (en) * 2006-01-11 2007-08-02 Hitachi, Ltd. Semiconductor device
US20070197018A1 (en) * 2004-07-23 2007-08-23 Industrial Technology Research Institute Wafer-leveled chip packaging structure and method thereof
US20070218593A1 (en) * 2006-03-14 2007-09-20 Disco Corporation Method for producing semiconductor package
US20080246126A1 (en) * 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
US20080315372A1 (en) * 2007-06-20 2008-12-25 Stats Chippac, Ltd. Wafer Level Integration Package
US7521283B2 (en) * 2004-12-07 2009-04-21 Shinko Electric Industries Co., Ltd. Manufacturing method of chip integrated substrate
US7550833B2 (en) * 2004-12-14 2009-06-23 Casio Computer Co., Ltd. Semiconductor device having a second semiconductor construction mounted on a first semiconductor construction and a manufacturing method thereof
US20090303690A1 (en) * 2008-06-09 2009-12-10 Sang-Ho Lee Integrated circuit package system for stackable devices
US20100078789A1 (en) * 2008-09-26 2010-04-01 Daesik Choi Semiconductor package system with through silicon via interposer
US7750451B2 (en) * 2007-02-07 2010-07-06 Stats Chippac Ltd. Multi-chip package system with multiple substrates
US7825520B1 (en) * 2006-11-16 2010-11-02 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US20110018119A1 (en) * 2009-07-21 2011-01-27 Samsung Electronics Co., Ltd. Semiconductor packages including heat slugs
US20120032340A1 (en) * 2010-08-06 2012-02-09 Stats Chippac, Ltd. Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
US8341835B1 (en) * 2002-05-01 2013-01-01 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
US8368187B2 (en) * 2010-02-03 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming air gap adjacent to stress sensitive region of the die
US8455995B2 (en) * 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US6429530B1 (en) 1998-11-02 2002-08-06 International Business Machines Corporation Miniaturized chip scale ball grid array semiconductor package
US6204562B1 (en) 1999-02-11 2001-03-20 United Microelectronics Corp. Wafer-level chip scale package
JP4251421B2 (en) * 2000-01-13 2009-04-08 新光電気工業株式会社 Manufacturing method of semiconductor device
JP3701542B2 (en) 2000-05-10 2005-09-28 シャープ株式会社 Semiconductor device and manufacturing method thereof
US6452278B1 (en) * 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6492726B1 (en) * 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
WO2002082540A1 (en) * 2001-03-30 2002-10-17 Fujitsu Limited Semiconductor device, method of manufacture thereof, and semiconductor substrate
US6930256B1 (en) * 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
DE10231385B4 (en) * 2001-07-10 2007-02-22 Samsung Electronics Co., Ltd., Suwon Semiconductor chip with bond pads and associated multi-chip package
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7723210B2 (en) * 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
DE10320646A1 (en) * 2003-05-07 2004-09-16 Infineon Technologies Ag Electronic component, typically integrated circuit, system support and manufacturing method, with support containing component positions in lines and columns, starting with coating auxiliary support with photosensitive layer
JP2005277356A (en) * 2004-03-26 2005-10-06 Sanyo Electric Co Ltd Circuit device
JP4298559B2 (en) * 2004-03-29 2009-07-22 新光電気工業株式会社 Electronic component mounting structure and manufacturing method thereof
JP4361826B2 (en) * 2004-04-20 2009-11-11 新光電気工業株式会社 Semiconductor device
JP2006019441A (en) * 2004-06-30 2006-01-19 Shinko Electric Ind Co Ltd Method of manufacturing substrate with built-in electronic substrate
JP4575071B2 (en) * 2004-08-02 2010-11-04 新光電気工業株式会社 Manufacturing method of electronic component built-in substrate
JP2006059992A (en) * 2004-08-19 2006-03-02 Shinko Electric Ind Co Ltd Method for manufacturing electronic component built-in board
US7629674B1 (en) * 2004-11-17 2009-12-08 Amkor Technology, Inc. Shielded package having shield fence
JP2006216911A (en) * 2005-02-07 2006-08-17 Renesas Technology Corp Semiconductor device and encapsulated semiconductor package
US7763963B2 (en) * 2005-05-04 2010-07-27 Stats Chippac Ltd. Stacked package semiconductor module having packages stacked in a cavity in the module substrate
KR100688560B1 (en) 2005-07-22 2007-03-02 삼성전자주식회사 Wafer level chip scale package and manufacturing method thereof
US8012867B2 (en) 2006-01-31 2011-09-06 Stats Chippac Ltd Wafer level chip scale package system
JP4877626B2 (en) 2006-02-16 2012-02-15 株式会社テラミクロス Manufacturing method of semiconductor device
US7710735B2 (en) 2006-04-01 2010-05-04 Stats Chippac Ltd. Multichip package system
TW200820402A (en) * 2006-10-26 2008-05-01 Chipmos Technologies Inc Stacked chip packaging with heat sink struct
DE102006058068B4 (en) * 2006-12-07 2018-04-05 Infineon Technologies Ag Semiconductor component with semiconductor chip and passive coil component and method for its production
US7612444B2 (en) * 2007-01-05 2009-11-03 Stats Chippac, Inc. Semiconductor package with flow controller
US7960210B2 (en) * 2007-04-23 2011-06-14 Cufer Asset Ltd. L.L.C. Ultra-thin chip packaging
US7923645B1 (en) * 2007-06-20 2011-04-12 Amkor Technology, Inc. Metal etch stop fabrication method and structure
US7830000B2 (en) * 2007-06-25 2010-11-09 Epic Technologies, Inc. Integrated thermal structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
SG148901A1 (en) * 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
US8225503B2 (en) * 2008-02-11 2012-07-24 Ibiden Co., Ltd. Method for manufacturing board with built-in electronic elements
US7838967B2 (en) * 2008-04-24 2010-11-23 Powertech Technology Inc. Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips
US7704796B2 (en) * 2008-06-04 2010-04-27 Stats Chippac, Ltd. Semiconductor device and method of forming recessed conductive vias in saw streets
US8101460B2 (en) * 2008-06-04 2012-01-24 Stats Chippac, Ltd. Semiconductor device and method of shielding semiconductor die from inter-device interference
US7851893B2 (en) * 2008-06-10 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of connecting a shielding layer to ground through conductive vias
US7618846B1 (en) * 2008-06-16 2009-11-17 Stats Chippac, Ltd. Semiconductor device and method of forming shielding along a profile disposed in peripheral region around the device
SG158823A1 (en) * 2008-07-18 2010-02-26 United Test & Assembly Ct Ltd Packaging structural member
US8674482B2 (en) * 2008-11-18 2014-03-18 Hong Kong Applied Science And Technology Research Institute Co. Ltd. Semiconductor chip with through-silicon-via and sidewall pad
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8093711B2 (en) * 2009-02-02 2012-01-10 Infineon Technologies Ag Semiconductor device
US7960827B1 (en) * 2009-04-09 2011-06-14 Amkor Technology, Inc. Thermal via heat spreader package and method
US8471154B1 (en) * 2009-08-06 2013-06-25 Amkor Technology, Inc. Stackable variable height via package and method
US8367470B2 (en) * 2009-08-07 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die
US8076762B2 (en) * 2009-08-13 2011-12-13 Qualcomm Incorporated Variable feature interface that induces a balanced stress to prevent thin die warpage
US9922955B2 (en) 2010-03-04 2018-03-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSP
US8258012B2 (en) * 2010-05-14 2012-09-04 Stats Chippac, Ltd. Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
US8357564B2 (en) * 2010-05-17 2013-01-22 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die
US8236617B2 (en) * 2010-06-04 2012-08-07 Stats Chippac, Ltd. Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structure
US8183130B2 (en) * 2010-06-15 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer around back surface and sides of semiconductor wafer containing IPD structure
US8097490B1 (en) * 2010-08-27 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
US8273604B2 (en) * 2011-02-22 2012-09-25 STAT ChipPAC, Ltd. Semiconductor device and method of forming WLCSP structure using protruded MLP

Patent Citations (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030116836A1 (en) * 2001-12-21 2003-06-26 Siliconware Precision Industries Co., Ltd. Semiconductor package with enhanced electrical and thermal performance and method for fabricating the same
US8341835B1 (en) * 2002-05-01 2013-01-01 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
US20070059862A1 (en) * 2002-08-27 2007-03-15 Eng Meow K Multiple chip semiconductor package
US20040070064A1 (en) * 2002-10-15 2004-04-15 Tae Yamane Semiconductor device and fabrication method of the same
US20040119166A1 (en) * 2002-11-05 2004-06-24 Masahiro Sunohara Semiconductor device and method of manufacturing the same
US20040183192A1 (en) * 2003-01-31 2004-09-23 Masashi Otsuka Semiconductor device assembled into a chip size package
US20070197018A1 (en) * 2004-07-23 2007-08-23 Industrial Technology Research Institute Wafer-leveled chip packaging structure and method thereof
US7528009B2 (en) * 2004-07-23 2009-05-05 Industrial Technology Research Institute Wafer-leveled chip packaging structure and method thereof
US7521283B2 (en) * 2004-12-07 2009-04-21 Shinko Electric Industries Co., Ltd. Manufacturing method of chip integrated substrate
US7550833B2 (en) * 2004-12-14 2009-06-23 Casio Computer Co., Ltd. Semiconductor device having a second semiconductor construction mounted on a first semiconductor construction and a manufacturing method thereof
US20070176298A1 (en) * 2006-01-11 2007-08-02 Hitachi, Ltd. Semiconductor device
US7656030B2 (en) * 2006-01-11 2010-02-02 Renesas Technology Corp. Semiconductor device
US7608481B2 (en) * 2006-03-14 2009-10-27 Disco Corporation Method for producing semiconductor package
US20070218593A1 (en) * 2006-03-14 2007-09-20 Disco Corporation Method for producing semiconductor package
US7825520B1 (en) * 2006-11-16 2010-11-02 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US7750451B2 (en) * 2007-02-07 2010-07-06 Stats Chippac Ltd. Multi-chip package system with multiple substrates
US20080246126A1 (en) * 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
US20080315372A1 (en) * 2007-06-20 2008-12-25 Stats Chippac, Ltd. Wafer Level Integration Package
US7553752B2 (en) * 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
US7843042B2 (en) * 2007-06-20 2010-11-30 Stats Chippac, Ltd. Wafer level integration package
US8189344B2 (en) * 2008-06-09 2012-05-29 Stats Chippac Ltd. Integrated circuit package system for stackable devices
US20090303690A1 (en) * 2008-06-09 2009-12-10 Sang-Ho Lee Integrated circuit package system for stackable devices
US20100078789A1 (en) * 2008-09-26 2010-04-01 Daesik Choi Semiconductor package system with through silicon via interposer
US8063475B2 (en) * 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
US20110018119A1 (en) * 2009-07-21 2011-01-27 Samsung Electronics Co., Ltd. Semiconductor packages including heat slugs
US8368187B2 (en) * 2010-02-03 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming air gap adjacent to stress sensitive region of the die
US8455995B2 (en) * 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
US20120032340A1 (en) * 2010-08-06 2012-02-09 Stats Chippac, Ltd. Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
US20130299973A1 (en) * 2010-08-06 2013-11-14 Stats Chippac, Ltd. Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150235919A1 (en) * 2012-07-24 2015-08-20 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component having an electrically insulating element
US9691682B2 (en) * 2012-07-24 2017-06-27 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component having an electrically insulating element
US9721852B2 (en) * 2014-01-21 2017-08-01 International Business Machines Corporation Semiconductor TSV device package to which other semiconductor device package can be later attached
US9818653B2 (en) 2014-01-21 2017-11-14 International Business Machines Corporation Semiconductor TSV device package to which other semiconductor device package can be later attached
US20150206863A1 (en) * 2014-01-21 2015-07-23 International Business Machines Corporation Semiconductor TSV device package to which other semiconductor device package can be later attached
US20220108967A1 (en) * 2017-06-30 2022-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure
US11791301B2 (en) * 2017-06-30 2023-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure
US20190371694A1 (en) * 2018-05-30 2019-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and methods of forming the same
US10748831B2 (en) * 2018-05-30 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages having thermal through vias (TTV)
US20200091026A1 (en) * 2018-09-13 2020-03-19 Dialog Semiconductor (Uk) Limited Wafer Level Chip Scale Package Structure
US11114359B2 (en) * 2018-09-13 2021-09-07 Dialog Semiconductor (Uk) Limited Wafer level chip scale package structure
EP3712623A1 (en) * 2019-03-22 2020-09-23 Melexis Technologies SA Current sensor
CN112992956A (en) * 2021-05-17 2021-06-18 甬矽电子(宁波)股份有限公司 Chip packaging structure, chip packaging method and electronic equipment

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